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体验新版 GitCode,发现更多精彩内容 >>
提交
40df6b3e
编写于
4月 17, 2018
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge
git://git.denx.de/u-boot-socfpga
上级
f4df1f76
f369e156
变更
25
隐藏空白更改
内联
并排
Showing
25 changed file
with
802 addition
and
0 deletion
+802
-0
arch/arm/dts/Makefile
arch/arm/dts/Makefile
+1
-0
arch/arm/dts/socfpga.dtsi
arch/arm/dts/socfpga.dtsi
+12
-0
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
+12
-0
arch/arm/dts/socfpga_stratix10.dtsi
arch/arm/dts/socfpga_stratix10.dtsi
+381
-0
arch/arm/dts/socfpga_stratix10_socdk.dts
arch/arm/dts/socfpga_stratix10_socdk.dts
+92
-0
arch/arm/mach-socfpga/include/mach/base_addr_s10.h
arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+33
-0
configs/socfpga_arria10_defconfig
configs/socfpga_arria10_defconfig
+2
-0
configs/socfpga_arria5_defconfig
configs/socfpga_arria5_defconfig
+4
-0
configs/socfpga_cyclone5_defconfig
configs/socfpga_cyclone5_defconfig
+4
-0
configs/socfpga_dbm_soc1_defconfig
configs/socfpga_dbm_soc1_defconfig
+4
-0
configs/socfpga_de0_nano_soc_defconfig
configs/socfpga_de0_nano_soc_defconfig
+4
-0
configs/socfpga_de10_nano_defconfig
configs/socfpga_de10_nano_defconfig
+4
-0
configs/socfpga_de1_soc_defconfig
configs/socfpga_de1_soc_defconfig
+4
-0
configs/socfpga_is1_defconfig
configs/socfpga_is1_defconfig
+4
-0
configs/socfpga_mcvevk_defconfig
configs/socfpga_mcvevk_defconfig
+4
-0
configs/socfpga_sockit_defconfig
configs/socfpga_sockit_defconfig
+4
-0
configs/socfpga_socrates_defconfig
configs/socfpga_socrates_defconfig
+4
-0
configs/socfpga_sr1500_defconfig
configs/socfpga_sr1500_defconfig
+4
-0
configs/socfpga_vining_fpga_defconfig
configs/socfpga_vining_fpga_defconfig
+3
-0
drivers/i2c/designware_i2c.c
drivers/i2c/designware_i2c.c
+10
-0
drivers/reset/Kconfig
drivers/reset/Kconfig
+7
-0
drivers/reset/Makefile
drivers/reset/Makefile
+1
-0
drivers/reset/reset-socfpga.c
drivers/reset/reset-socfpga.c
+105
-0
include/configs/socfpga_common.h
include/configs/socfpga_common.h
+2
-0
include/dt-bindings/reset/altr,rst-mgr-s10.h
include/dt-bindings/reset/altr,rst-mgr-s10.h
+97
-0
未找到文件。
arch/arm/dts/Makefile
浏览文件 @
40df6b3e
...
...
@@ -193,6 +193,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_sockit.dtb
\
socfpga_cyclone5_socrates.dtb
\
socfpga_cyclone5_sr1500.dtb
\
socfpga_stratix10_socdk.dtb
\
socfpga_cyclone5_vining_fpga.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM)
+=
dra72-evm.dtb dra7-evm.dtb
\
...
...
arch/arm/dts/socfpga.dtsi
浏览文件 @
40df6b3e
...
...
@@ -14,6 +14,10 @@
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
serial0 = &uart0;
serial1 = &uart1;
timer0 = &timer0;
...
...
@@ -505,6 +509,8 @@
compatible = "snps,designware-i2c";
reg = <0xffc04000 0x1000>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C0_RESET>;
reset-names = "i2c";
interrupts = <0 158 0x4>;
status = "disabled";
};
...
...
@@ -515,6 +521,8 @@
compatible = "snps,designware-i2c";
reg = <0xffc05000 0x1000>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C1_RESET>;
reset-names = "i2c";
interrupts = <0 159 0x4>;
status = "disabled";
};
...
...
@@ -525,6 +533,8 @@
compatible = "snps,designware-i2c";
reg = <0xffc06000 0x1000>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C2_RESET>;
reset-names = "i2c";
interrupts = <0 160 0x4>;
status = "disabled";
};
...
...
@@ -535,6 +545,8 @@
compatible = "snps,designware-i2c";
reg = <0xffc07000 0x1000>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C3_RESET>;
reset-names = "i2c";
interrupts = <0 161 0x4>;
status = "disabled";
};
...
...
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
浏览文件 @
40df6b3e
...
...
@@ -56,6 +56,18 @@
status
=
"okay"
;
};
&
i2c0
{
status
=
"okay"
;
dxl345
:
adxl345
@
0
{
compatible
=
"adi,adxl345"
;
reg
=
<
0x53
>;
interrupt
-
parent
=
<&
portc
>;
interrupts
=
<
3
2
>;
};
};
&
mmc0
{
status
=
"okay"
;
u
-
boot
,
dm
-
pre
-
reloc
;
...
...
arch/arm/dts/socfpga_stratix10.dtsi
0 → 100644
浏览文件 @
40df6b3e
/*
* Copyright (C) 2018 Intel Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "altr,socfpga-stratix10";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 120 8>,
<0 121 8>,
<0 122 8>,
<0 123 8>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
interrupt-parent = <&intc>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
intc: intc@fffc1000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0xfffc1000 0x0 0x1000>,
<0x0 0xfffc2000 0x0 0x2000>,
<0x0 0xfffc4000 0x0 0x2000>,
<0x0 0xfffc6000 0x0 0x2000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
device_type = "soc";
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
clkmgr@ffd1000 {
compatible = "altr,clk-mgr";
reg = <0xffd10000 0x1000>;
};
gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>;
interrupts = <0 90 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
gmac1: ethernet@ff802000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff802000 0x2000>;
interrupts = <0 91 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
gmac2: ethernet@ff804000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff804000 0x2000>;
interrupts = <0 92 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC2_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
gpio0: gpio@ffc03200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03200 0x100>;
resets = <&rst GPIO0_RESET>;
status = "disabled";
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <24>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 110 4>;
};
};
gpio1: gpio@ffc03300 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03300 0x100>;
resets = <&rst GPIO1_RESET>;
status = "disabled";
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <24>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 111 4>;
};
};
i2c0: i2c@ffc02800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02800 0x100>;
interrupts = <0 103 4>;
resets = <&rst I2C0_RESET>;
status = "disabled";
};
i2c1: i2c@ffc02900 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02900 0x100>;
interrupts = <0 104 4>;
resets = <&rst I2C1_RESET>;
status = "disabled";
};
i2c2: i2c@ffc02a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02a00 0x100>;
interrupts = <0 105 4>;
resets = <&rst I2C2_RESET>;
status = "disabled";
};
i2c3: i2c@ffc02b00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02b00 0x100>;
interrupts = <0 106 4>;
resets = <&rst I2C3_RESET>;
status = "disabled";
};
i2c4: i2c@ffc02c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02c00 0x100>;
interrupts = <0 107 4>;
resets = <&rst I2C4_RESET>;
status = "disabled";
};
mmc: dwmmc0@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
reg = <0xff808000 0x1000>;
interrupts = <0 96 4>;
fifo-depth = <0x400>;
resets = <&rst SDMMC_RESET>;
reset-names = "reset";
status = "disabled";
};
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x100000>;
};
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd11000 0x1000>;
altr,modrst-offset = <0x20>;
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
interrupts = <0 99 4>;
resets = <&rst SPIM0_RESET>;
reg-io-width = <4>;
num-chipselect = <4>;
bus-num = <0>;
status = "disabled";
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;
interrupts = <0 100 4>;
resets = <&rst SPIM1_RESET>;
reg-io-width = <4>;
num-chipselect = <4>;
bus-num = <0>;
status = "disabled";
};
sysmgr: sysmgr@ffd12000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd12000 0x1000>;
};
/* Local timer */
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
timer0: timer0@ffc03000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 113 4>;
reg = <0xffc03000 0x100>;
};
timer1: timer1@ffc03100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 114 4>;
reg = <0xffc03100 0x100>;
};
timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 115 4>;
reg = <0xffd00000 0x100>;
};
timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 116 4>;
reg = <0xffd00100 0x100>;
};
uart0: serial0@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x100>;
interrupts = <0 108 4>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART0_RESET>;
status = "disabled";
};
uart1: serial1@ffc02100 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02100 0x100>;
interrupts = <0 109 4>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART1_RESET>;
status = "disabled";
};
usbphy0: usbphy@0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
};
usb0: usb@ffb00000 {
compatible = "snps,dwc2";
reg = <0xffb00000 0x40000>;
interrupts = <0 93 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
status = "disabled";
};
usb1: usb@ffb40000 {
compatible = "snps,dwc2";
reg = <0xffb40000 0x40000>;
interrupts = <0 94 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
status = "disabled";
};
watchdog0: watchdog@ffd00200 {
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>;
status = "disabled";
};
watchdog1: watchdog@ffd00300 {
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0 118 4>;
resets = <&rst WATCHDOG1_RESET>;
status = "disabled";
};
watchdog2: watchdog@ffd00400 {
compatible = "snps,dw-wdt";
reg = <0xffd00400 0x100>;
interrupts = <0 125 4>;
resets = <&rst WATCHDOG2_RESET>;
status = "disabled";
};
watchdog3: watchdog@ffd00500 {
compatible = "snps,dw-wdt";
reg = <0xffd00500 0x100>;
interrupts = <0 126 4>;
resets = <&rst WATCHDOG3_RESET>;
status = "disabled";
};
};
};
arch/arm/dts/socfpga_stratix10_socdk.dts
0 → 100644
浏览文件 @
40df6b3e
/*
*
Copyright
(
C
)
2018
Intel
Corporation
*
*
SPDX
-
License
-
Identifier
:
GPL
-
2.0
*/
#
include
"socfpga_stratix10.dtsi"
/
{
model
=
"SoCFPGA Stratix 10 SoCDK"
;
aliases
{
serial0
=
&
uart0
;
};
chosen
{
stdout
-
path
=
"serial0:115200n8"
;
};
leds
{
compatible
=
"gpio-leds"
;
hps0
{
label
=
"hps_led0"
;
gpios
=
<&
portb
20
GPIO_ACTIVE_HIGH
>;
};
hps1
{
label
=
"hps_led1"
;
gpios
=
<&
portb
19
GPIO_ACTIVE_HIGH
>;
};
hps2
{
label
=
"hps_led2"
;
gpios
=
<&
portb
21
GPIO_ACTIVE_HIGH
>;
};
};
memory
{
device_type
=
"memory"
;
/*
We
expect
the
bootloader
to
fill
in
the
reg
*/
reg
=
<
0
0
0
0
>;
};
};
&
gpio1
{
status
=
"okay"
;
};
&
gmac0
{
status
=
"okay"
;
phy
-
mode
=
"rgmii"
;
phy
-
handle
=
<&
phy0
>;
max
-
frame
-
size
=
<
3800
>;
mdio0
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
0
>;
compatible
=
"snps,dwmac-mdio"
;
phy0
:
ethernet
-
phy
@
0
{
reg
=
<
4
>;
txd0
-
skew
-
ps
=
<
0
>;
/*
-
420
ps
*/
txd1
-
skew
-
ps
=
<
0
>;
/*
-
420
ps
*/
txd2
-
skew
-
ps
=
<
0
>;
/*
-
420
ps
*/
txd3
-
skew
-
ps
=
<
0
>;
/*
-
420
ps
*/
rxd0
-
skew
-
ps
=
<
420
>;
/*
0
ps
*/
rxd1
-
skew
-
ps
=
<
420
>;
/*
0
ps
*/
rxd2
-
skew
-
ps
=
<
420
>;
/*
0
ps
*/
rxd3
-
skew
-
ps
=
<
420
>;
/*
0
ps
*/
txen
-
skew
-
ps
=
<
0
>;
/*
-
420
ps
*/
txc
-
skew
-
ps
=
<
1860
>;
/*
960
ps
*/
rxdv
-
skew
-
ps
=
<
420
>;
/*
0
ps
*/
rxc
-
skew
-
ps
=
<
1680
>;
/*
780
ps
*/
};
};
};
&
mmc
{
status
=
"okay"
;
cap
-
sd
-
highspeed
;
broken
-
cd
;
bus
-
width
=
<
4
>;
};
&
uart0
{
status
=
"okay"
;
};
&
usb0
{
status
=
"okay"
;
};
arch/arm/mach-socfpga/include/mach/base_addr_s10.h
0 → 100644
浏览文件 @
40df6b3e
/*
* Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
#define _SOCFPGA_S10_BASE_HARDWARE_H_
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
#define SOCFPGA_SDR_ADDRESS 0xf8011000
#define SOCFPGA_SMMU_ADDRESS 0xfa000000
#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc02100
#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000
#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100
#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000
#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
#define GICD_BASE 0xfffc1000
#define GICC_BASE 0xfffc2000
#endif
/* _SOCFPGA_S10_BASE_HARDWARE_H_ */
configs/socfpga_arria10_defconfig
浏览文件 @
40df6b3e
...
...
@@ -17,6 +17,8 @@ CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
...
...
configs/socfpga_arria5_defconfig
浏览文件 @
40df6b3e
...
...
@@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -42,6 +44,7 @@ CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
...
...
@@ -54,6 +57,7 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
...
...
configs/socfpga_cyclone5_defconfig
浏览文件 @
40df6b3e
...
...
@@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -42,6 +44,7 @@ CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
...
...
@@ -55,6 +58,7 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
...
...
configs/socfpga_dbm_soc1_defconfig
浏览文件 @
40df6b3e
...
...
@@ -24,6 +24,8 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -45,12 +47,14 @@ CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
...
...
configs/socfpga_de0_nano_soc_defconfig
浏览文件 @
40df6b3e
...
...
@@ -24,6 +24,8 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -42,6 +44,7 @@ CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
...
...
@@ -49,6 +52,7 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
...
...
configs/socfpga_de10_nano_defconfig
浏览文件 @
40df6b3e
...
...
@@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -38,6 +40,7 @@ CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
...
...
@@ -45,6 +48,7 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
...
...
configs/socfpga_de1_soc_defconfig
浏览文件 @
40df6b3e
...
...
@@ -24,6 +24,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -38,6 +40,7 @@ CONFIG_SPL_DM=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
...
...
@@ -45,6 +48,7 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
...
...
configs/socfpga_is1_defconfig
浏览文件 @
40df6b3e
...
...
@@ -22,6 +22,8 @@ CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
...
...
@@ -40,6 +42,7 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
...
...
@@ -49,5 +52,6 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
configs/socfpga_mcvevk_defconfig
浏览文件 @
40df6b3e
...
...
@@ -24,6 +24,8 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -42,12 +44,14 @@ CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
...
...
configs/socfpga_sockit_defconfig
浏览文件 @
40df6b3e
...
...
@@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -42,6 +44,7 @@ CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
...
...
@@ -55,6 +58,7 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
...
...
configs/socfpga_socrates_defconfig
浏览文件 @
40df6b3e
...
...
@@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -43,6 +45,7 @@ CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
...
...
@@ -55,6 +58,7 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
...
...
configs/socfpga_sr1500_defconfig
浏览文件 @
40df6b3e
...
...
@@ -25,6 +25,8 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -44,6 +46,7 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
...
...
@@ -54,6 +57,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_vining_fpga_defconfig
浏览文件 @
40df6b3e
...
...
@@ -26,6 +26,8 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
...
...
@@ -71,6 +73,7 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
...
...
drivers/i2c/designware_i2c.c
浏览文件 @
40df6b3e
...
...
@@ -9,6 +9,7 @@
#include <dm.h>
#include <i2c.h>
#include <pci.h>
#include <reset.h>
#include <asm/io.h>
#include "designware_i2c.h"
...
...
@@ -34,6 +35,7 @@ static struct dw_scl_sda_cfg byt_config = {
struct
dw_i2c
{
struct
i2c_regs
*
regs
;
struct
dw_scl_sda_cfg
*
scl_sda_cfg
;
struct
reset_ctl
reset_ctl
;
};
#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
...
...
@@ -534,6 +536,7 @@ static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
static
int
designware_i2c_probe
(
struct
udevice
*
bus
)
{
struct
dw_i2c
*
priv
=
dev_get_priv
(
bus
);
int
ret
;
if
(
device_is_on_pci_bus
(
bus
))
{
#ifdef CONFIG_DM_PCI
...
...
@@ -549,6 +552,13 @@ static int designware_i2c_probe(struct udevice *bus)
priv
->
regs
=
(
struct
i2c_regs
*
)
devfdt_get_addr_ptr
(
bus
);
}
ret
=
reset_get_by_name
(
bus
,
"i2c"
,
&
priv
->
reset_ctl
);
if
(
ret
)
pr_info
(
"reset_get_by_name() failed: %d
\n
"
,
ret
);
if
(
&
priv
->
reset_ctl
)
reset_deassert
(
&
priv
->
reset_ctl
);
__dw_i2c_init
(
priv
->
regs
,
0
,
0
);
return
0
;
...
...
drivers/reset/Kconfig
浏览文件 @
40df6b3e
...
...
@@ -91,4 +91,11 @@ config RESET_MESON
help
Support for reset controller on Amlogic Meson SoC.
config RESET_SOCFPGA
bool "Reset controller driver for SoCFPGA"
depends on DM_RESET && ARCH_SOCFPGA
default y
help
Support for reset controller on SoCFPGA platform.
endmenu
drivers/reset/Makefile
浏览文件 @
40df6b3e
...
...
@@ -14,3 +14,4 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_AST2500_RESET)
+=
ast2500-reset.o
obj-$(CONFIG_RESET_ROCKCHIP)
+=
reset-rockchip.o
obj-$(CONFIG_RESET_MESON)
+=
reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA)
+=
reset-socfpga.o
drivers/reset/reset-socfpga.c
0 → 100644
浏览文件 @
40df6b3e
/*
* Socfpga Reset Controller Driver
*
* Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* based on
* Allwinner SoCs Reset Controller driver
*
* Copyright 2013 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <dm/of_access.h>
#include <reset-uclass.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
#define BANK_INCREMENT 4
#define NR_BANKS 8
struct
socfpga_reset_data
{
void
__iomem
*
membase
;
};
static
int
socfpga_reset_assert
(
struct
reset_ctl
*
reset_ctl
)
{
struct
socfpga_reset_data
*
data
=
dev_get_priv
(
reset_ctl
->
dev
);
int
id
=
reset_ctl
->
id
;
int
reg_width
=
sizeof
(
u32
);
int
bank
=
id
/
(
reg_width
*
BITS_PER_BYTE
);
int
offset
=
id
%
(
reg_width
*
BITS_PER_BYTE
);
setbits_le32
(
data
->
membase
+
(
bank
*
BANK_INCREMENT
),
BIT
(
offset
));
return
0
;
}
static
int
socfpga_reset_deassert
(
struct
reset_ctl
*
reset_ctl
)
{
struct
socfpga_reset_data
*
data
=
dev_get_priv
(
reset_ctl
->
dev
);
int
id
=
reset_ctl
->
id
;
int
reg_width
=
sizeof
(
u32
);
int
bank
=
id
/
(
reg_width
*
BITS_PER_BYTE
);
int
offset
=
id
%
(
reg_width
*
BITS_PER_BYTE
);
clrbits_le32
(
data
->
membase
+
(
bank
*
BANK_INCREMENT
),
BIT
(
offset
));
return
0
;
}
static
int
socfpga_reset_request
(
struct
reset_ctl
*
reset_ctl
)
{
debug
(
"%s(reset_ctl=%p) (dev=%p, id=%lu)
\n
"
,
__func__
,
reset_ctl
,
reset_ctl
->
dev
,
reset_ctl
->
id
);
return
0
;
}
static
int
socfpga_reset_free
(
struct
reset_ctl
*
reset_ctl
)
{
debug
(
"%s(reset_ctl=%p) (dev=%p, id=%lu)
\n
"
,
__func__
,
reset_ctl
,
reset_ctl
->
dev
,
reset_ctl
->
id
);
return
0
;
}
static
const
struct
reset_ops
socfpga_reset_ops
=
{
.
request
=
socfpga_reset_request
,
.
free
=
socfpga_reset_free
,
.
rst_assert
=
socfpga_reset_assert
,
.
rst_deassert
=
socfpga_reset_deassert
,
};
static
int
socfpga_reset_probe
(
struct
udevice
*
dev
)
{
struct
socfpga_reset_data
*
data
=
dev_get_priv
(
dev
);
const
void
*
blob
=
gd
->
fdt_blob
;
int
node
=
dev_of_offset
(
dev
);
u32
modrst_offset
;
data
->
membase
=
devfdt_get_addr_ptr
(
dev
);
modrst_offset
=
fdtdec_get_int
(
blob
,
node
,
"altr,modrst-offset"
,
0x10
);
data
->
membase
+=
modrst_offset
;
return
0
;
}
static
const
struct
udevice_id
socfpga_reset_match
[]
=
{
{
.
compatible
=
"altr,rst-mgr"
},
{
/* sentinel */
},
};
U_BOOT_DRIVER
(
socfpga_reset
)
=
{
.
name
=
"socfpga-reset"
,
.
id
=
UCLASS_RESET
,
.
of_match
=
socfpga_reset_match
,
.
probe
=
socfpga_reset_probe
,
.
priv_auto_alloc_size
=
sizeof
(
struct
socfpga_reset_data
),
.
ops
=
&
socfpga_reset_ops
,
};
include/configs/socfpga_common.h
浏览文件 @
40df6b3e
...
...
@@ -137,6 +137,7 @@
/*
* I2C support
*/
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
...
...
@@ -157,6 +158,7 @@
unsigned
int
cm_get_l4_sp_clk_hz
(
void
);
#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
#endif
#endif
/* CONFIG_DM_I2C */
/*
* QSPI support
...
...
include/dt-bindings/reset/altr,rst-mgr-s10.h
0 → 100644
浏览文件 @
40df6b3e
/*
* Copyright (C) 2016-2018 Intel Corporation. All rights reserved
* Copyright (C) 2016 Altera Corporation. All rights reserved
*
* SPDX-License-Identifier: GPL-2.0
* derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
*/
#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
/* MPUMODRST */
#define CPU0_RESET 0
#define CPU1_RESET 1
#define CPU2_RESET 2
#define CPU3_RESET 3
/* PER0MODRST */
#define EMAC0_RESET 32
#define EMAC1_RESET 33
#define EMAC2_RESET 34
#define USB0_RESET 35
#define USB1_RESET 36
#define NAND_RESET 37
/* 38 is empty */
#define SDMMC_RESET 39
#define EMAC0_OCP_RESET 40
#define EMAC1_OCP_RESET 41
#define EMAC2_OCP_RESET 42
#define USB0_OCP_RESET 43
#define USB1_OCP_RESET 44
#define NAND_OCP_RESET 45
/* 46 is empty */
#define SDMMC_OCP_RESET 47
#define DMA_RESET 48
#define SPIM0_RESET 49
#define SPIM1_RESET 50
#define SPIS0_RESET 51
#define SPIS1_RESET 52
#define DMA_OCP_RESET 53
#define EMAC_PTP_RESET 54
/* 55 is empty*/
#define DMAIF0_RESET 56
#define DMAIF1_RESET 57
#define DMAIF2_RESET 58
#define DMAIF3_RESET 59
#define DMAIF4_RESET 60
#define DMAIF5_RESET 61
#define DMAIF6_RESET 62
#define DMAIF7_RESET 63
/* PER1MODRST */
#define WATCHDOG0_RESET 64
#define WATCHDOG1_RESET 65
#define WATCHDOG2_RESET 66
#define WATCHDOG3_RESET 67
#define L4SYSTIMER0_RESET 68
#define L4SYSTIMER1_RESET 69
#define SPTIMER0_RESET 70
#define SPTIMER1_RESET 71
#define I2C0_RESET 72
#define I2C1_RESET 73
#define I2C2_RESET 74
#define I2C3_RESET 75
#define I2C4_RESET 76
/* 77-79 is empty */
#define UART0_RESET 80
#define UART1_RESET 81
/* 82-87 is empty */
#define GPIO0_RESET 88
#define GPIO1_RESET 89
/* BRGMODRST */
#define SOC2FPGA_RESET 96
#define LWHPS2FPGA_RESET 97
#define FPGA2SOC_RESET 98
#define F2SSDRAM0_RESET 99
#define F2SSDRAM1_RESET 100
#define F2SSDRAM2_RESET 101
#define DDRSCH_RESET 102
/* COLDMODRST */
#define CPUPO0_RESET 160
#define CPUPO1_RESET 161
#define CPUPO2_RESET 162
#define CPUPO3_RESET 163
/* 164-167 is empty */
#define L2_RESET 168
/* DBGMODRST */
#define DBG_RESET 224
#define CSDAP_RESET 225
/* TAPMODRST */
#define TAP_RESET 256
#endif
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