Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

- Fix sifive serial y-modem transfer.
- Access CSRs using CSR numbers.
- Update doc sifive-fu540
- Support big endian hosts and target.

arch/riscv/cpu/cpu.c

@@ -7,7 +7,6 @@
 #include <cpu.h>
 #include <dm.h>
 #include <log.h>
-#include <asm/csr.h>
 #include <asm/encoding.h>
 #include <dm/uclass-internal.h>
 
@@ -48,7 +47,7 @@ static inline bool supports_extension(char ext)
 	return false;
 #else  /* !CONFIG_CPU */
 #ifdef CONFIG_RISCV_MMODE
-	return csr_read(misa) & (1 << (ext - 'a'));
+	return csr_read(CSR_MISA) & (1 << (ext - 'a'));
 #else  /* !CONFIG_RISCV_MMODE */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
@@ -82,7 +81,7 @@ int arch_cpu_init_dm(void)
 	/* Enable FPU */
 	if (supports_extension('d') || supports_extension('f')) {
 		csr_set(MODE_PREFIX(status), MSTATUS_FS);
-		csr_write(fcsr, 0);
+		csr_write(CSR_FCSR, 0);
 	}
 
 	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
@@ -90,11 +89,11 @@ int arch_cpu_init_dm(void)
 		 * Enable perf counters for cycle, time,
 		 * and instret counters only
 		 */
-		csr_write(mcounteren, GENMASK(2, 0));
+		csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
 
 		/* Disable paging */
 		if (supports_extension('s'))
-			csr_write(satp, 0);
+			csr_write(CSR_SATP, 0);
 	}
 
 	return 0;

arch/riscv/cpu/start.S

@@ -13,7 +13,6 @@
 #include <config.h>
 #include <common.h>
 #include <elf.h>
-#include <asm/csr.h>
 #include <asm/encoding.h>
 #include <generated/asm-offsets.h>
 
@@ -41,7 +40,7 @@ secondary_harts_relocation_error:
 .globl _start
 _start:
 #ifdef CONFIG_RISCV_MMODE
-	csrr	a0, mhartid
+	csrr	a0, CSR_MHARTID
 #endif
 
 	/* save hart id and dtb pointer */

arch/riscv/include/asm/asm.h

+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_ASM_H
+#define _ASM_RISCV_ASM_H
+
+#ifdef __ASSEMBLY__
+#define __ASM_STR(x)	x
+#else
+#define __ASM_STR(x)	#x
+#endif
+
+#if __riscv_xlen == 64
+#define __REG_SEL(a, b)	__ASM_STR(a)
+#elif __riscv_xlen == 32
+#define __REG_SEL(a, b)	__ASM_STR(b)
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+#define REG_L		__REG_SEL(ld, lw)
+#define REG_S		__REG_SEL(sd, sw)
+#define SZREG		__REG_SEL(8, 4)
+#define LGREG		__REG_SEL(3, 2)
+
+#if __SIZEOF_POINTER__ == 8
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.dword
+#define RISCV_SZPTR		8
+#define RISCV_LGPTR		3
+#else
+#define RISCV_PTR		".dword"
+#define RISCV_SZPTR		"8"
+#define RISCV_LGPTR		"3"
+#endif
+#elif __SIZEOF_POINTER__ == 4
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.word
+#define RISCV_SZPTR		4
+#define RISCV_LGPTR		2
+#else
+#define RISCV_PTR		".word"
+#define RISCV_SZPTR		"4"
+#define RISCV_LGPTR		"2"
+#endif
+#else
+#error "Unexpected __SIZEOF_POINTER__"
+#endif
+
+#if (__SIZEOF_INT__ == 4)
+#define RISCV_INT		__ASM_STR(.word)
+#define RISCV_SZINT		__ASM_STR(4)
+#define RISCV_LGINT		__ASM_STR(2)
+#else
+#error "Unexpected __SIZEOF_INT__"
+#endif
+
+#if (__SIZEOF_SHORT__ == 2)
+#define RISCV_SHORT		__ASM_STR(.half)
+#define RISCV_SZSHORT		__ASM_STR(2)
+#define RISCV_LGSHORT		__ASM_STR(1)
+#else
+#error "Unexpected __SIZEOF_SHORT__"
+#endif
+
+#endif /* _ASM_RISCV_ASM_H */

arch/riscv/include/asm/csr.h

-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (C) 2015 Regents of the University of California
  *
@@ -8,13 +8,14 @@
 #ifndef _ASM_RISCV_CSR_H
 #define _ASM_RISCV_CSR_H
 
+#include <asm/asm.h>
 #include <linux/const.h>
 
 /* Status register flags */
 #define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
 #define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
 #define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
-#define SR_SUM		_AC(0x00040000, UL) /* Supervisor access User Memory */
+#define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
 
 #define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
 #define SR_FS_OFF	_AC(0x00000000, UL)
@@ -35,7 +36,7 @@
 #endif
 
 /* SATP flags */
-#if __riscv_xlen == 32
+#ifndef CONFIG_64BIT
 #define SATP_PPN	_AC(0x003FFFFF, UL)
 #define SATP_MODE_32	_AC(0x80000000, UL)
 #define SATP_MODE	SATP_MODE_32
@@ -45,10 +46,18 @@
 #define SATP_MODE	SATP_MODE_39
 #endif
 
-/* Interrupt Enable and Interrupt Pending flags */
-#define MIE_MSIE	_AC(0x00000008, UL) /* Software Interrupt Enable */
-#define SIE_SSIE	_AC(0x00000002, UL) /* Software Interrupt Enable */
-#define SIE_STIE	_AC(0x00000020, UL) /* Timer Interrupt Enable */
+/* SCAUSE */
+#define SCAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
+
+#define IRQ_U_SOFT		0
+#define IRQ_S_SOFT		1
+#define IRQ_M_SOFT		3
+#define IRQ_U_TIMER		4
+#define IRQ_S_TIMER		5
+#define IRQ_M_TIMER		7
+#define IRQ_U_EXT		8
+#define IRQ_S_EXT		9
+#define IRQ_M_EXT		11
 
 #define EXC_INST_MISALIGNED	0
 #define EXC_INST_ACCESS		1
@@ -60,14 +69,47 @@
 #define EXC_LOAD_PAGE_FAULT	13
 #define EXC_STORE_PAGE_FAULT	15
 
-#ifndef __ASSEMBLY__
+/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
+#define MIE_MSIE		(_AC(0x1, UL) << IRQ_M_SOFT)
+#define SIE_SSIE		(_AC(0x1, UL) << IRQ_S_SOFT)
+#define SIE_STIE		(_AC(0x1, UL) << IRQ_S_TIMER)
+#define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)
+
+#define CSR_FCSR		0x003
+#define CSR_CYCLE		0xc00
+#define CSR_TIME		0xc01
+#define CSR_INSTRET		0xc02
+#define CSR_SSTATUS		0x100
+#define CSR_SIE			0x104
+#define CSR_STVEC		0x105
+#define CSR_SCOUNTEREN		0x106
+#define CSR_SSCRATCH		0x140
+#define CSR_SEPC		0x141
+#define CSR_SCAUSE		0x142
+#define CSR_STVAL		0x143
+#define CSR_SIP			0x144
+#define CSR_SATP		0x180
+#define CSR_MSTATUS		0x300
+#define CSR_MISA		0x301
+#define CSR_MIE			0x304
+#define CSR_MTVEC		0x305
+#define CSR_MCOUNTEREN		0x306
+#define CSR_MSCRATCH		0x340
+#define CSR_MEPC		0x341
+#define CSR_MCAUSE		0x342
+#define CSR_MTVAL		0x343
+#define CSR_MIP			0x344
+#define CSR_CYCLEH		0xc80
+#define CSR_TIMEH		0xc81
+#define CSR_INSTRETH		0xc82
+#define CSR_MHARTID		0xf14
 
-#define xcsr(csr)	#csr
+#ifndef __ASSEMBLY__
 
 #define csr_swap(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1"	\
+	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
 			      : "=r" (__v) : "rK" (__v)		\
 			      : "memory");			\
 	__v;							\
@@ -76,7 +118,7 @@
 #define csr_read(csr)						\
 ({								\
 	register unsigned long __v;				\
-	__asm__ __volatile__ ("csrr %0, " xcsr(csr)		\
+	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
 			      : "=r" (__v) :			\
 			      : "memory");			\
 	__v;							\
@@ -85,7 +127,7 @@
 #define csr_write(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrw " xcsr(csr) ", %0"		\
+	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
 			      : : "rK" (__v)			\
 			      : "memory");			\
 })
@@ -93,7 +135,7 @@
 #define csr_read_set(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1"	\
+	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
 			      : "=r" (__v) : "rK" (__v)		\
 			      : "memory");			\
 	__v;							\
@@ -102,7 +144,7 @@
 #define csr_set(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrs " xcsr(csr) ", %0"		\
+	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
 			      : : "rK" (__v)			\
 			      : "memory");			\
 })
@@ -110,7 +152,7 @@
 #define csr_read_clear(csr, val)				\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1"	\
+	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
 			      : "=r" (__v) : "rK" (__v)		\
 			      : "memory");			\
 	__v;							\
@@ -119,7 +161,7 @@
 #define csr_clear(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrc " xcsr(csr) ", %0"		\
+	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
 			      : : "rK" (__v)			\
 			      : "memory");			\
 })

arch/riscv/include/asm/encoding.h

@@ -7,6 +7,8 @@
 #ifndef RISCV_CSR_ENCODING_H
 #define RISCV_CSR_ENCODING_H
 
+#include <asm/csr.h>
+
 #ifdef CONFIG_RISCV_SMODE
 #define MODE_PREFIX(__suffix)	s##__suffix
 #else
@@ -49,13 +51,10 @@
 #define SSTATUS64_SD	0x8000000000000000
 
 #define MIP_SSIP	BIT(IRQ_S_SOFT)
-#define MIP_HSIP	BIT(IRQ_H_SOFT)
 #define MIP_MSIP	BIT(IRQ_M_SOFT)
 #define MIP_STIP	BIT(IRQ_S_TIMER)
-#define MIP_HTIP	BIT(IRQ_H_TIMER)
 #define MIP_MTIP	BIT(IRQ_M_TIMER)
 #define MIP_SEIP	BIT(IRQ_S_EXT)
-#define MIP_HEIP	BIT(IRQ_H_EXT)
 #define MIP_MEIP	BIT(IRQ_M_EXT)
 
 #define SIP_SSIP	MIP_SSIP
@@ -73,18 +72,6 @@
 #define VM_SV39		9
 #define VM_SV48		10
 
-#define IRQ_S_SOFT	1
-#define IRQ_H_SOFT	2
-#define IRQ_M_SOFT	3
-#define IRQ_S_TIMER	5
-#define IRQ_H_TIMER	6
-#define IRQ_M_TIMER	7
-#define IRQ_S_EXT	9
-#define IRQ_H_EXT	10
-#define IRQ_M_EXT	11
-#define IRQ_COP		12
-#define IRQ_HOST	13
-
 #define CAUSE_MISALIGNED_FETCH		0
 #define CAUSE_FETCH_ACCESS		1
 #define CAUSE_ILLEGAL_INSTRUCTION	2
@@ -167,227 +154,6 @@
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
 
-/* CSR numbers */
-#define CSR_FFLAGS		0x1
-#define CSR_FRM			0x2
-#define CSR_FCSR		0x3
-
-#define CSR_SSTATUS		0x100
-#define CSR_SEDELEG		0x102
-#define CSR_SIDELEG		0x103
-#define CSR_SIE			0x104
-#define CSR_STVEC		0x105
-#define CSR_SCOUNTEREN		0x106
-#define CSR_SSCRATCH		0x140
-#define CSR_SEPC		0x141
-#define CSR_SCAUSE		0x142
-#define CSR_STVAL		0x143
-#define CSR_SIP			0x144
-#define CSR_SATP		0x180
-
-#define CSR_MSTATUS		0x300
-#define CSR_MISA		0x301
-#define CSR_MEDELEG		0x302
-#define CSR_MIDELEG		0x303
-#define CSR_MIE			0x304
-#define CSR_MTVEC		0x305
-#define CSR_MCOUNTEREN		0x306
-#define CSR_MHPMEVENT3		0x323
-#define CSR_MHPMEVENT4		0x324
-#define CSR_MHPMEVENT5		0x325
-#define CSR_MHPMEVENT6		0x326
-#define CSR_MHPMEVENT7		0x327
-#define CSR_MHPMEVENT8		0x328
-#define CSR_MHPMEVENT9		0x329
-#define CSR_MHPMEVENT10		0x32a
-#define CSR_MHPMEVENT11		0x32b
-#define CSR_MHPMEVENT12		0x32c
-#define CSR_MHPMEVENT13		0x32d
-#define CSR_MHPMEVENT14		0x32e
-#define CSR_MHPMEVENT15		0x32f
-#define CSR_MHPMEVENT16		0x330
-#define CSR_MHPMEVENT17		0x331
-#define CSR_MHPMEVENT18		0x332
-#define CSR_MHPMEVENT19		0x333
-#define CSR_MHPMEVENT20		0x334
-#define CSR_MHPMEVENT21		0x335
-#define CSR_MHPMEVENT22		0x336
-#define CSR_MHPMEVENT23		0x337
-#define CSR_MHPMEVENT24		0x338
-#define CSR_MHPMEVENT25		0x339
-#define CSR_MHPMEVENT26		0x33a
-#define CSR_MHPMEVENT27		0x33b
-#define CSR_MHPMEVENT28		0x33c
-#define CSR_MHPMEVENT29		0x33d
-#define CSR_MHPMEVENT30		0x33e
-#define CSR_MHPMEVENT31		0x33f
-#define CSR_MSCRATCH		0x340
-#define CSR_MEPC		0x341
-#define CSR_MCAUSE		0x342
-#define CSR_MTVAL		0x343
-#define CSR_MIP			0x344
-#define CSR_PMPCFG0		0x3a0
-#define CSR_PMPCFG1		0x3a1
-#define CSR_PMPCFG2		0x3a2
-#define CSR_PMPCFG3		0x3a3
-#define CSR_PMPADDR0		0x3b0
-#define CSR_PMPADDR1		0x3b1
-#define CSR_PMPADDR2		0x3b2
-#define CSR_PMPADDR3		0x3b3
-#define CSR_PMPADDR4		0x3b4
-#define CSR_PMPADDR5		0x3b5
-#define CSR_PMPADDR6		0x3b6
-#define CSR_PMPADDR7		0x3b7
-#define CSR_PMPADDR8		0x3b8
-#define CSR_PMPADDR9		0x3b9
-#define CSR_PMPADDR10		0x3ba
-#define CSR_PMPADDR11		0x3bb
-#define CSR_PMPADDR12		0x3bc
-#define CSR_PMPADDR13		0x3bd
-#define CSR_PMPADDR14		0x3be
-#define CSR_PMPADDR15		0x3bf
-
-#define CSR_TSELECT		0x7a0
-#define CSR_TDATA1		0x7a1
-#define CSR_TDATA2		0x7a2
-#define CSR_TDATA3		0x7a3
-#define CSR_DCSR		0x7b0
-#define CSR_DPC			0x7b1
-#define CSR_DSCRATCH		0x7b2
-
-#define CSR_MCYCLE		0xb00
-#define CSR_MINSTRET		0xb02
-#define CSR_MHPMCOUNTER3	0xb03
-#define CSR_MHPMCOUNTER4	0xb04
-#define CSR_MHPMCOUNTER5	0xb05
-#define CSR_MHPMCOUNTER6	0xb06
-#define CSR_MHPMCOUNTER7	0xb07
-#define CSR_MHPMCOUNTER8	0xb08
-#define CSR_MHPMCOUNTER9	0xb09
-#define CSR_MHPMCOUNTER10	0xb0a
-#define CSR_MHPMCOUNTER11	0xb0b
-#define CSR_MHPMCOUNTER12	0xb0c
-#define CSR_MHPMCOUNTER13	0xb0d
-#define CSR_MHPMCOUNTER14	0xb0e
-#define CSR_MHPMCOUNTER15	0xb0f
-#define CSR_MHPMCOUNTER16	0xb10
-#define CSR_MHPMCOUNTER17	0xb11
-#define CSR_MHPMCOUNTER18	0xb12
-#define CSR_MHPMCOUNTER19	0xb13
-#define CSR_MHPMCOUNTER20	0xb14
-#define CSR_MHPMCOUNTER21	0xb15
-#define CSR_MHPMCOUNTER22	0xb16
-#define CSR_MHPMCOUNTER23	0xb17
-#define CSR_MHPMCOUNTER24	0xb18
-#define CSR_MHPMCOUNTER25	0xb19
-#define CSR_MHPMCOUNTER26	0xb1a
-#define CSR_MHPMCOUNTER27	0xb1b
-#define CSR_MHPMCOUNTER28	0xb1c
-#define CSR_MHPMCOUNTER29	0xb1d
-#define CSR_MHPMCOUNTER30	0xb1e
-#define CSR_MHPMCOUNTER31	0xb1f
-#define CSR_MCYCLEH		0xb80
-#define CSR_MINSTRETH		0xb82
-#define CSR_MHPMCOUNTER3H	0xb83
-#define CSR_MHPMCOUNTER4H	0xb84
-#define CSR_MHPMCOUNTER5H	0xb85
-#define CSR_MHPMCOUNTER6H	0xb86
-#define CSR_MHPMCOUNTER7H	0xb87
-#define CSR_MHPMCOUNTER8H	0xb88
-#define CSR_MHPMCOUNTER9H	0xb89
-#define CSR_MHPMCOUNTER10H	0xb8a
-#define CSR_MHPMCOUNTER11H	0xb8b
-#define CSR_MHPMCOUNTER12H	0xb8c
-#define CSR_MHPMCOUNTER13H	0xb8d
-#define CSR_MHPMCOUNTER14H	0xb8e
-#define CSR_MHPMCOUNTER15H	0xb8f
-#define CSR_MHPMCOUNTER16H	0xb90
-#define CSR_MHPMCOUNTER17H	0xb91
-#define CSR_MHPMCOUNTER18H	0xb92
-#define CSR_MHPMCOUNTER19H	0xb93
-#define CSR_MHPMCOUNTER20H	0xb94
-#define CSR_MHPMCOUNTER21H	0xb95
-#define CSR_MHPMCOUNTER22H	0xb96
-#define CSR_MHPMCOUNTER23H	0xb97
-#define CSR_MHPMCOUNTER24H	0xb98
-#define CSR_MHPMCOUNTER25H	0xb99
-#define CSR_MHPMCOUNTER26H	0xb9a
-#define CSR_MHPMCOUNTER27H	0xb9b
-#define CSR_MHPMCOUNTER28H	0xb9c
-#define CSR_MHPMCOUNTER29H	0xb9d
-#define CSR_MHPMCOUNTER30H	0xb9e
-#define CSR_MHPMCOUNTER31H	0xb9f
-
-#define CSR_CYCLE		0xc00
-#define CSR_TIME		0xc01
-#define CSR_INSTRET		0xc02
-#define CSR_HPMCOUNTER3		0xc03
-#define CSR_HPMCOUNTER4		0xc04
-#define CSR_HPMCOUNTER5		0xc05
-#define CSR_HPMCOUNTER6		0xc06
-#define CSR_HPMCOUNTER7		0xc07
-#define CSR_HPMCOUNTER8		0xc08
-#define CSR_HPMCOUNTER9		0xc09
-#define CSR_HPMCOUNTER10	0xc0a
-#define CSR_HPMCOUNTER11	0xc0b
-#define CSR_HPMCOUNTER12	0xc0c
-#define CSR_HPMCOUNTER13	0xc0d
-#define CSR_HPMCOUNTER14	0xc0e
-#define CSR_HPMCOUNTER15	0xc0f
-#define CSR_HPMCOUNTER16	0xc10
-#define CSR_HPMCOUNTER17	0xc11
-#define CSR_HPMCOUNTER18	0xc12
-#define CSR_HPMCOUNTER19	0xc13
-#define CSR_HPMCOUNTER20	0xc14
-#define CSR_HPMCOUNTER21	0xc15
-#define CSR_HPMCOUNTER22	0xc16
-#define CSR_HPMCOUNTER23	0xc17
-#define CSR_HPMCOUNTER24	0xc18
-#define CSR_HPMCOUNTER25	0xc19
-#define CSR_HPMCOUNTER26	0xc1a
-#define CSR_HPMCOUNTER27	0xc1b
-#define CSR_HPMCOUNTER28	0xc1c
-#define CSR_HPMCOUNTER29	0xc1d
-#define CSR_HPMCOUNTER30	0xc1e
-#define CSR_HPMCOUNTER31	0xc1f
-#define CSR_CYCLEH		0xc80
-#define CSR_TIMEH		0xc81
-#define CSR_INSTRETH		0xc82
-#define CSR_HPMCOUNTER3H	0xc83
-#define CSR_HPMCOUNTER4H	0xc84
-#define CSR_HPMCOUNTER5H	0xc85
-#define CSR_HPMCOUNTER6H	0xc86
-#define CSR_HPMCOUNTER7H	0xc87
-#define CSR_HPMCOUNTER8H	0xc88
-#define CSR_HPMCOUNTER9H	0xc89
-#define CSR_HPMCOUNTER10H	0xc8a
-#define CSR_HPMCOUNTER11H	0xc8b
-#define CSR_HPMCOUNTER12H	0xc8c
-#define CSR_HPMCOUNTER13H	0xc8d
-#define CSR_HPMCOUNTER14H	0xc8e
-#define CSR_HPMCOUNTER15H	0xc8f
-#define CSR_HPMCOUNTER16H	0xc90
-#define CSR_HPMCOUNTER17H	0xc91
-#define CSR_HPMCOUNTER18H	0xc92
-#define CSR_HPMCOUNTER19H	0xc93
-#define CSR_HPMCOUNTER20H	0xc94
-#define CSR_HPMCOUNTER21H	0xc95
-#define CSR_HPMCOUNTER22H	0xc96
-#define CSR_HPMCOUNTER23H	0xc97
-#define CSR_HPMCOUNTER24H	0xc98
-#define CSR_HPMCOUNTER25H	0xc99
-#define CSR_HPMCOUNTER26H	0xc9a
-#define CSR_HPMCOUNTER27H	0xc9b
-#define CSR_HPMCOUNTER28H	0xc9c
-#define CSR_HPMCOUNTER29H	0xc9d
-#define CSR_HPMCOUNTER30H	0xc9e
-#define CSR_HPMCOUNTER31H	0xc9f
-
-#define CSR_MVENDORID		0xf11
-#define CSR_MARCHID		0xf12
-#define CSR_MIMPID		0xf13
-#define CSR_MHARTID		0xf14
-
 #endif /* __riscv */
 
 #endif /* RISCV_CSR_ENCODING_H */

drivers/serial/serial_sifive.c

@@ -22,6 +22,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UART_TXCTRL_TXEN	0x1
 #define UART_RXCTRL_RXEN	0x1
 
+/* IP register */
+#define UART_IP_RXWM            0x2
+
 struct uart_sifive {
 	u32 txfifo;
 	u32 rxfifo;
@@ -34,7 +37,6 @@ struct uart_sifive {
 
 struct sifive_uart_platdata {
 	unsigned long clock;
-	int saved_input_char;
 	struct uart_sifive *regs;
 };
 
@@ -94,7 +96,7 @@ static int _sifive_serial_getc(struct uart_sifive *regs)
 		return -EAGAIN;
 	ch &= UART_RXFIFO_DATA;
 
-	return (!ch) ? -EAGAIN : ch;
+	return ch;
 }
 
 static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
@@ -133,7 +135,6 @@ static int sifive_serial_probe(struct udevice *dev)
 	if (gd->flags & GD_FLG_RELOC)
 		return 0;
 
-	platdata->saved_input_char = 0;
 	_sifive_serial_init(platdata->regs);
 
 	return 0;
@@ -145,12 +146,6 @@ static int sifive_serial_getc(struct udevice *dev)
 	struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
 	struct uart_sifive *regs = platdata->regs;
 
-	if (platdata->saved_input_char > 0) {
-		c = platdata->saved_input_char;
-		platdata->saved_input_char = 0;
-		return c;
-	}
-
 	while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
 
 	return c;
@@ -171,14 +166,10 @@ static int sifive_serial_pending(struct udevice *dev, bool input)
 	struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
 	struct uart_sifive *regs = platdata->regs;
 
-	if (input) {
-		if (platdata->saved_input_char > 0)
-			return 1;
-		platdata->saved_input_char = _sifive_serial_getc(regs);
-		return (platdata->saved_input_char > 0) ? 1 : 0;
-	} else {
+	if (input)
+		return (readl(&regs->ip) & UART_IP_RXWM);
+	else
 		return !!(readl(&regs->txfifo) & UART_TXFIFO_FULL);
-	}
 }
 
 static int sifive_serial_ofdata_to_platdata(struct udevice *dev)

tools/prelink-riscv.c

@@ -8,10 +8,6 @@
  * without fixup. Both RV32 and RV64 are supported.
  */
 
-#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
-#error "Only little-endian host is supported"
-#endif
-
 #include <errno.h>
 #include <stdbool.h>
 #include <stdint.h>
@@ -25,6 +21,7 @@
 #include <sys/stat.h>
 #include <sys/types.h>
 #include <unistd.h>
+#include <compiler.h>
 
 #ifndef EM_RISCV
 #define EM_RISCV 243
@@ -50,12 +47,28 @@ const char *argv0;
 		exit(EXIT_FAILURE); \
 	} while (0)
 
+#define PRELINK_BYTEORDER le
+#define PRELINK_INC_BITS 32
+#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
+#undef PRELINK_INC_BITS
+
+#define PRELINK_BYTEORDER le
+#define PRELINK_INC_BITS 64
+#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
+#undef PRELINK_INC_BITS
+
+#define PRELINK_BYTEORDER be
 #define PRELINK_INC_BITS 32
 #include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
 #undef PRELINK_INC_BITS
 
+#define PRELINK_BYTEORDER be
 #define PRELINK_INC_BITS 64
 #include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
 #undef PRELINK_INC_BITS
 
 int main(int argc, const char *const *argv)
@@ -91,11 +104,19 @@ int main(int argc, const char *const *argv)
 		die("Invalid ELF file %s", argv[1]);
 
 	bool is64 = e_ident[EI_CLASS] == ELFCLASS64;
-
-	if (is64)
-		prelink64(data);
-	else
-		prelink32(data);
+	bool isbe = e_ident[EI_DATA] == ELFDATA2MSB;
+
+	if (is64) {
+		if (isbe)
+			prelink_be64(data);
+		else
+			prelink_le64(data);
+	} else {
+		if (isbe)
+			prelink_be32(data);
+		else
+			prelink_le32(data);
+	}
 
 	return 0;
 }

tools/prelink-riscv.inc

@@ -12,9 +12,9 @@
 #define CONCAT(x, y) CONCAT_IMPL(x, y)
 #define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
 
-#define prelink_nn      CONCAT(prelink, PRELINK_INC_BITS)
+#define prelink_bonn    CONCAT3(prelink_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
 #define uintnn_t        CONCAT3(uint, PRELINK_INC_BITS, _t)
-#define get_offset_nn   CONCAT(get_offset_, PRELINK_INC_BITS)
+#define get_offset_bonn CONCAT3(get_offset_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
 #define Elf_Ehdr        CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
 #define Elf_Phdr        CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
 #define Elf_Rela        CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
@@ -23,34 +23,38 @@
 #define Elf_Addr        CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
 #define ELF_R_TYPE      CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
 #define ELF_R_SYM       CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
+#define target16_to_cpu CONCAT(PRELINK_BYTEORDER, 16_to_cpu)
+#define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
+#define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
+#define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
 
-static void* get_offset_nn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
+static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
 {
 	Elf_Phdr *p;
 
 	for (p = phdrs; p < phdrs + phnum; ++p)
-		if (p->p_vaddr <= addr && p->p_vaddr + p->p_memsz > addr)
-			return data + p->p_offset + (addr - p->p_vaddr);
+		if (targetnn_to_cpu(p->p_vaddr) <= addr && targetnn_to_cpu(p->p_vaddr) + targetnn_to_cpu(p->p_memsz) > addr)
+			return data + targetnn_to_cpu(p->p_offset) + (addr - targetnn_to_cpu(p->p_vaddr));
 
 	return NULL;
 }
 
-static void prelink_nn(void *data)
+static void prelink_bonn(void *data)
 {
 	Elf_Ehdr *ehdr = data;
 	Elf_Phdr *p;
 	Elf_Dyn *dyn;
 	Elf_Rela *r;
 
-	if (ehdr->e_machine != EM_RISCV)
+	if (target16_to_cpu(ehdr->e_machine) != EM_RISCV)
 		die("Machine type is not RISC-V");
 
-	Elf_Phdr *phdrs = data + ehdr->e_phoff;
+	Elf_Phdr *phdrs = data + targetnn_to_cpu(ehdr->e_phoff);
 
 	Elf_Dyn *dyns = NULL;
-	for (p = phdrs; p < phdrs + ehdr->e_phnum; ++p) {
-		if (p->p_type == PT_DYNAMIC) {
-			dyns = data + p->p_offset;
+	for (p = phdrs; p < phdrs + target16_to_cpu(ehdr->e_phnum); ++p) {
+		if (target32_to_cpu(p->p_type) == PT_DYNAMIC) {
+			dyns = data + targetnn_to_cpu(p->p_offset);
 			break;
 		}
 	}
@@ -62,14 +66,14 @@ static void prelink_nn(void *data)
 	size_t rela_count = 0;
 	Elf_Sym *dynsym = NULL;
 	for (dyn = dyns;; ++dyn) {
-		if (dyn->d_tag == DT_NULL)
+		if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
 			break;
-		else if (dyn->d_tag == DT_RELA)
-			rela_dyn = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr);
-		else if (dyn->d_tag == DT_RELASZ)
-			rela_count = dyn->d_un.d_val / sizeof(Elf_Rela);
-		else if (dyn->d_tag == DT_SYMTAB)
-			dynsym = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr);
+		else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
+			rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
+		else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
+		  rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
+		else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
+			dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
 
 	}
 
@@ -80,23 +84,23 @@ static void prelink_nn(void *data)
 		die("No .dynsym found");
 
 	for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
-		void* buf = get_offset_nn(data, phdrs, ehdr->e_phnum, r->r_offset);
+		void* buf = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), targetnn_to_cpu(r->r_offset));
 
 		if (buf == NULL)
 			continue;
 
-		if (ELF_R_TYPE(r->r_info) == R_RISCV_RELATIVE)
+		if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
 			*((uintnn_t*) buf) = r->r_addend;
-		else if (ELF_R_TYPE(r->r_info) == R_RISCV_32)
-			*((uint32_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value;
-		else if (ELF_R_TYPE(r->r_info) == R_RISCV_64)
-			*((uint64_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value;
+		else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
+			*((uint32_t*) buf) = dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
+		else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
+			*((uint64_t*) buf) = dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
 	}
 }
 
-#undef prelink_nn
+#undef prelink_bonn
 #undef uintnn_t
-#undef get_offset_nn
+#undef get_offset_bonn
 #undef Elf_Ehdr
 #undef Elf_Phdr
 #undef Elf_Rela
@@ -105,6 +109,10 @@ static void prelink_nn(void *data)
 #undef Elf_Addr
 #undef ELF_R_TYPE
 #undef ELF_R_SYM
+#undef target16_to_cpu
+#undef target32_to_cpu
+#undef target64_to_cpu
+#undef targetnn_to_cpu
 
 #undef CONCAT_IMPL
 #undef CONCAT