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体验新版 GitCode,发现更多精彩内容 >>
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3c0c1f02
编写于
3月 24, 2015
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-uniphier
上级
8a440b09
90e357ef
变更
22
隐藏空白更改
内联
并排
Showing
22 changed file
with
200 addition
and
190 deletion
+200
-190
arch/arm/mach-uniphier/Kconfig
arch/arm/mach-uniphier/Kconfig
+0
-3
arch/arm/mach-uniphier/Makefile
arch/arm/mach-uniphier/Makefile
+1
-1
arch/arm/mach-uniphier/cache_uniphier.c
arch/arm/mach-uniphier/cache_uniphier.c
+2
-30
arch/arm/mach-uniphier/init_page_table.S
arch/arm/mach-uniphier/init_page_table.S
+9
-1
arch/arm/mach-uniphier/late_lowlevel_init.S
arch/arm/mach-uniphier/late_lowlevel_init.S
+17
-0
arch/arm/mach-uniphier/lowlevel_init.S
arch/arm/mach-uniphier/lowlevel_init.S
+47
-16
arch/arm/mach-uniphier/ph1-ld4/Makefile
arch/arm/mach-uniphier/ph1-ld4/Makefile
+2
-2
arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
+27
-0
arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
+2
-16
arch/arm/mach-uniphier/ph1-pro4/Makefile
arch/arm/mach-uniphier/ph1-pro4/Makefile
+2
-2
arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
+27
-0
arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
+2
-13
arch/arm/mach-uniphier/ph1-sld8/Makefile
arch/arm/mach-uniphier/ph1-sld8/Makefile
+1
-16
arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c
arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c
+27
-0
arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
+2
-16
arch/arm/mach-uniphier/smp.S
arch/arm/mach-uniphier/smp.S
+0
-54
arch/arm/mach-uniphier/spl.c
arch/arm/mach-uniphier/spl.c
+15
-3
arch/arm/mach-uniphier/support_card.c
arch/arm/mach-uniphier/support_card.c
+6
-5
configs/ph1_ld4_defconfig
configs/ph1_ld4_defconfig
+1
-0
configs/ph1_pro4_defconfig
configs/ph1_pro4_defconfig
+1
-0
configs/ph1_sld8_defconfig
configs/ph1_sld8_defconfig
+1
-0
include/configs/uniphier.h
include/configs/uniphier.h
+8
-12
未找到文件。
arch/arm/mach-uniphier/Kconfig
浏览文件 @
3c0c1f02
menu "Panasonic UniPhier platform"
depends on ARCH_UNIPHIER
config SYS_SOC
default "uniphier"
config SYS_CONFIG_NAME
default "uniphier"
...
...
arch/arm/mach-uniphier/Makefile
浏览文件 @
3c0c1f02
...
...
@@ -12,6 +12,7 @@ obj-y += ddrphy_training.o
else
obj-y
+=
late_lowlevel_init.o
obj-$(CONFIG_BOARD_EARLY_INIT_F)
+=
board_early_init_f.o
obj-$(CONFIG_DISPLAY_CPUINFO)
+=
cpu_info.o
obj-$(CONFIG_MISC_INIT_F)
+=
print_misc_info.o
...
...
@@ -21,7 +22,6 @@ obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
obj-$(CONFIG_BOARD_LATE_INIT)
+=
board_late_init.o
obj-y
+=
reset.o
obj-y
+=
cache_uniphier.o
obj-$(CONFIG_UNIPHIER_SMP)
+=
smp.o
obj-$(CONFIG_CMD_PINMON)
+=
cmd_pinmon.o
obj-$(CONFIG_CMD_DDRPHY_DUMP)
+=
cmd_ddrphy.o
...
...
arch/arm/mach-uniphier/cache_uniphier.c
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2015 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
...
...
@@ -119,36 +120,7 @@ void v7_outer_cache_disable(void)
writel
(
tmp
,
SSCC
);
}
void
wakeup_secondary
(
void
);
void
enable_caches
(
void
)
{
uint32_t
reg
;
#ifdef CONFIG_UNIPHIER_SMP
/*
* The secondary CPU must move to DDR,
* before L2 disable.
* On SPL, the Page Table is located on the L2.
*/
wakeup_secondary
();
#endif
/*
* UniPhier SoCs must use L2 cache for init stack pointer.
* We disable L2 and L1 in this order.
* If CONFIG_SYS_DCACHE_OFF is not defined,
* caches are enabled again with a new page table.
*/
/* L2 disable */
v7_outer_cache_disable
();
/* L1 disable */
reg
=
get_cr
();
reg
&=
~
(
CR_C
|
CR_M
);
set_cr
(
reg
);
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable
();
#endif
}
arch/arm/mach-uniphier/init_page_table.S
浏览文件 @
3c0c1f02
/*
*
Copyright
(
C
)
2015
Panasonic
Corporation
*
Copyright
(
C
)
2015
Socionext
Inc
.
*
Author
:
Masahiro
Yamada
<
yamada
.
masahiro
@
socionext
.
com
>
*
*
SPDX
-
License
-
Identifier
:
GPL
-
2
.0
+
*/
#include <config.h>
#include <linux/linkage.h>
...
...
@@ -8,7 +16,7 @@
#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
#define STACK_SECTION ((CONFIG_S
YS_INIT_SP_ADDR
) >> (SECTION_SHIFT))
#define STACK_SECTION ((CONFIG_S
PL_STACK
) >> (SECTION_SHIFT))
.
section
".rodata"
.
align
14
...
...
arch/arm/mach-uniphier/late_lowlevel_init.S
0 → 100644
浏览文件 @
3c0c1f02
/*
*
Copyright
(
C
)
2015
Socionext
Inc
.
*
Author
:
Masahiro
Yamada
<
yamada
.
masahiro
@
socionext
.
com
>
*
*
SPDX
-
License
-
Identifier
:
GPL
-
2
.0
+
*/
#include <linux/linkage.h>
#include <mach/ssc-regs.h>
ENTRY
(
lowlevel_init
)
ldr
r1
,
=
SSCC
ldr
r0
,
[
r1
]
bic
r0
,
r0
,
#
SSCC_ON
@
L2
disable
str
r0
,
[
r1
]
mov
pc
,
lr
ENDPROC
(
lowlevel_init
)
arch/arm/mach-uniphier/lowlevel_init.S
浏览文件 @
3c0c1f02
/*
*
Copyright
(
C
)
2012
-
2014
Panasonic
Corporation
*
Author
:
Masahiro
Yamada
<
yamada
.
m
@
jp
.
panasonic
.
com
>
*
Copyright
(
C
)
2012
-
2015
Panasonic
Corporation
*
Copyright
(
C
)
2015
Socionext
Inc
.
*
Author
:
Masahiro
Yamada
<
yamada
.
masahiro
@
socionext
.
com
>
*
*
SPDX
-
License
-
Identifier
:
GPL
-
2
.0
+
*/
...
...
@@ -24,8 +25,8 @@ ENTRY(lowlevel_init)
*
First
we
need
to
turn
on
MMU
and
Dcache
again
to
get
back
*
data
access
to
L2
.
*/
mrc
p15
,
0
,
r0
,
c1
,
c0
,
0
@
SCTLR
(
System
Contr
l
Register
)
orr
r0
,
r0
,
#(
CR_C
|
CR_M
)
@
enable
MMU
and
Dcache
mrc
p15
,
0
,
r0
,
c1
,
c0
,
0
@
SCTLR
(
System
Contro
l
Register
)
orr
r0
,
r0
,
#(
CR_C
|
CR_M
)
@
enable
MMU
and
Dcache
mcr
p15
,
0
,
r0
,
c1
,
c0
,
0
#ifdef CONFIG_DEBUG_LL
...
...
@@ -40,13 +41,32 @@ ENTRY(lowlevel_init)
ldr
r3
,
=
init_page_table
@
page
table
must
be
16
KB
aligned
/
*
Disable
MMU
and
Dcache
before
switching
Page
Table
*/
mrc
p15
,
0
,
r0
,
c1
,
c0
,
0
@
SCTLR
(
System
Contrl
Register
)
mrc
p15
,
0
,
r0
,
c1
,
c0
,
0
@
SCTLR
(
System
Contr
o
l
Register
)
bic
r0
,
r0
,
#(
CR_C
|
CR_M
)
@
disable
MMU
and
Dcache
mcr
p15
,
0
,
r0
,
c1
,
c0
,
0
bl
enable_mmu
#ifdef CONFIG_UNIPHIER_SMP
secondary_startup
:
/
*
*
Entry
point
for
secondary
CPUs
*
*
The
Boot
ROM
has
already
enabled
MMU
for
the
secondary
CPUs
as
well
*
as
for
the
primary
one
.
The
MMU
table
embedded
in
the
Boot
ROM
*
prohibits
the
DRAM
access
,
so
it
is
impossible
to
bring
the
*
secondary
CPUs
into
DRAM
directly
.
They
must
jump
here
into
SPL
,
*
which
is
run
on
L2
cache
.
*
*
Boot
Sequence
*
[
primary
CPU
]
[
secondary
CPUs
]
*
start
from
Boot
ROM
start
from
Boot
ROM
*
jump
to
SPL
sleep
in
Boot
ROM
*
kick
secondaries
---(
sev
)--->
jump
to
SPL
*
jump
to
U
-
Boot
main
sleep
in
SPL
*
jump
to
Linux
*
kick
secondaries
---(
sev
)--->
jump
to
Linux
*/
/
*
*
ACTLR
(
Auxiliary
Control
Register
)
for
Cortex
-
A9
*
bit
[
9
]
Parity
on
...
...
@@ -54,7 +74,7 @@ ENTRY(lowlevel_init)
*
bit
[
7
]
EXCL
(
Exclusive
cache
bit
)
*
bit
[
6
]
SMP
*
bit
[
3
]
Write
full
line
of
zeros
mode
*
bit
[
2
]
L1
P
refetch
enable
*
bit
[
2
]
L1
p
refetch
enable
*
bit
[
1
]
L2
prefetch
enable
*
bit
[
0
]
FW
(
Cache
and
TLB
maintenance
broadcast
)
*/
...
...
@@ -67,20 +87,31 @@ ENTRY(lowlevel_init)
and
r0
,
r0
,
#
0x3
cmp
r0
,
#
0x0
beq
primary_cpu
ldr
r1
,
=
ROM_BOOT_ROMRSV2
/
*
only
for
secondary
CPUs
*/
ldr
r1
,
=
ROM_BOOT_ROMRSV2
@
The
last
data
access
to
L2
cache
mrc
p15
,
0
,
r0
,
c1
,
c0
,
0
@
SCTLR
(
System
Control
Register
)
orr
r0
,
r0
,
#
CR_I
@
Enable
ICache
bic
r0
,
r0
,
#(
CR_C
|
CR_M
)
@
MMU
and
Dcache
must
be
disabled
mcr
p15
,
0
,
r0
,
c1
,
c0
,
0
@
before
jumping
to
Linux
mov
r0
,
#
0
str
r0
,
[
r1
]
0
:
wfe
ldr
r0
,
[
r1
]
b
1
f
/
*
*
L2
cache
is
shared
among
all
the
CPUs
and
it
might
be
disabled
by
*
the
primary
one
.
Before
that
,
the
following
5
lines
must
be
cached
*
on
the
Icaches
of
the
secondary
CPUs
.
*/
0
:
wfe
@
kicked
by
Linux
1
:
ldr
r0
,
[
r1
]
cmp
r0
,
#
0
b
eq
0
b
b
x
r0
@
r0
:
entry
point
of
U
-
Boot
main
for
the
secondary
CPU
b
xne
r0
@
r0
:
Linux
entry
for
secondary
CPUs
b
0
b
primary_cpu
:
ldr
r1
,
=
ROM_BOOT_ROMRSV2
ldr
r0
,
=
_start
@
entry
for
the
secondary
CPU
ldr
r0
,
=
secondary_startup
str
r0
,
[
r1
]
ldr
r0
,
[
r1
]
@
make
sure
str
is
complete
before
sev
sev
@
kick
the
se
donc
ary
CPU
sev
@
kick
the
se
cond
ary
CPU
mrc
p15
,
4
,
r1
,
c15
,
c0
,
0
@
Configuration
Base
Address
Register
bfc
r1
,
#
0
,
#
13
@
clear
bit
12
-
0
mov
r0
,
#-
1
...
...
@@ -117,7 +148,7 @@ ENTRY(enable_mmu)
*
TLBs
was
already
invalidated
in
"../start.S"
*
So
,
we
don
't need to invalidate it here.
*/
mrc
p15
,
0
,
r0
,
c1
,
c0
,
0
@
SCTLR
(
System
Contrl
Register
)
mrc
p15
,
0
,
r0
,
c1
,
c0
,
0
@
SCTLR
(
System
Contr
o
l
Register
)
orr
r0
,
r0
,
#(
CR_C
|
CR_M
)
@
MMU
and
Dcache
enable
mcr
p15
,
0
,
r0
,
c1
,
c0
,
0
...
...
@@ -142,7 +173,7 @@ ENTRY(setup_init_ram)
ldr
r0
,
=
0x00408006
@
touch
to
zero
with
address
range
ldr
r1
,
=
SSCOQM
str
r0
,
[
r1
]
ldr
r0
,
=
(
CONFIG_S
YS_INIT_SP_ADDR
-
BOOT_RAM_SIZE
)
@
base
address
ldr
r0
,
=
(
CONFIG_S
PL_STACK
-
BOOT_RAM_SIZE
)
@
base
address
ldr
r1
,
=
SSCOQAD
str
r0
,
[
r1
]
ldr
r0
,
=
BOOT_RAM_SIZE
...
...
@@ -154,7 +185,7 @@ ENTRY(setup_init_ram)
ldr
r1
,
=
SSCOPPQSEF
ldr
r0
,
[
r1
]
cmp
r0
,
#
0
@
check
if
the
command
is
successfully
set
bne
0
b
@
try
again
if
an
error
occur
re
s
bne
0
b
@
try
again
if
an
error
occurs
ldr
r1
,
=
SSCOLPQS
1
:
...
...
arch/arm/mach-uniphier/ph1-ld4/Makefile
浏览文件 @
3c0c1f02
...
...
@@ -5,12 +5,12 @@
ifdef
CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL)
+=
lowlevel_debug.o
obj-y
+=
bcu_init.o sg_init.o pll_init.o early_clkrst_init.o
\
pll_spectrum.o umc_init.o ddrphy_init.o
early_pinctrl.o
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD)
+=
sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD)
+=
sbc_init_3cs.o
obj-$(CONFIG_SPL_DM)
+=
platdevice.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F)
+=
pinctrl.o clkrst_init.o
obj-$(if
$(CONFIG_OF_CONTROL),,
y)
+=
platdevice.o
endif
obj-y
+=
boot-mode.o
arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
0 → 100644
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <mach/sg-regs.h>
void
early_pin_init
(
void
)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel
(
85
,
1
);
/* HSDOUT3 -> RXD0 */
sg_set_pinsel
(
88
,
1
);
/* HDDOUT6 -> TXD0 */
sg_set_pinsel
(
69
,
23
);
/* PCIOWR -> TXD1 */
sg_set_pinsel
(
70
,
23
);
/* PCIORD -> RXD1 */
sg_set_pinsel
(
128
,
13
);
/* XIRQ6 -> TXD2 */
sg_set_pinsel
(
129
,
13
);
/* XIRQ7 -> RXD2 */
sg_set_pinsel
(
110
,
1
);
/* SBO0 -> TXD3 */
sg_set_pinsel
(
111
,
1
);
/* SBI0 -> RXD3 */
#endif
}
arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <mach/sg-regs.h>
...
...
@@ -14,20 +14,6 @@ void pin_init(void)
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel
(
85
,
1
);
/* HSDOUT3 -> RXD0 */
sg_set_pinsel
(
88
,
1
);
/* HDDOUT6 -> TXD0 */
sg_set_pinsel
(
69
,
23
);
/* PCIOWR -> TXD1 */
sg_set_pinsel
(
70
,
23
);
/* PCIORD -> RXD1 */
sg_set_pinsel
(
128
,
13
);
/* XIRQ6 -> TXD2 */
sg_set_pinsel
(
129
,
13
);
/* XIRQ7 -> RXD2 */
sg_set_pinsel
(
110
,
1
);
/* SBO0 -> TXD3 */
sg_set_pinsel
(
111
,
1
);
/* SBI0 -> RXD3 */
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel
(
158
,
0
);
/* XNFRE -> XNFRE_GB */
sg_set_pinsel
(
159
,
0
);
/* XNFWE -> XNFWE_GB */
...
...
arch/arm/mach-uniphier/ph1-pro4/Makefile
浏览文件 @
3c0c1f02
...
...
@@ -5,12 +5,12 @@
ifdef
CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL)
+=
lowlevel_debug.o
obj-y
+=
sg_init.o pll_init.o early_clkrst_init.o
\
pll_spectrum.o umc_init.o ddrphy_init.o
early_pinctrl.o
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD)
+=
sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD)
+=
sbc_init_3cs.o
obj-$(CONFIG_SPL_DM)
+=
platdevice.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F)
+=
pinctrl.o clkrst_init.o
obj-$(if
$(CONFIG_OF_CONTROL),,
y)
+=
platdevice.o
endif
obj-y
+=
boot-mode.o
arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
0 → 100644
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <mach/sg-regs.h>
void
early_pin_init
(
void
)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel
(
127
,
0
);
/* RXD0 -> RXD0 */
sg_set_pinsel
(
128
,
0
);
/* TXD0 -> TXD0 */
sg_set_pinsel
(
129
,
0
);
/* RXD1 -> RXD1 */
sg_set_pinsel
(
130
,
0
);
/* TXD1 -> TXD1 */
sg_set_pinsel
(
131
,
0
);
/* RXD2 -> RXD2 */
sg_set_pinsel
(
132
,
0
);
/* TXD2 -> TXD2 */
sg_set_pinsel
(
88
,
2
);
/* CH6CLK -> RXD3 */
sg_set_pinsel
(
89
,
2
);
/* CH6VAL -> TXD3 */
#endif
writel
(
1
,
SG_LOADPINCTRL
);
}
arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <mach/sg-regs.h>
...
...
@@ -12,17 +12,6 @@ void pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel
(
127
,
0
);
/* RXD0 -> RXD0 */
sg_set_pinsel
(
128
,
0
);
/* TXD0 -> TXD0 */
sg_set_pinsel
(
129
,
0
);
/* RXD1 -> RXD1 */
sg_set_pinsel
(
130
,
0
);
/* TXD1 -> TXD1 */
sg_set_pinsel
(
131
,
0
);
/* RXD2 -> RXD2 */
sg_set_pinsel
(
132
,
0
);
/* TXD2 -> TXD2 */
sg_set_pinsel
(
88
,
2
);
/* CH6CLK -> RXD3 */
sg_set_pinsel
(
89
,
2
);
/* CH6VAL -> TXD3 */
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel
(
40
,
0
);
/* NFD0 -> NFD0 */
sg_set_pinsel
(
41
,
0
);
/* NFD1 -> NFD1 */
...
...
arch/arm/mach-uniphier/ph1-sld8/Makefile
浏览文件 @
3c0c1f02
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef
CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL)
+=
lowlevel_debug.o
obj-y
+=
bcu_init.o sg_init.o pll_init.o early_clkrst_init.o
\
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD)
+=
sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD)
+=
sbc_init_3cs.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F)
+=
pinctrl.o clkrst_init.o
obj-$(if
$(CONFIG_OF_CONTROL),,
y)
+=
platdevice.o
endif
obj-y
+=
boot-mode.o
include
$(src)/../ph1-ld4/Makefile
arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c
0 → 100644
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <mach/sg-regs.h>
void
early_pin_init
(
void
)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel
(
70
,
3
);
/* HDDOUT0 -> TXD0 */
sg_set_pinsel
(
71
,
3
);
/* HSDOUT1 -> RXD0 */
sg_set_pinsel
(
114
,
0
);
/* TXD1 -> TXD1 */
sg_set_pinsel
(
115
,
0
);
/* RXD1 -> RXD1 */
sg_set_pinsel
(
112
,
1
);
/* SBO1 -> TXD2 */
sg_set_pinsel
(
113
,
1
);
/* SBI1 -> RXD2 */
sg_set_pinsel
(
110
,
1
);
/* SBO0 -> TXD3 */
sg_set_pinsel
(
111
,
1
);
/* SBI0 -> RXD3 */
#endif
}
arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <mach/sg-regs.h>
...
...
@@ -12,20 +12,6 @@ void pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel
(
70
,
3
);
/* HDDOUT0 -> TXD0 */
sg_set_pinsel
(
71
,
3
);
/* HSDOUT1 -> RXD0 */
sg_set_pinsel
(
114
,
0
);
/* TXD1 -> TXD1 */
sg_set_pinsel
(
115
,
0
);
/* RXD1 -> RXD1 */
sg_set_pinsel
(
112
,
1
);
/* SBO1 -> TXD2 */
sg_set_pinsel
(
113
,
1
);
/* SBI1 -> RXD2 */
sg_set_pinsel
(
110
,
1
);
/* SBO0 -> TXD3 */
sg_set_pinsel
(
111
,
1
);
/* SBI0 -> RXD3 */
#endif
#ifdef CONFIG_SYS_I2C_UNIPHIER
{
u32
tmp
;
...
...
arch/arm/mach-uniphier/smp.S
已删除
100644 → 0
浏览文件 @
8a440b09
/*
*
Copyright
(
C
)
2013
Panasonic
Corporation
*
Author
:
Masahiro
Yamada
<
yamada
.
m
@
jp
.
panasonic
.
com
>
*
*
SPDX
-
License
-
Identifier
:
GPL
-
2
.0
+
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/system.h>
#include <mach/led.h>
#include <mach/sbc-regs.h>
/*
Entry
point
of
U
-
Boot
main
program
for
the
secondary
CPU
*/
LENTRY
(
secondary_entry
)
mrc
p15
,
0
,
r0
,
c1
,
c0
,
0
@
SCTLR
(
System
Contrl
Register
)
bic
r0
,
r0
,
#(
CR_C
|
CR_M
)
@
MMU
and
Dcache
disable
mcr
p15
,
0
,
r0
,
c1
,
c0
,
0
mcr
p15
,
0
,
r0
,
c8
,
c7
,
0
@
invalidate
TLBs
mcr
p15
,
0
,
r0
,
c7
,
c5
,
0
@
invalidate
icache
dsb
led_write
(
C
,0,,)
ldr
r1
,
=
ROM_BOOT_ROMRSV2
mov
r0
,
#
0
str
r0
,
[
r1
]
0
:
wfe
ldr
r4
,
[
r1
]
@
r4
:
entry
point
for
secondary
CPUs
cmp
r4
,
#
0
beq
0
b
led_write
(
C
,
P
,
U
,
1
)
bx
r4
@
secondary
CPUs
jump
to
linux
ENDPROC
(
secondary_entry
)
ENTRY
(
wakeup_secondary
)
ldr
r1
,
=
ROM_BOOT_ROMRSV2
0
:
ldr
r0
,
[
r1
]
cmp
r0
,
#
0
bne
0
b
/
*
set
entry
address
and
send
event
to
the
secondary
CPU
*/
ldr
r0
,
=
secondary_entry
str
r0
,
[
r1
]
ldr
r0
,
[
r1
]
@
make
sure
store
is
complete
mov
r0
,
#
0x100
0
:
subs
r0
,
r0
,
#
1
@
I
don
't know the reason, but without this wait
bne
0
b
@
fails
to
wake
up
the
secondary
CPU
sev
/
*
wait
until
the
secondary
CPU
reach
to
secondary_entry
*/
0
:
ldr
r0
,
[
r1
]
cmp
r0
,
#
0
bne
0
b
bx
lr
ENDPROC
(
wakeup_secondary
)
arch/arm/mach-uniphier/spl.c
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2013-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2015 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
...
...
@@ -20,6 +21,7 @@ void pll_init(void);
void
pin_init
(
void
);
void
memconf_init
(
void
);
void
early_clkrst_init
(
void
);
void
early_pin_init
(
void
);
int
umc_init
(
void
);
void
enable_dpll_ssc
(
void
);
...
...
@@ -47,6 +49,16 @@ void spl_board_init(void)
led_write
(
L
,
2
,
,
);
early_pin_init
();
led_write
(
L
,
3
,
,
);
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init
();
#endif
led_write
(
L
,
4
,
,
);
{
int
res
;
...
...
@@ -56,9 +68,9 @@ void spl_board_init(void)
;
}
}
led_write
(
L
,
3
,
,
);
led_write
(
L
,
5
,
,
);
enable_dpll_ssc
();
led_write
(
L
,
4
,
,
);
led_write
(
L
,
6
,
,
);
}
arch/arm/mach-uniphier/support_card.c
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2012-2015 Panasonic Corporation
* Copyright (C) 2015 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
...
...
@@ -94,7 +95,7 @@ void support_card_init(void)
/*
* After power on, we need to keep the LAN controller in reset state
* for a while. (200 usec)
* Fortunatel
l
y, enough wait time is already inserted in pll_init()
* Fortunately, enough wait time is already inserted in pll_init()
* function. So we do not have to wait here.
*/
support_card_reset_deassert
();
...
...
@@ -213,11 +214,11 @@ static void detect_num_flash_banks(void)
debug
(
"number of flash banks: %d
\n
"
,
cfi_flash_num_flash_banks
);
}
#else
/* ONFIG_SYS_NO_FLASH */
#else
/*
C
ONFIG_SYS_NO_FLASH */
void
detect_num_flash_banks
(
void
)
{
};
#endif
/* ONFIG_SYS_NO_FLASH */
#endif
/*
C
ONFIG_SYS_NO_FLASH */
void
support_card_late_init
(
void
)
{
...
...
configs/ph1_ld4_defconfig
浏览文件 @
3c0c1f02
...
...
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
CONFIG_MACH_PH1_LD4=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
...
...
configs/ph1_pro4_defconfig
浏览文件 @
3c0c1f02
...
...
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
CONFIG_MACH_PH1_PRO4=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
...
...
configs/ph1_sld8_defconfig
浏览文件 @
3c0c1f02
...
...
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
CONFIG_MACH_PH1_SLD8=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
...
...
include/configs/uniphier.h
浏览文件 @
3c0c1f02
/*
* Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2015 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
...
...
@@ -275,20 +276,13 @@
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_SPL_STACK (0x0ff08000)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000)
#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000)
#else
#define CONFIG_SYS_INIT_SP_ADDR ((CONFIG_SYS_TEXT_BASE) - 0x00001000)
#endif
#define CONFIG_PANIC_HANG
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
/* for mem_malloc_init */
...
...
@@ -298,4 +292,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
#endif
/* __CONFIG_UNIPHIER_COMMON_H__ */
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