提交 3990c9d6 编写于 作者: V Vipul Kumar 提交者: Tom Rini

arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL

This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the
values over to the defconfigs.
Signed-off-by: NVipul Kumar <vipulk@xilinx.com>
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
上级 f4158346
......@@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -30,6 +30,7 @@ CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -30,6 +30,7 @@ CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -28,6 +28,7 @@ CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -26,6 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -34,6 +34,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -29,6 +29,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -30,6 +30,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -39,6 +39,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -39,6 +39,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -34,6 +34,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -32,6 +32,7 @@ CONFIG_CMD_CACHE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BLK=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
......
......@@ -32,6 +32,7 @@ CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_DM_MMC=y
......
......@@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BLK=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
......
......@@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BLK=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
......
......@@ -34,6 +34,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -38,6 +38,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
......
......@@ -50,4 +50,11 @@ config FPGA_SPARTAN3
help
Enable Spartan3 FPGA driver for loading in BIT format.
config FPGA_ZYNQPL
bool "Enable Xilinx FPGA for Zynq"
depends on ARCH_ZYNQ
help
Enable FPGA driver for loading bitstream in BIT and BIN format
on Xilinx Zynq devices.
endmenu
......@@ -269,8 +269,6 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/* Enable the PL to be downloaded */
#define CONFIG_FPGA_ZYNQPL
/* FIT support */
#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
......
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