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体验新版 GitCode,发现更多精彩内容 >>
提交
36b904a7
编写于
8月 11, 2006
作者:
R
Rafal Jaworowski
提交者:
Rafal Jaworowski
8月 11, 2006
浏览文件
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浏览文件
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电子邮件补丁
差异文件
Fix PCI-Express on PPC440SPe rev. A.
上级
692519b1
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
26 addition
and
37 deletion
+26
-37
CHANGELOG
CHANGELOG
+2
-0
board/amcc/yucca/init.S
board/amcc/yucca/init.S
+8
-15
board/amcc/yucca/yucca.c
board/amcc/yucca/yucca.c
+1
-0
cpu/ppc4xx/440spe_pcie.c
cpu/ppc4xx/440spe_pcie.c
+13
-14
include/configs/yucca.h
include/configs/yucca.h
+2
-8
未找到文件。
CHANGELOG
浏览文件 @
36b904a7
...
@@ -2,6 +2,8 @@
...
@@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4:
Changes since U-Boot 1.1.4:
======================================================================
======================================================================
* Fix PCI-Express on PPC440SPe rev. A.
* Add initial support for PCI-Express on PPC440SPe (Yucca board).
* Add initial support for PCI-Express on PPC440SPe (Yucca board).
* Fix timer problems on AMCC yucca board.
* Fix timer problems on AMCC yucca board.
...
...
board/amcc/yucca/init.S
浏览文件 @
36b904a7
...
@@ -105,17 +105,14 @@ tlbtabA:
...
@@ -105,17 +105,14 @@ tlbtabA:
tlbentry
(
CFG_PCI_BASE
,
SZ_256M
,
0x00000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_BASE
,
SZ_256M
,
0x00000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_MEMBASE
,
SZ_256M
,
0x10000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_MEMBASE
,
SZ_256M
,
0x10000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE_MEMBASE
,
SZ_256M
,
0xB0000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE_MEMBASE
,
SZ_256M
,
0xB0000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE_BASE
,
SZ_16K
,
0x20000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_16M
,
0x40000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_16M
,
0x80000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_CFGBASE
,
SZ_1K
,
0x40000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_16M
,
0xC0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_CFGBASE
,
SZ_1K
,
0x80000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_XCFGBASE
,
SZ_4K
,
0x50000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_CFGBASE
,
SZ_1K
,
0xC0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_XCFGBASE
,
SZ_4K
,
0x90000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_XCFGBASE
,
SZ_1K
,
0x50000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_XCFGBASE
,
SZ_4K
,
0xD0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_XCFGBASE
,
SZ_1K
,
0x90000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_XCFGBASE
,
SZ_1K
,
0xD0000000
,
0xC
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_REGBASE
,
SZ_1K
,
0x60000400
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE3_REGBASE
,
SZ_1K
,
0x60001400
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE5_REGBASE
,
SZ_1K
,
0x60002400
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbtab_end
tlbtab_end
/**************************************************************************
/**************************************************************************
...
@@ -152,8 +149,4 @@ tlbtabB:
...
@@ -152,8 +149,4 @@ tlbtabB:
tlbentry
(
CFG_PCIE0_XCFGBASE
,
SZ_1K
,
0x10000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE0_XCFGBASE
,
SZ_1K
,
0x10000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_XCFGBASE
,
SZ_1K
,
0x30000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_XCFGBASE
,
SZ_1K
,
0x30000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_XCFGBASE
,
SZ_1K
,
0x50000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE2_XCFGBASE
,
SZ_1K
,
0x50000000
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE1_REGBASE
,
SZ_1K
,
0x60000400
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE3_REGBASE
,
SZ_1K
,
0x60001400
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCIE5_REGBASE
,
SZ_1K
,
0x60002400
,
0xD
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbtab_end
tlbtab_end
board/amcc/yucca/yucca.c
浏览文件 @
36b904a7
...
@@ -1032,6 +1032,7 @@ void pcie_setup_hoses(void)
...
@@ -1032,6 +1032,7 @@ void pcie_setup_hoses(void)
continue
;
continue
;
yucca_setup_pcie_fpga_rootpoint
(
i
);
yucca_setup_pcie_fpga_rootpoint
(
i
);
if
(
ppc440spe_init_pcie_rootport
(
i
))
{
if
(
ppc440spe_init_pcie_rootport
(
i
))
{
printf
(
"PCIE%d: initialization failed
\n
"
,
i
);
printf
(
"PCIE%d: initialization failed
\n
"
,
i
);
continue
;
continue
;
...
...
cpu/ppc4xx/440spe_pcie.c
浏览文件 @
36b904a7
...
@@ -148,30 +148,28 @@ static void ppc440spe_setup_utl(u32 port) {
...
@@ -148,30 +148,28 @@ static void ppc440spe_setup_utl(u32 port) {
*/
*/
switch
(
port
)
{
switch
(
port
)
{
case
0
:
case
0
:
mtdcr
(
DCRN_PEGPL_REGBAH
(
PCIE0
),
0x0000000
d
);
mtdcr
(
DCRN_PEGPL_REGBAH
(
PCIE0
),
0x0000000
c
);
mtdcr
(
DCRN_PEGPL_REGBAL
(
PCIE0
),
0x
600004
00
);
mtdcr
(
DCRN_PEGPL_REGBAL
(
PCIE0
),
0x
200000
00
);
mtdcr
(
DCRN_PEGPL_REGMSK
(
PCIE0
),
0x
FFFFFC
01
);
mtdcr
(
DCRN_PEGPL_REGMSK
(
PCIE0
),
0x
000070
01
);
mtdcr
(
DCRN_PEGPL_SPECIAL
(
PCIE0
),
0x68782800
);
mtdcr
(
DCRN_PEGPL_SPECIAL
(
PCIE0
),
0x68782800
);
utl_base
=
(
unsigned
int
*
)(
CFG_PCIE1_REGBASE
);
break
;
break
;
case
1
:
case
1
:
mtdcr
(
DCRN_PEGPL_REGBAH
(
PCIE1
),
0x0000000
d
);
mtdcr
(
DCRN_PEGPL_REGBAH
(
PCIE1
),
0x0000000
c
);
mtdcr
(
DCRN_PEGPL_REGBAL
(
PCIE1
),
0x
600014
00
);
mtdcr
(
DCRN_PEGPL_REGBAL
(
PCIE1
),
0x
200010
00
);
mtdcr
(
DCRN_PEGPL_REGMSK
(
PCIE1
),
0x
FFFFFC
01
);
mtdcr
(
DCRN_PEGPL_REGMSK
(
PCIE1
),
0x
000070
01
);
mtdcr
(
DCRN_PEGPL_SPECIAL
(
PCIE1
),
0x68782800
);
mtdcr
(
DCRN_PEGPL_SPECIAL
(
PCIE1
),
0x68782800
);
utl_base
=
(
unsigned
int
*
)(
CFG_PCIE3_REGBASE
);
break
;
break
;
case
2
:
case
2
:
mtdcr
(
DCRN_PEGPL_REGBAH
(
PCIE2
),
0x0000000
d
);
mtdcr
(
DCRN_PEGPL_REGBAH
(
PCIE2
),
0x0000000
c
);
mtdcr
(
DCRN_PEGPL_REGBAL
(
PCIE2
),
0x
600024
00
);
mtdcr
(
DCRN_PEGPL_REGBAL
(
PCIE2
),
0x
200020
00
);
mtdcr
(
DCRN_PEGPL_REGMSK
(
PCIE2
),
0x
FFFFFC
01
);
mtdcr
(
DCRN_PEGPL_REGMSK
(
PCIE2
),
0x
000070
01
);
mtdcr
(
DCRN_PEGPL_SPECIAL
(
PCIE2
),
0x68782800
);
mtdcr
(
DCRN_PEGPL_SPECIAL
(
PCIE2
),
0x68782800
);
utl_base
=
(
unsigned
int
*
)(
CFG_PCIE5_REGBASE
);
break
;
break
;
}
}
utl_base
=
(
unsigned
int
*
)(
CFG_PCIE_BASE
+
0x1000
*
port
);
/*
/*
* Set buffer allocations and then assert VRB and TXE.
* Set buffer allocations and then assert VRB and TXE.
*/
*/
...
@@ -182,7 +180,7 @@ static void ppc440spe_setup_utl(u32 port) {
...
@@ -182,7 +180,7 @@ static void ppc440spe_setup_utl(u32 port) {
out_be32
(
utl_base
+
PEUTL_IPHBSZ
,
0x08000000
);
out_be32
(
utl_base
+
PEUTL_IPHBSZ
,
0x08000000
);
out_be32
(
utl_base
+
PEUTL_IPDBSZ
,
0x10000000
);
out_be32
(
utl_base
+
PEUTL_IPDBSZ
,
0x10000000
);
out_be32
(
utl_base
+
PEUTL_RCIRQEN
,
0x00f00000
);
out_be32
(
utl_base
+
PEUTL_RCIRQEN
,
0x00f00000
);
out_be32
(
utl_base
+
PEUTL_PCTL
,
0x808000
7d
);
out_be32
(
utl_base
+
PEUTL_PCTL
,
0x808000
66
);
}
}
static
int
check_error
(
void
)
static
int
check_error
(
void
)
...
@@ -420,6 +418,7 @@ int ppc440spe_init_pcie_rootport(int port)
...
@@ -420,6 +418,7 @@ int ppc440spe_init_pcie_rootport(int port)
* PCIE1: 0xd_2000_0000
* PCIE1: 0xd_2000_0000
* PCIE2: 0xd_4000_0000
* PCIE2: 0xd_4000_0000
*/
*/
switch
(
port
)
{
switch
(
port
)
{
case
0
:
case
0
:
if
(
ppc440spe_revB
())
{
if
(
ppc440spe_revB
())
{
...
...
include/configs/yucca.h
浏览文件 @
36b904a7
...
@@ -67,8 +67,9 @@
...
@@ -67,8 +67,9 @@
#define CFG_PCI_BASE 0xd0000000
/* internal PCI regs */
#define CFG_PCI_BASE 0xd0000000
/* internal PCI regs */
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
#define CFG_PCIE_MEMBASE 0x
B
0000000
/* mapped PCIe memory */
#define CFG_PCIE_MEMBASE 0x
b
0000000
/* mapped PCIe memory */
#define CFG_PCIE_MEMSIZE 0x01000000
#define CFG_PCIE_MEMSIZE 0x01000000
#define CFG_PCIE_BASE 0xe0000000
/* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
#define CFG_PCIE0_CFGBASE 0xc0000000
#define CFG_PCIE0_XCFGBASE 0xc0000400
#define CFG_PCIE0_XCFGBASE 0xc0000400
...
@@ -77,13 +78,6 @@
...
@@ -77,13 +78,6 @@
#define CFG_PCIE2_CFGBASE 0xc0002000
#define CFG_PCIE2_CFGBASE 0xc0002000
#define CFG_PCIE2_XCFGBASE 0xc0002400
#define CFG_PCIE2_XCFGBASE 0xc0002400
#define CFG_PCIE0_REGBASE 0xc0003000
#define CFG_PCIE1_REGBASE 0xc0003400
#define CFG_PCIE2_REGBASE 0xc0004000
#define CFG_PCIE3_REGBASE 0xc0004400
#define CFG_PCIE4_REGBASE 0xc0005000
#define CFG_PCIE5_REGBASE 0xc0005400
/* System RAM mapped to PCI space */
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
...
...
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