提交 34330a36 编写于 作者: A Adam Ford 提交者: Tom Rini

Convert CONFIG_EMIF4 et al to Kconfig

This converts the following to Kconfig:
   CONFIG_EMIF4
   CONFIG_SDRC
Signed-off-by: NAdam Ford <aford173@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NStefano Babic <sbabic@denx.de>
上级 f0333b4c
......@@ -150,6 +150,21 @@ config TARGET_SNIPER
endchoice
choice
prompt "Memory Controller"
default SDRC
config SDRC
bool "SDRC controller"
help
The default memory controller on most OMAP3 boards is SDRC.
config EMIF4
bool "EMIF4 controller"
help
Enable this on boards like AM3517 which use EMIF4 controller
endchoice
config SPL_OMAP3_ID_NAND
bool "Support OMAP3-specific ID and MFR function"
help
......
......@@ -4,6 +4,7 @@ CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_AM3517_CRANE=y
CONFIG_EMIF4=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
......
......@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_AM3517_EVM=y
CONFIG_EMIF4=y
CONFIG_BOOTDELAY=10
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
......
......@@ -3,6 +3,7 @@ CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_CM_T3517=y
CONFIG_EMIF4=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
......
......@@ -3,6 +3,7 @@ CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_ECO5PK=y
CONFIG_EMIF4=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
......
......@@ -4,6 +4,7 @@ CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_MCX=y
CONFIG_EMIF4=y
CONFIG_VIDEO=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
......
......@@ -3,6 +3,7 @@ CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_MT_VENTOUX=y
CONFIG_EMIF4=y
CONFIG_VIDEO=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
......
......@@ -3,6 +3,7 @@ CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_TWISTER=y
CONFIG_EMIF4=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
......
......@@ -16,7 +16,6 @@
/*
* High Level Configuration Options
*/
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
......
......@@ -14,7 +14,6 @@
#define __CONFIG_H
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
......
......@@ -24,8 +24,6 @@
*/
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
......
......@@ -23,8 +23,6 @@
* to be on the safe side once the default is changed.
*/
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
......
......@@ -15,8 +15,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
......
......@@ -33,8 +33,6 @@
*/
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#include <asm/arch/mem.h>
......
......@@ -39,7 +39,6 @@
* DRAM
*/
#define CONFIG_SDRC
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
......
......@@ -16,8 +16,6 @@
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
......
......@@ -17,8 +17,6 @@
* High Level Configuration Options
*/
#define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
......
......@@ -21,9 +21,6 @@
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
/* The chip has SDRC controller */
#define CONFIG_SDRC
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
......
......@@ -25,8 +25,6 @@
*/
#define CONFIG_SYS_TEXT_BASE 0x80100000
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
......
......@@ -562,7 +562,6 @@ CONFIG_EHCI_MMIO_BIG_ENDIAN
CONFIG_EHCI_MXS_PORT0
CONFIG_EHCI_MXS_PORT1
CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
CONFIG_EMIF4
CONFIG_EMMC_BOOT
CONFIG_EMU
CONFIG_ENABLE_36BIT_PHYS
......@@ -1973,7 +1972,6 @@ CONFIG_SCSI_DEV_LIST
CONFIG_SC_TIMER_CLK
CONFIG_SDCARD
CONFIG_SDRAM_OFFSET_FOR_RT
CONFIG_SDRC
CONFIG_SD_BOOT_QSPI
CONFIG_SECBOOT
CONFIG_SECURE_BL1_ONLY
......
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