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体验新版 GitCode,发现更多精彩内容 >>
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33b9079b
编写于
8月 26, 2008
作者:
K
Kumar Gala
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电子邮件补丁
差异文件
FSL DDR: Convert sbc8548 to new DDR code.
Signed-off-by:
N
Kumar Gala
<
galak@kernel.crashing.org
>
上级
a947e4c7
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
108 addition
and
17 deletion
+108
-17
board/sbc8548/Makefile
board/sbc8548/Makefile
+6
-3
board/sbc8548/ddr.c
board/sbc8548/ddr.c
+80
-0
board/sbc8548/sbc8548.c
board/sbc8548/sbc8548.c
+4
-1
include/configs/sbc8548.h
include/configs/sbc8548.h
+18
-13
未找到文件。
board/sbc8548/Makefile
浏览文件 @
33b9079b
...
...
@@ -28,10 +28,13 @@ include $(TOPDIR)/config.mk
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
:=
$(BOARD)
.o law.o tlb.o
COBJS-y
+=
$(BOARD)
.o
COBJS-y
+=
law.o
COBJS-y
+=
tlb.o
COBJS-$(CONFIG_FSL_DDR2)
+=
ddr.o
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
SRCS
:=
$(SOBJS:.o=.S)
$
(
COBJS
-y
:.o
=
.c
)
OBJS
:=
$(
addprefix
$(obj)
,
$
(
COBJS
-y
))
SOBJS
:=
$(
addprefix
$(obj)
,
$(SOBJS)
)
$(LIB)
:
$(obj).depend $(OBJS) $(SOBJS)
...
...
board/sbc8548/ddr.c
0 → 100644
浏览文件 @
33b9079b
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
static
void
get_spd
(
ddr2_spd_eeprom_t
*
spd
,
unsigned
char
i2c_address
)
{
i2c_read
(
i2c_address
,
0
,
1
,
(
uchar
*
)
spd
,
sizeof
(
ddr2_spd_eeprom_t
));
}
unsigned
int
fsl_ddr_get_mem_data_rate
(
void
)
{
return
get_ddr_freq
(
0
);
}
void
fsl_ddr_get_spd
(
ddr2_spd_eeprom_t
*
ctrl_dimms_spd
,
unsigned
int
ctrl_num
)
{
unsigned
int
i
;
if
(
ctrl_num
)
{
printf
(
"%s unexpected ctrl_num = %u
\n
"
,
__FUNCTION__
,
ctrl_num
);
return
;
}
for
(
i
=
0
;
i
<
CONFIG_DIMM_SLOTS_PER_CTLR
;
i
++
)
{
get_spd
(
&
(
ctrl_dimms_spd
[
i
]),
SPD_EEPROM_ADDRESS
);
}
}
void
fsl_ddr_board_options
(
memctl_options_t
*
popts
,
unsigned
int
ctrl_num
)
{
/*
* Factors to consider for clock adjust:
* - number of chips on bus
* - position of slot
* - DDR1 vs. DDR2?
* - ???
*
* This needs to be determined on a board-by-board basis.
* 0110 3/4 cycle late
* 0111 7/8 cycle late
*/
popts
->
clk_adjust
=
7
;
/*
* Factors to consider for CPO:
* - frequency
* - ddr1 vs. ddr2
*/
popts
->
cpo_override
=
10
;
/*
* Factors to consider for write data delay:
* - number of DIMMs
*
* 1 = 1/4 clock delay
* 2 = 1/2 clock delay
* 3 = 3/4 clock delay
* 4 = 1 clock delay
* 5 = 5/4 clock delay
* 6 = 3/2 clock delay
*/
popts
->
write_data_delay
=
3
;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts
->
half_strength_driver_enable
=
0
;
}
board/sbc8548/sbc8548.c
浏览文件 @
33b9079b
...
...
@@ -30,6 +30,7 @@
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
...
...
@@ -106,7 +107,9 @@ initdram(int board_type)
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size
=
spd_sdram
();
dram_size
=
fsl_ddr_sdram
();
dram_size
=
setup_ddr_tlbs
(
dram_size
/
0x100000
);
dram_size
*=
0x100000
;
#else
dram_size
=
fixed_sdram
();
#endif
...
...
include/configs/sbc8548.h
浏览文件 @
33b9079b
...
...
@@ -47,19 +47,11 @@
#define CONFIG_TSEC_ENET
/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#undef CONFIG_SPD_EEPROM
/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL
/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING
/* Sets the 2T timing bit */
#undef CONFIG_DDR_ECC
/* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS
/* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1
/* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL
/* 85xx has clock control reg */
#define CONFIG_SYS_CLK_FREQ 66000000
/* SBC8548 default SYSCLK */
/*
...
...
@@ -94,13 +86,26 @@
#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000
/* DDR is system memory*/
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_SPD_EEPROM
/* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_SPD
#undef CONFIG_DDR_ECC
/* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CFG_DDR_SDRAM_BASE 0x00000000
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define SPD_EEPROM_ADDRESS 0x51
/* DDR DIMM */
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51
/* CTLR 0 DIMM 0 */
/*
* Make sure required options are set
...
...
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