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体验新版 GitCode,发现更多精彩内容 >>
提交
32dbaafa
编写于
3月 26, 2012
作者:
A
Alison Wang
提交者:
jason
9月 20, 2012
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
ColdFire: Clean up checkpatch warnings for MCF52x2
Signed-off-by:
N
Alison Wang
<
b18965@freescale.com
>
上级
849fc424
变更
9
隐藏空白更改
内联
并排
Showing
9 changed file
with
310 addition
and
262 deletion
+310
-262
arch/m68k/cpu/mcf52x2/cpu.c
arch/m68k/cpu/mcf52x2/cpu.c
+69
-46
arch/m68k/cpu/mcf52x2/cpu_init.c
arch/m68k/cpu/mcf52x2/cpu_init.c
+129
-123
arch/m68k/cpu/mcf52x2/interrupts.c
arch/m68k/cpu/mcf52x2/interrupts.c
+21
-19
arch/m68k/cpu/mcf52x2/speed.c
arch/m68k/cpu/mcf52x2/speed.c
+10
-9
board/freescale/m5208evbe/m5208evbe.c
board/freescale/m5208evbe/m5208evbe.c
+15
-13
board/freescale/m5253demo/m5253demo.c
board/freescale/m5253demo/m5253demo.c
+16
-13
board/freescale/m5253evbe/m5253evbe.c
board/freescale/m5253evbe/m5253evbe.c
+17
-13
board/freescale/m5272c3/m5272c3.c
board/freescale/m5272c3/m5272c3.c
+6
-3
board/freescale/m5275evb/m5275evb.c
board/freescale/m5275evb/m5275evb.c
+27
-23
未找到文件。
arch/m68k/cpu/mcf52x2/cpu.c
浏览文件 @
32dbaafa
...
@@ -9,6 +9,8 @@
...
@@ -9,6 +9,8 @@
* MCF5275 additions
* MCF5275 additions
* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
*
*
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* See file CREDITS for list of people who contributed to this
* See file CREDITS for list of people who contributed to this
* project.
* project.
*
*
...
@@ -32,6 +34,7 @@
...
@@ -32,6 +34,7 @@
#include <watchdog.h>
#include <watchdog.h>
#include <command.h>
#include <command.h>
#include <asm/immap.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <netdev.h>
#include <netdev.h>
#include "cpu.h"
#include "cpu.h"
...
@@ -40,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR;
...
@@ -40,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_M5208
#ifdef CONFIG_M5208
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
int
flag
,
int
argc
,
char
*
const
argv
[])
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
int
flag
,
int
argc
,
char
*
const
argv
[])
{
{
volatile
rcm_t
*
rcm
=
(
rcm_t
*
)(
MMAP_RCM
);
rcm_t
*
rcm
=
(
rcm_t
*
)(
MMAP_RCM
);
udelay
(
1000
);
udelay
(
1000
);
rcm
->
rcr
=
RCM_RCR_SOFTRST
;
out_8
(
&
rcm
->
rcr
,
RCM_RCR_SOFTRST
)
;
/* we don't return! */
/* we don't return! */
return
0
;
return
0
;
...
@@ -65,18 +68,21 @@ int checkcpu(void)
...
@@ -65,18 +68,21 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
/* Called by macro WATCHDOG_RESET */
void
watchdog_reset
(
void
)
void
watchdog_reset
(
void
)
{
{
volatile
wdog_t
*
wdt
=
(
volatile
wdog_t
*
)(
MMAP_WDOG
);
wdog_t
*
wdt
=
(
wdog_t
*
)(
MMAP_WDOG
);
wdt
->
sr
=
0x5555
;
wdt
->
sr
=
0xAAAA
;
out_be16
(
&
wdt
->
sr
,
0x5555
);
out_be16
(
&
wdt
->
sr
,
0xaaaa
);
}
}
int
watchdog_disable
(
void
)
int
watchdog_disable
(
void
)
{
{
volatile
wdog_t
*
wdt
=
(
volatile
wdog_t
*
)(
MMAP_WDOG
);
wdog_t
*
wdt
=
(
wdog_t
*
)(
MMAP_WDOG
);
wdt
->
sr
=
0x5555
;
/* reset watchdog counter */
/* reset watchdog counter */
wdt
->
sr
=
0xAAAA
;
out_be16
(
&
wdt
->
sr
,
0x5555
);
wdt
->
cr
=
0
;
/* disable watchdog timer */
out_be16
(
&
wdt
->
sr
,
0xaaaa
);
/* disable watchdog timer */
out_be16
(
&
wdt
->
cr
,
0
);
puts
(
"WATCHDOG:disabled
\n
"
);
puts
(
"WATCHDOG:disabled
\n
"
);
return
(
0
);
return
(
0
);
...
@@ -84,15 +90,18 @@ int watchdog_disable(void)
...
@@ -84,15 +90,18 @@ int watchdog_disable(void)
int
watchdog_init
(
void
)
int
watchdog_init
(
void
)
{
{
volatile
wdog_t
*
wdt
=
(
volatile
wdog_t
*
)(
MMAP_WDOG
);
wdog_t
*
wdt
=
(
wdog_t
*
)(
MMAP_WDOG
);
wdt
->
cr
=
0
;
/* disable watchdog */
/* disable watchdog */
out_be16
(
&
wdt
->
cr
,
0
);
/* set timeout and enable watchdog */
/* set timeout and enable watchdog */
wdt
->
mr
=
out_be16
(
&
wdt
->
mr
,
((
CONFIG_WATCHDOG_TIMEOUT
*
CONFIG_SYS_HZ
)
/
(
32768
*
1000
))
-
1
;
(
CONFIG_WATCHDOG_TIMEOUT
*
CONFIG_SYS_HZ
)
/
(
32768
*
1000
)
-
1
);
wdt
->
sr
=
0x5555
;
/* reset watchdog counter */
wdt
->
sr
=
0xAAAA
;
/* reset watchdog counter */
out_be16
(
&
wdt
->
sr
,
0x5555
);
out_be16
(
&
wdt
->
sr
,
0xaaaa
);
puts
(
"WATCHDOG:enabled
\n
"
);
puts
(
"WATCHDOG:enabled
\n
"
);
return
(
0
);
return
(
0
);
...
@@ -178,13 +187,13 @@ int watchdog_init(void)
...
@@ -178,13 +187,13 @@ int watchdog_init(void)
#ifdef CONFIG_M5272
#ifdef CONFIG_M5272
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
int
flag
,
int
argc
,
char
*
const
argv
[])
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
int
flag
,
int
argc
,
char
*
const
argv
[])
{
{
volatile
wdog_t
*
wdp
=
(
wdog_t
*
)
(
MMAP_WDOG
);
wdog_t
*
wdp
=
(
wdog_t
*
)
(
MMAP_WDOG
);
wdp
->
wdog_wrrr
=
0
;
out_be16
(
&
wdp
->
wdog_wrrr
,
0
)
;
udelay
(
1000
);
udelay
(
1000
);
/* enable watchdog, set timeout to 0 and wait */
/* enable watchdog, set timeout to 0 and wait */
wdp
->
wdog_wrrr
=
1
;
out_be16
(
&
wdp
->
wdog_wrrr
,
1
)
;
while
(
1
)
;
while
(
1
)
;
/* we don't return! */
/* we don't return! */
...
@@ -193,12 +202,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
...
@@ -193,12 +202,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int
checkcpu
(
void
)
int
checkcpu
(
void
)
{
{
volatile
sysctrl_t
*
sysctrl
=
(
sysctrl_t
*
)
(
MMAP_CFG
);
sysctrl_t
*
sysctrl
=
(
sysctrl_t
*
)
(
MMAP_CFG
);
uchar
msk
;
uchar
msk
;
char
*
suf
;
char
*
suf
;
puts
(
"CPU: "
);
puts
(
"CPU: "
);
msk
=
(
sysctrl
->
sc_dir
>
28
)
&
0xf
;
msk
=
(
in_be32
(
&
sysctrl
->
sc_dir
)
>
28
)
&
0xf
;
switch
(
msk
)
{
switch
(
msk
)
{
case
0x2
:
case
0x2
:
suf
=
"1K75N"
;
suf
=
"1K75N"
;
...
@@ -221,17 +230,21 @@ int checkcpu(void)
...
@@ -221,17 +230,21 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
/* Called by macro WATCHDOG_RESET */
void
watchdog_reset
(
void
)
void
watchdog_reset
(
void
)
{
{
volatile
wdog_t
*
wdt
=
(
volatile
wdog_t
*
)(
MMAP_WDOG
);
wdog_t
*
wdt
=
(
wdog_t
*
)(
MMAP_WDOG
);
wdt
->
wdog_wcr
=
0
;
out_be16
(
&
wdt
->
wdog_wcr
,
0
);
}
}
int
watchdog_disable
(
void
)
int
watchdog_disable
(
void
)
{
{
volatile
wdog_t
*
wdt
=
(
volatile
wdog_t
*
)(
MMAP_WDOG
);
wdog_t
*
wdt
=
(
wdog_t
*
)(
MMAP_WDOG
);
wdt
->
wdog_wcr
=
0
;
/* reset watchdog counter */
/* reset watchdog counter */
wdt
->
wdog_wirr
=
0
;
/* disable watchdog interrupt */
out_be16
(
&
wdt
->
wdog_wcr
,
0
);
wdt
->
wdog_wrrr
=
0
;
/* disable watchdog timer */
/* disable watchdog interrupt */
out_be16
(
&
wdt
->
wdog_wirr
,
0
);
/* disable watchdog timer */
out_be16
(
&
wdt
->
wdog_wrrr
,
0
);
puts
(
"WATCHDOG:disabled
\n
"
);
puts
(
"WATCHDOG:disabled
\n
"
);
return
(
0
);
return
(
0
);
...
@@ -239,14 +252,17 @@ int watchdog_disable(void)
...
@@ -239,14 +252,17 @@ int watchdog_disable(void)
int
watchdog_init
(
void
)
int
watchdog_init
(
void
)
{
{
volatile
wdog_t
*
wdt
=
(
volatile
wdog_t
*
)(
MMAP_WDOG
);
wdog_t
*
wdt
=
(
wdog_t
*
)(
MMAP_WDOG
);
wdt
->
wdog_wirr
=
0
;
/* disable watchdog interrupt */
/* disable watchdog interrupt */
out_be16
(
&
wdt
->
wdog_wirr
,
0
);
/* set timeout and enable watchdog */
/* set timeout and enable watchdog */
wdt
->
wdog_wrrr
=
out_be16
(
&
wdt
->
wdog_wrrr
,
((
CONFIG_WATCHDOG_TIMEOUT
*
CONFIG_SYS_HZ
)
/
(
32768
*
1000
))
-
1
;
(
CONFIG_WATCHDOG_TIMEOUT
*
CONFIG_SYS_HZ
)
/
(
32768
*
1000
)
-
1
);
wdt
->
wdog_wcr
=
0
;
/* reset watchdog counter */
/* reset watchdog counter */
out_be16
(
&
wdt
->
wdog_wcr
,
0
);
puts
(
"WATCHDOG:enabled
\n
"
);
puts
(
"WATCHDOG:enabled
\n
"
);
return
(
0
);
return
(
0
);
...
@@ -258,11 +274,11 @@ int watchdog_init(void)
...
@@ -258,11 +274,11 @@ int watchdog_init(void)
#ifdef CONFIG_M5275
#ifdef CONFIG_M5275
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
int
flag
,
int
argc
,
char
*
const
argv
[])
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
int
flag
,
int
argc
,
char
*
const
argv
[])
{
{
volatile
rcm_t
*
rcm
=
(
rcm_t
*
)(
MMAP_RCM
);
rcm_t
*
rcm
=
(
rcm_t
*
)(
MMAP_RCM
);
udelay
(
1000
);
udelay
(
1000
);
rcm
->
rcr
=
RCM_RCR_SOFTRST
;
out_8
(
&
rcm
->
rcr
,
RCM_RCR_SOFTRST
)
;
/* we don't return! */
/* we don't return! */
return
0
;
return
0
;
...
@@ -282,18 +298,22 @@ int checkcpu(void)
...
@@ -282,18 +298,22 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
/* Called by macro WATCHDOG_RESET */
void
watchdog_reset
(
void
)
void
watchdog_reset
(
void
)
{
{
volatile
wdog_t
*
wdt
=
(
volatile
wdog_t
*
)(
MMAP_WDOG
);
wdog_t
*
wdt
=
(
wdog_t
*
)(
MMAP_WDOG
);
wdt
->
wsr
=
0x5555
;
wdt
->
wsr
=
0xAAAA
;
out_be16
(
&
wdt
->
wsr
,
0x5555
);
out_be16
(
&
wdt
->
wsr
,
0xaaaa
);
}
}
int
watchdog_disable
(
void
)
int
watchdog_disable
(
void
)
{
{
volatile
wdog_t
*
wdt
=
(
volatile
wdog_t
*
)(
MMAP_WDOG
);
wdog_t
*
wdt
=
(
wdog_t
*
)(
MMAP_WDOG
);
wdt
->
wsr
=
0x5555
;
/* reset watchdog counter */
/* reset watchdog counter */
wdt
->
wsr
=
0xAAAA
;
out_be16
(
&
wdt
->
wsr
,
0x5555
);
wdt
->
wcr
=
0
;
/* disable watchdog timer */
out_be16
(
&
wdt
->
wsr
,
0xaaaa
);
/* disable watchdog timer */
out_be16
(
&
wdt
->
wcr
,
0
);
puts
(
"WATCHDOG:disabled
\n
"
);
puts
(
"WATCHDOG:disabled
\n
"
);
return
(
0
);
return
(
0
);
...
@@ -301,15 +321,18 @@ int watchdog_disable(void)
...
@@ -301,15 +321,18 @@ int watchdog_disable(void)
int
watchdog_init
(
void
)
int
watchdog_init
(
void
)
{
{
volatile
wdog_t
*
wdt
=
(
volatile
wdog_t
*
)(
MMAP_WDOG
);
wdog_t
*
wdt
=
(
wdog_t
*
)(
MMAP_WDOG
);
wdt
->
wcr
=
0
;
/* disable watchdog */
/* disable watchdog */
out_be16
(
&
wdt
->
wcr
,
0
);
/* set timeout and enable watchdog */
/* set timeout and enable watchdog */
wdt
->
wmr
=
out_be16
(
&
wdt
->
wmr
,
((
CONFIG_WATCHDOG_TIMEOUT
*
CONFIG_SYS_HZ
)
/
(
32768
*
1000
))
-
1
;
(
CONFIG_WATCHDOG_TIMEOUT
*
CONFIG_SYS_HZ
)
/
(
32768
*
1000
)
-
1
);
wdt
->
wsr
=
0x5555
;
/* reset watchdog counter */
wdt
->
wsr
=
0xAAAA
;
/* reset watchdog counter */
out_be16
(
&
wdt
->
wsr
,
0x5555
);
out_be16
(
&
wdt
->
wsr
,
0xaaaa
);
puts
(
"WATCHDOG:enabled
\n
"
);
puts
(
"WATCHDOG:enabled
\n
"
);
return
(
0
);
return
(
0
);
...
...
arch/m68k/cpu/mcf52x2/cpu_init.c
浏览文件 @
32dbaafa
...
@@ -8,7 +8,7 @@
...
@@ -8,7 +8,7 @@
* (c) Copyright 2010
* (c) Copyright 2010
* Arcturus Networks Inc. <www.arcturusnetworks.com>
* Arcturus Networks Inc. <www.arcturusnetworks.com>
*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
*
...
@@ -37,6 +37,7 @@
...
@@ -37,6 +37,7 @@
#include <common.h>
#include <common.h>
#include <watchdog.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/immap.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <config.h>
...
@@ -48,57 +49,57 @@
...
@@ -48,57 +49,57 @@
/* Only 5272 Flexbus chipselect is different from the rest */
/* Only 5272 Flexbus chipselect is different from the rest */
void
init_fbcs
(
void
)
void
init_fbcs
(
void
)
{
{
volatile
fbcs_t
*
fbcs
=
(
fbcs_t
*
)
(
MMAP_FBCS
);
fbcs_t
*
fbcs
=
(
fbcs_t
*
)
(
MMAP_FBCS
);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
&& defined(CONFIG_SYS_CS0_CTRL))
fbcs
->
csar0
=
CONFIG_SYS_CS0_BASE
;
out_be32
(
&
fbcs
->
csar0
,
CONFIG_SYS_CS0_BASE
)
;
fbcs
->
cscr0
=
CONFIG_SYS_CS0_CTRL
;
out_be32
(
&
fbcs
->
cscr0
,
CONFIG_SYS_CS0_CTRL
)
;
fbcs
->
csmr0
=
CONFIG_SYS_CS0_MASK
;
out_be32
(
&
fbcs
->
csmr0
,
CONFIG_SYS_CS0_MASK
)
;
#else
#else
#warning "Chip Select 0 are not initialized/used"
#warning "Chip Select 0 are not initialized/used"
#endif
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
&& defined(CONFIG_SYS_CS1_CTRL))
fbcs
->
csar1
=
CONFIG_SYS_CS1_BASE
;
out_be32
(
&
fbcs
->
csar1
,
CONFIG_SYS_CS1_BASE
)
;
fbcs
->
cscr1
=
CONFIG_SYS_CS1_CTRL
;
out_be32
(
&
fbcs
->
cscr1
,
CONFIG_SYS_CS1_CTRL
)
;
fbcs
->
csmr1
=
CONFIG_SYS_CS1_MASK
;
out_be32
(
&
fbcs
->
csmr1
,
CONFIG_SYS_CS1_MASK
)
;
#endif
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
&& defined(CONFIG_SYS_CS2_CTRL))
fbcs
->
csar2
=
CONFIG_SYS_CS2_BASE
;
out_be32
(
&
fbcs
->
csar2
,
CONFIG_SYS_CS2_BASE
)
;
fbcs
->
cscr2
=
CONFIG_SYS_CS2_CTRL
;
out_be32
(
&
fbcs
->
cscr2
,
CONFIG_SYS_CS2_CTRL
)
;
fbcs
->
csmr2
=
CONFIG_SYS_CS2_MASK
;
out_be32
(
&
fbcs
->
csmr2
,
CONFIG_SYS_CS2_MASK
)
;
#endif
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
&& defined(CONFIG_SYS_CS3_CTRL))
fbcs
->
csar3
=
CONFIG_SYS_CS3_BASE
;
out_be32
(
&
fbcs
->
csar3
,
CONFIG_SYS_CS3_BASE
)
;
fbcs
->
cscr3
=
CONFIG_SYS_CS3_CTRL
;
out_be32
(
&
fbcs
->
cscr3
,
CONFIG_SYS_CS3_CTRL
)
;
fbcs
->
csmr3
=
CONFIG_SYS_CS3_MASK
;
out_be32
(
&
fbcs
->
csmr3
,
CONFIG_SYS_CS3_MASK
)
;
#endif
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
&& defined(CONFIG_SYS_CS4_CTRL))
fbcs
->
csar4
=
CONFIG_SYS_CS4_BASE
;
out_be32
(
&
fbcs
->
csar4
,
CONFIG_SYS_CS4_BASE
)
;
fbcs
->
cscr4
=
CONFIG_SYS_CS4_CTRL
;
out_be32
(
&
fbcs
->
cscr4
,
CONFIG_SYS_CS4_CTRL
)
;
fbcs
->
csmr4
=
CONFIG_SYS_CS4_MASK
;
out_be32
(
&
fbcs
->
csmr4
,
CONFIG_SYS_CS4_MASK
)
;
#endif
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
&& defined(CONFIG_SYS_CS5_CTRL))
fbcs
->
csar5
=
CONFIG_SYS_CS5_BASE
;
out_be32
(
&
fbcs
->
csar5
,
CONFIG_SYS_CS5_BASE
)
;
fbcs
->
cscr5
=
CONFIG_SYS_CS5_CTRL
;
out_be32
(
&
fbcs
->
cscr5
,
CONFIG_SYS_CS5_CTRL
)
;
fbcs
->
csmr5
=
CONFIG_SYS_CS5_MASK
;
out_be32
(
&
fbcs
->
csmr5
,
CONFIG_SYS_CS5_MASK
)
;
#endif
#endif
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
&& defined(CONFIG_SYS_CS6_CTRL))
&& defined(CONFIG_SYS_CS6_CTRL))
fbcs
->
csar6
=
CONFIG_SYS_CS6_BASE
;
out_be32
(
&
fbcs
->
csar6
,
CONFIG_SYS_CS6_BASE
)
;
fbcs
->
cscr6
=
CONFIG_SYS_CS6_CTRL
;
out_be32
(
&
fbcs
->
cscr6
,
CONFIG_SYS_CS6_CTRL
)
;
fbcs
->
csmr6
=
CONFIG_SYS_CS6_MASK
;
out_be32
(
&
fbcs
->
csmr6
,
CONFIG_SYS_CS6_MASK
)
;
#endif
#endif
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
&& defined(CONFIG_SYS_CS7_CTRL))
&& defined(CONFIG_SYS_CS7_CTRL))
fbcs
->
csar7
=
CONFIG_SYS_CS7_BASE
;
out_be32
(
&
fbcs
->
csar7
,
CONFIG_SYS_CS7_BASE
)
;
fbcs
->
cscr7
=
CONFIG_SYS_CS7_CTRL
;
out_be32
(
&
fbcs
->
cscr7
,
CONFIG_SYS_CS7_CTRL
)
;
fbcs
->
csmr7
=
CONFIG_SYS_CS7_MASK
;
out_be32
(
&
fbcs
->
csmr7
,
CONFIG_SYS_CS7_MASK
)
;
#endif
#endif
}
}
#endif
#endif
...
@@ -106,22 +107,22 @@ void init_fbcs(void)
...
@@ -106,22 +107,22 @@ void init_fbcs(void)
#if defined(CONFIG_M5208)
#if defined(CONFIG_M5208)
void
cpu_init_f
(
void
)
void
cpu_init_f
(
void
)
{
{
volatile
scm1_t
*
scm1
=
(
scm1_t
*
)
MMAP_SCM1
;
scm1_t
*
scm1
=
(
scm1_t
*
)
MMAP_SCM1
;
#ifndef CONFIG_WATCHDOG
#ifndef CONFIG_WATCHDOG
volatile
wdog_t
*
wdg
=
(
wdog_t
*
)
MMAP_WDOG
;
wdog_t
*
wdg
=
(
wdog_t
*
)
MMAP_WDOG
;
/* Disable the watchdog if we aren't using it */
/* Disable the watchdog if we aren't using it */
wdg
->
cr
=
0
;
out_be16
(
&
wdg
->
cr
,
0
)
;
#endif
#endif
scm1
->
mpr
=
0x77777777
;
out_be32
(
&
scm1
->
mpr
,
0x77777777
)
;
scm1
->
pacra
=
0
;
out_be32
(
&
scm1
->
pacra
,
0
)
;
scm1
->
pacrb
=
0
;
out_be32
(
&
scm1
->
pacrb
,
0
)
;
scm1
->
pacrc
=
0
;
out_be32
(
&
scm1
->
pacrc
,
0
)
;
scm1
->
pacrd
=
0
;
out_be32
(
&
scm1
->
pacrd
,
0
)
;
scm1
->
pacre
=
0
;
out_be32
(
&
scm1
->
pacre
,
0
)
;
scm1
->
pacrf
=
0
;
out_be32
(
&
scm1
->
pacrf
,
0
)
;
/* FlexBus Chipselect */
/* FlexBus Chipselect */
init_fbcs
();
init_fbcs
();
...
@@ -137,36 +138,36 @@ int cpu_init_r(void)
...
@@ -137,36 +138,36 @@ int cpu_init_r(void)
void
uart_port_conf
(
int
port
)
void
uart_port_conf
(
int
port
)
{
{
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
/* Setup Ports: */
/* Setup Ports: */
switch
(
port
)
{
switch
(
port
)
{
case
0
:
case
0
:
gpio
->
par_uart
&=
GPIO_PAR_UART0_UNMASK
;
clrbits_be16
(
&
gpio
->
par_uart
,
~
GPIO_PAR_UART0_UNMASK
)
;
gpio
->
par_uart
|=
(
GPIO_PAR_UART_U0TXD
|
GPIO_PAR_UART_U0RXD
);
setbits_be16
(
&
gpio
->
par_uart
,
GPIO_PAR_UART_U0TXD
|
GPIO_PAR_UART_U0RXD
);
break
;
break
;
case
1
:
case
1
:
gpio
->
par_uart
&=
GPIO_PAR_UART0_UNMASK
;
clrbits_be16
(
&
gpio
->
par_uart
,
~
GPIO_PAR_UART0_UNMASK
)
;
gpio
->
par_uart
|=
(
GPIO_PAR_UART_U1TXD
|
GPIO_PAR_UART_U1RXD
);
setbits_be16
(
&
gpio
->
par_uart
,
GPIO_PAR_UART_U1TXD
|
GPIO_PAR_UART_U1RXD
);
break
;
break
;
case
2
:
case
2
:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
#ifdef CONFIG_SYS_UART2_PRI_GPIO
gpio
->
par_timer
&=
clrbits_8
(
&
gpio
->
par_timer
,
(
GPIO_PAR_TMR_TIN0_UNMASK
|
GPIO_PAR_TMR_TIN1_UNMASK
);
~
(
GPIO_PAR_TMR_TIN0_UNMASK
|
GPIO_PAR_TMR_TIN1_UNMASK
)
);
gpio
->
par_timer
|=
setbits_8
(
&
gpio
->
par_timer
,
(
GPIO_PAR_TMR_TIN0_U2TXD
|
GPIO_PAR_TMR_TIN1_U2RXD
);
GPIO_PAR_TMR_TIN0_U2TXD
|
GPIO_PAR_TMR_TIN1_U2RXD
);
#endif
#endif
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
gpio
->
par_feci2c
&=
clrbits_8
(
&
gpio
->
par_feci2c
,
(
GPIO_PAR_FECI2C_MDC_UNMASK
|
GPIO_PAR_FECI2C_MDIO_UNMASK
);
~
(
GPIO_PAR_FECI2C_MDC_UNMASK
|
GPIO_PAR_FECI2C_MDIO_UNMASK
)
);
gpio
->
par_feci2c
|=
setbits_8
(
&
gpio
->
par_feci2c
,
(
GPIO_PAR_FECI2C_MDC_U2TXD
|
GPIO_PAR_FECI2C_MDIO_U2RXD
);
GPIO_PAR_FECI2C_MDC_U2TXD
|
GPIO_PAR_FECI2C_MDIO_U2RXD
);
#endif
#endif
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
gpio
->
par_feci2c
&=
clrbits_8
(
&
gpio
->
par_feci2c
,
(
GPIO_PAR_FECI2C_SDA_UNMASK
|
GPIO_PAR_FECI2C_SCL_UNMASK
);
~
(
GPIO_PAR_FECI2C_SDA_UNMASK
|
GPIO_PAR_FECI2C_SCL_UNMASK
)
);
gpio
->
par_feci2c
|=
setbits_8
(
&
gpio
->
par_feci2c
,
(
GPIO_PAR_FECI2C_SDA_U2TXD
|
GPIO_PAR_FECI2C_SCL_U2RXD
);
GPIO_PAR_FECI2C_SDA_U2TXD
|
GPIO_PAR_FECI2C_SCL_U2RXD
);
#endif
#endif
break
;
break
;
}
}
...
@@ -175,17 +176,17 @@ void uart_port_conf(int port)
...
@@ -175,17 +176,17 @@ void uart_port_conf(int port)
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_CMD_NET)
int
fecpin_setclear
(
struct
eth_device
*
dev
,
int
setclear
)
int
fecpin_setclear
(
struct
eth_device
*
dev
,
int
setclear
)
{
{
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
if
(
setclear
)
{
if
(
setclear
)
{
gpio
->
par_fec
|=
setbits_8
(
&
gpio
->
par_fec
,
GPIO_PAR_FEC_7W_FEC
|
GPIO_PAR_FEC_MII_FEC
;
GPIO_PAR_FEC_7W_FEC
|
GPIO_PAR_FEC_MII_FEC
)
;
gpio
->
par_feci2c
|=
setbits_8
(
&
gpio
->
par_feci2c
,
GPIO_PAR_FECI2C_MDC_MDC
|
GPIO_PAR_FECI2C_MDIO_MDIO
;
GPIO_PAR_FECI2C_MDC_MDC
|
GPIO_PAR_FECI2C_MDIO_MDIO
)
;
}
else
{
}
else
{
gpio
->
par_fec
&=
clrbits_8
(
&
gpio
->
par_fec
,
(
GPIO_PAR_FEC_7W_UNMASK
&
GPIO_PAR_FEC_MII_UNMASK
);
~
(
GPIO_PAR_FEC_7W_UNMASK
&
GPIO_PAR_FEC_MII_UNMASK
)
);
gpio
->
par_feci2c
&=
GPIO_PAR_FECI2C_RMII_UNMASK
;
clrbits_8
(
&
gpio
->
par_feci2c
,
~
GPIO_PAR_FECI2C_RMII_UNMASK
)
;
}
}
return
0
;
return
0
;
}
}
...
@@ -249,17 +250,17 @@ int cpu_init_r(void)
...
@@ -249,17 +250,17 @@ int cpu_init_r(void)
void
uart_port_conf
(
int
port
)
void
uart_port_conf
(
int
port
)
{
{
volatile
u32
*
par
=
(
u32
*
)
MMAP_PAR
;
u32
*
par
=
(
u32
*
)
MMAP_PAR
;
/* Setup Ports: */
/* Setup Ports: */
switch
(
port
)
{
switch
(
port
)
{
case
1
:
case
1
:
*
par
&=
0xFFE7FFFF
;
clrbits_be32
(
par
,
0x00180000
)
;
*
par
|=
0x00180000
;
setbits_be32
(
par
,
0x00180000
)
;
break
;
break
;
case
2
:
case
2
:
*
par
&=
0xFFFFFFFC
;
clrbits_be32
(
par
,
0x00000003
)
;
*
par
&=
0x00000003
;
clrbits_be32
(
par
,
0xFFFFFFFC
)
;
break
;
break
;
}
}
}
}
...
@@ -348,59 +349,59 @@ void cpu_init_f(void)
...
@@ -348,59 +349,59 @@ void cpu_init_f(void)
* already initialized.
* already initialized.
*/
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#ifndef CONFIG_MONITOR_IS_IN_RAM
volatile
sysctrl_t
*
sysctrl
=
(
sysctrl_t
*
)
(
CONFIG_SYS_MBAR
);
sysctrl_t
*
sysctrl
=
(
sysctrl_t
*
)
(
CONFIG_SYS_MBAR
);
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
(
MMAP_GPIO
);
gpio_t
*
gpio
=
(
gpio_t
*
)
(
MMAP_GPIO
);
volatile
csctrl_t
*
csctrl
=
(
csctrl_t
*
)
(
MMAP_FBCS
);
csctrl_t
*
csctrl
=
(
csctrl_t
*
)
(
MMAP_FBCS
);
sysctrl
->
sc_scr
=
CONFIG_SYS_SCR
;
out_be16
(
&
sysctrl
->
sc_scr
,
CONFIG_SYS_SCR
)
;
sysctrl
->
sc_spr
=
CONFIG_SYS_SPR
;
out_be16
(
&
sysctrl
->
sc_spr
,
CONFIG_SYS_SPR
)
;
/* Setup Ports: */
/* Setup Ports: */
gpio
->
gpio_pacnt
=
CONFIG_SYS_PACNT
;
out_be32
(
&
gpio
->
gpio_pacnt
,
CONFIG_SYS_PACNT
)
;
gpio
->
gpio_paddr
=
CONFIG_SYS_PADDR
;
out_be16
(
&
gpio
->
gpio_paddr
,
CONFIG_SYS_PADDR
)
;
gpio
->
gpio_padat
=
CONFIG_SYS_PADAT
;
out_be16
(
&
gpio
->
gpio_padat
,
CONFIG_SYS_PADAT
)
;
gpio
->
gpio_pbcnt
=
CONFIG_SYS_PBCNT
;
out_be32
(
&
gpio
->
gpio_pbcnt
,
CONFIG_SYS_PBCNT
)
;
gpio
->
gpio_pbddr
=
CONFIG_SYS_PBDDR
;
out_be16
(
&
gpio
->
gpio_pbddr
,
CONFIG_SYS_PBDDR
)
;
gpio
->
gpio_pbdat
=
CONFIG_SYS_PBDAT
;
out_be16
(
&
gpio
->
gpio_pbdat
,
CONFIG_SYS_PBDAT
)
;
gpio
->
gpio_pdcnt
=
CONFIG_SYS_PDCNT
;
out_be32
(
&
gpio
->
gpio_pdcnt
,
CONFIG_SYS_PDCNT
)
;
/* Memory Controller: */
/* Memory Controller: */
csctrl
->
cs_br0
=
CONFIG_SYS_BR0_PRELIM
;
out_be32
(
&
csctrl
->
cs_br0
,
CONFIG_SYS_BR0_PRELIM
)
;
csctrl
->
cs_or0
=
CONFIG_SYS_OR0_PRELIM
;
out_be32
(
&
csctrl
->
cs_or0
,
CONFIG_SYS_OR0_PRELIM
)
;
#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
csctrl
->
cs_br1
=
CONFIG_SYS_BR1_PRELIM
;
out_be32
(
&
csctrl
->
cs_br1
,
CONFIG_SYS_BR1_PRELIM
)
;
csctrl
->
cs_or1
=
CONFIG_SYS_OR1_PRELIM
;
out_be32
(
&
csctrl
->
cs_or1
,
CONFIG_SYS_OR1_PRELIM
)
;
#endif
#endif
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
csctrl
->
cs_br2
=
CONFIG_SYS_BR2_PRELIM
;
out_be32
(
&
csctrl
->
cs_br2
,
CONFIG_SYS_BR2_PRELIM
)
;
csctrl
->
cs_or2
=
CONFIG_SYS_OR2_PRELIM
;
out_be32
(
&
csctrl
->
cs_or2
,
CONFIG_SYS_OR2_PRELIM
)
;
#endif
#endif
#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
csctrl
->
cs_br3
=
CONFIG_SYS_BR3_PRELIM
;
out_be32
(
&
csctrl
->
cs_br3
,
CONFIG_SYS_BR3_PRELIM
)
;
csctrl
->
cs_or3
=
CONFIG_SYS_OR3_PRELIM
;
out_be32
(
&
csctrl
->
cs_or3
,
CONFIG_SYS_OR3_PRELIM
)
;
#endif
#endif
#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
csctrl
->
cs_br4
=
CONFIG_SYS_BR4_PRELIM
;
out_be32
(
&
csctrl
->
cs_br4
,
CONFIG_SYS_BR4_PRELIM
)
;
csctrl
->
cs_or4
=
CONFIG_SYS_OR4_PRELIM
;
out_be32
(
&
csctrl
->
cs_or4
,
CONFIG_SYS_OR4_PRELIM
)
;
#endif
#endif
#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
csctrl
->
cs_br5
=
CONFIG_SYS_BR5_PRELIM
;
out_be32
(
&
csctrl
->
cs_br5
,
CONFIG_SYS_BR5_PRELIM
)
;
csctrl
->
cs_or5
=
CONFIG_SYS_OR5_PRELIM
;
out_be32
(
&
csctrl
->
cs_or5
,
CONFIG_SYS_OR5_PRELIM
)
;
#endif
#endif
#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
csctrl
->
cs_br6
=
CONFIG_SYS_BR6_PRELIM
;
out_be32
(
&
csctrl
->
cs_br6
,
CONFIG_SYS_BR6_PRELIM
)
;
csctrl
->
cs_or6
=
CONFIG_SYS_OR6_PRELIM
;
out_be32
(
&
csctrl
->
cs_or6
,
CONFIG_SYS_OR6_PRELIM
)
;
#endif
#endif
#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
csctrl
->
cs_br7
=
CONFIG_SYS_BR7_PRELIM
;
out_be32
(
&
csctrl
->
cs_br7
,
CONFIG_SYS_BR7_PRELIM
)
;
csctrl
->
cs_or7
=
CONFIG_SYS_OR7_PRELIM
;
out_be32
(
&
csctrl
->
cs_or7
,
CONFIG_SYS_OR7_PRELIM
)
;
#endif
#endif
#endif
/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#endif
/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
...
@@ -420,17 +421,21 @@ int cpu_init_r(void)
...
@@ -420,17 +421,21 @@ int cpu_init_r(void)
void
uart_port_conf
(
int
port
)
void
uart_port_conf
(
int
port
)
{
{
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
/* Setup Ports: */
/* Setup Ports: */
switch
(
port
)
{
switch
(
port
)
{
case
0
:
case
0
:
gpio
->
gpio_pbcnt
&=
~
(
GPIO_PBCNT_PB0MSK
|
GPIO_PBCNT_PB1MSK
);
clrbits_be32
(
&
gpio
->
gpio_pbcnt
,
gpio
->
gpio_pbcnt
|=
(
GPIO_PBCNT_URT0_TXD
|
GPIO_PBCNT_URT0_RXD
);
GPIO_PBCNT_PB0MSK
|
GPIO_PBCNT_PB1MSK
);
setbits_be32
(
&
gpio
->
gpio_pbcnt
,
GPIO_PBCNT_URT0_TXD
|
GPIO_PBCNT_URT0_RXD
);
break
;
break
;
case
1
:
case
1
:
gpio
->
gpio_pdcnt
&=
~
(
GPIO_PDCNT_PD1MSK
|
GPIO_PDCNT_PD4MSK
);
clrbits_be32
(
&
gpio
->
gpio_pdcnt
,
gpio
->
gpio_pdcnt
|=
(
GPIO_PDCNT_URT1_RXD
|
GPIO_PDCNT_URT1_TXD
);
GPIO_PDCNT_PD1MSK
|
GPIO_PDCNT_PD4MSK
);
setbits_be32
(
&
gpio
->
gpio_pdcnt
,
GPIO_PDCNT_URT1_RXD
|
GPIO_PDCNT_URT1_TXD
);
break
;
break
;
}
}
}
}
...
@@ -438,13 +443,14 @@ void uart_port_conf(int port)
...
@@ -438,13 +443,14 @@ void uart_port_conf(int port)
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_CMD_NET)
int
fecpin_setclear
(
struct
eth_device
*
dev
,
int
setclear
)
int
fecpin_setclear
(
struct
eth_device
*
dev
,
int
setclear
)
{
{
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
if
(
setclear
)
{
if
(
setclear
)
{
gpio
->
gpio_pbcnt
|=
GPIO_PBCNT_E_MDC
|
GPIO_PBCNT_E_RXER
|
setbits_be32
(
&
gpio
->
gpio_pbcnt
,
GPIO_PBCNT_E_RXD1
|
GPIO_PBCNT_E_RXD2
|
GPIO_PBCNT_E_MDC
|
GPIO_PBCNT_E_RXER
|
GPIO_PBCNT_E_RXD3
|
GPIO_PBCNT_E_TXD1
|
GPIO_PBCNT_E_RXD1
|
GPIO_PBCNT_E_RXD2
|
GPIO_PBCNT_E_TXD2
|
GPIO_PBCNT_E_TXD3
;
GPIO_PBCNT_E_RXD3
|
GPIO_PBCNT_E_TXD1
|
GPIO_PBCNT_E_TXD2
|
GPIO_PBCNT_E_TXD3
);
}
else
{
}
else
{
}
}
return
0
;
return
0
;
...
@@ -469,11 +475,11 @@ void cpu_init_f(void)
...
@@ -469,11 +475,11 @@ void cpu_init_f(void)
*/
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#ifndef CONFIG_MONITOR_IS_IN_RAM
volatile
wdog_t
*
wdog_reg
=
(
wdog_t
*
)
(
MMAP_WDOG
);
wdog_t
*
wdog_reg
=
(
wdog_t
*
)
(
MMAP_WDOG
);
volatile
gpio_t
*
gpio_reg
=
(
gpio_t
*
)
(
MMAP_GPIO
);
gpio_t
*
gpio_reg
=
(
gpio_t
*
)
(
MMAP_GPIO
);
/* Kill watchdog so we can initialize the PLL */
/* Kill watchdog so we can initialize the PLL */
wdog_reg
->
wcr
=
0
;
out_be16
(
&
wdog_reg
->
wcr
,
0
)
;
/* FlexBus Chipselect */
/* FlexBus Chipselect */
init_fbcs
();
init_fbcs
();
...
@@ -498,21 +504,21 @@ int cpu_init_r(void)
...
@@ -498,21 +504,21 @@ int cpu_init_r(void)
void
uart_port_conf
(
int
port
)
void
uart_port_conf
(
int
port
)
{
{
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
/* Setup Ports: */
/* Setup Ports: */
switch
(
port
)
{
switch
(
port
)
{
case
0
:
case
0
:
gpio
->
par_uart
&=
~
UART0_ENABLE_MASK
;
clrbits_be16
(
&
gpio
->
par_uart
,
UART0_ENABLE_MASK
)
;
gpio
->
par_uart
|=
UART0_ENABLE_MASK
;
setbits_be16
(
&
gpio
->
par_uart
,
UART0_ENABLE_MASK
)
;
break
;
break
;
case
1
:
case
1
:
gpio
->
par_uart
&=
~
UART1_ENABLE_MASK
;
clrbits_be16
(
&
gpio
->
par_uart
,
UART1_ENABLE_MASK
)
;
gpio
->
par_uart
|=
UART1_ENABLE_MASK
;
setbits_be16
(
&
gpio
->
par_uart
,
UART1_ENABLE_MASK
)
;
break
;
break
;
case
2
:
case
2
:
gpio
->
par_uart
&=
~
UART2_ENABLE_MASK
;
clrbits_be16
(
&
gpio
->
par_uart
,
UART2_ENABLE_MASK
)
;
gpio
->
par_uart
|=
UART2_ENABLE_MASK
;
setbits_be16
(
&
gpio
->
par_uart
,
UART2_ENABLE_MASK
)
;
break
;
break
;
}
}
}
}
...
@@ -521,24 +527,24 @@ void uart_port_conf(int port)
...
@@ -521,24 +527,24 @@ void uart_port_conf(int port)
int
fecpin_setclear
(
struct
eth_device
*
dev
,
int
setclear
)
int
fecpin_setclear
(
struct
eth_device
*
dev
,
int
setclear
)
{
{
struct
fec_info_s
*
info
=
(
struct
fec_info_s
*
)
dev
->
priv
;
struct
fec_info_s
*
info
=
(
struct
fec_info_s
*
)
dev
->
priv
;
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
if
(
setclear
)
{
if
(
setclear
)
{
/* Enable Ethernet pins */
/* Enable Ethernet pins */
if
(
info
->
iobase
==
CONFIG_SYS_FEC0_IOBASE
)
{
if
(
info
->
iobase
==
CONFIG_SYS_FEC0_IOBASE
)
{
gpio
->
par_feci2c
|=
0x0F00
;
setbits_be16
(
&
gpio
->
par_feci2c
,
0x0f00
)
;
gpio
->
par_fec0hl
|=
0xC0
;
setbits_8
(
&
gpio
->
par_fec0hl
,
0xc0
)
;
}
else
{
}
else
{
gpio
->
par_feci2c
|=
0x00A0
;
setbits_be16
(
&
gpio
->
par_feci2c
,
0x00a0
)
;
gpio
->
par_fec1hl
|=
0xC0
;
setbits_8
(
&
gpio
->
par_fec1hl
,
0xc0
)
;
}
}
}
else
{
}
else
{
if
(
info
->
iobase
==
CONFIG_SYS_FEC0_IOBASE
)
{
if
(
info
->
iobase
==
CONFIG_SYS_FEC0_IOBASE
)
{
gpio
->
par_feci2c
&=
~
0x0F00
;
clrbits_be16
(
&
gpio
->
par_feci2c
,
0x0f00
)
;
gpio
->
par_fec0hl
&=
~
0xC0
;
clrbits_8
(
&
gpio
->
par_fec0hl
,
0xc0
)
;
}
else
{
}
else
{
gpio
->
par_feci2c
&=
~
0x00A0
;
clrbits_be16
(
&
gpio
->
par_feci2c
,
0x00a0
)
;
gpio
->
par_fec1hl
&=
~
0xC0
;
clrbits_8
(
&
gpio
->
par_fec1hl
,
0xc0
)
;
}
}
}
}
...
...
arch/m68k/cpu/mcf52x2/interrupts.c
浏览文件 @
32dbaafa
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2004
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
*
* See file CREDITS for list of people who contributed to this
* See file CREDITS for list of people who contributed to this
...
@@ -28,20 +28,22 @@
...
@@ -28,20 +28,22 @@
#include <watchdog.h>
#include <watchdog.h>
#include <asm/processor.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <asm/immap.h>
#include <asm/io.h>
#ifdef CONFIG_M5272
#ifdef CONFIG_M5272
int
interrupt_init
(
void
)
int
interrupt_init
(
void
)
{
{
volatile
intctrl_t
*
intp
=
(
intctrl_t
*
)
(
MMAP_INTC
);
intctrl_t
*
intp
=
(
intctrl_t
*
)
(
MMAP_INTC
);
/* disable all external interrupts */
/* disable all external interrupts */
intp
->
int_icr1
=
0x88888888
;
out_be32
(
&
intp
->
int_icr1
,
0x88888888
);
intp
->
int_icr2
=
0x88888888
;
out_be32
(
&
intp
->
int_icr2
,
0x88888888
);
intp
->
int_icr3
=
0x88888888
;
out_be32
(
&
intp
->
int_icr3
,
0x88888888
);
intp
->
int_icr4
=
0x88888888
;
out_be32
(
&
intp
->
int_icr4
,
0x88888888
);
intp
->
int_pitr
=
0x00000000
;
out_be32
(
&
intp
->
int_pitr
,
0x00000000
);
/* initialize vector register */
/* initialize vector register */
intp
->
int_pivr
=
0x40
;
out_8
(
&
intp
->
int_pivr
,
0x40
)
;
enable_interrupts
();
enable_interrupts
();
...
@@ -51,10 +53,10 @@ int interrupt_init(void)
...
@@ -51,10 +53,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
#if defined(CONFIG_MCFTMR)
void
dtimer_intr_setup
(
void
)
void
dtimer_intr_setup
(
void
)
{
{
volatile
intctrl_t
*
intp
=
(
intctrl_t
*
)
(
CONFIG_SYS_INTR_BASE
);
intctrl_t
*
intp
=
(
intctrl_t
*
)
(
CONFIG_SYS_INTR_BASE
);
intp
->
int_icr1
&=
~
INT_ICR1_TMR3MASK
;
clrbits_be32
(
&
intp
->
int_icr1
,
INT_ICR1_TMR3MASK
)
;
intp
->
int_icr1
|=
CONFIG_SYS_TMRINTR_PRI
;
setbits_be32
(
&
intp
->
int_icr1
,
CONFIG_SYS_TMRINTR_PRI
)
;
}
}
#endif
/* CONFIG_MCFTMR */
#endif
/* CONFIG_MCFTMR */
#endif
/* CONFIG_M5272 */
#endif
/* CONFIG_M5272 */
...
@@ -63,14 +65,14 @@ void dtimer_intr_setup(void)
...
@@ -63,14 +65,14 @@ void dtimer_intr_setup(void)
defined(CONFIG_M5271) || defined(CONFIG_M5275)
defined(CONFIG_M5271) || defined(CONFIG_M5275)
int
interrupt_init
(
void
)
int
interrupt_init
(
void
)
{
{
volatile
int0_t
*
intp
=
(
int0_t
*
)
(
CONFIG_SYS_INTR_BASE
);
int0_t
*
intp
=
(
int0_t
*
)
(
CONFIG_SYS_INTR_BASE
);
/* Make sure all interrupts are disabled */
/* Make sure all interrupts are disabled */
#if defined(CONFIG_M5208)
#if defined(CONFIG_M5208)
intp
->
imrl0
=
0xFFFFFFFF
;
out_be32
(
&
intp
->
imrl0
,
0xffffffff
)
;
intp
->
imrh0
=
0xFFFFFFFF
;
out_be32
(
&
intp
->
imrh0
,
0xffffffff
)
;
#else
#else
intp
->
imrl0
|=
0x1
;
setbits_be32
(
&
intp
->
imrl0
,
0x1
)
;
#endif
#endif
enable_interrupts
();
enable_interrupts
();
...
@@ -80,11 +82,11 @@ int interrupt_init(void)
...
@@ -80,11 +82,11 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
#if defined(CONFIG_MCFTMR)
void
dtimer_intr_setup
(
void
)
void
dtimer_intr_setup
(
void
)
{
{
volatile
int0_t
*
intp
=
(
int0_t
*
)
(
CONFIG_SYS_INTR_BASE
);
int0_t
*
intp
=
(
int0_t
*
)
(
CONFIG_SYS_INTR_BASE
);
intp
->
icr0
[
CONFIG_SYS_TMRINTR_NO
]
=
CONFIG_SYS_TMRINTR_PRI
;
out_8
(
&
intp
->
icr0
[
CONFIG_SYS_TMRINTR_NO
],
CONFIG_SYS_TMRINTR_PRI
)
;
intp
->
imrl0
&=
0xFFFFFFFE
;
clrbits_be32
(
&
intp
->
imrl0
,
0x00000001
)
;
intp
->
imrl0
&=
~
CONFIG_SYS_TMRINTR_MASK
;
clrbits_be32
(
&
intp
->
imrl0
,
CONFIG_SYS_TMRINTR_MASK
)
;
}
}
#endif
/* CONFIG_MCFTMR */
#endif
/* CONFIG_MCFTMR */
#endif
/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#endif
/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
...
...
arch/m68k/cpu/mcf52x2/speed.c
浏览文件 @
32dbaafa
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
* (C) Copyright 2003
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
* Josef Baumgartner <josef.baumgartner@telex.de>
*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
*
* See file CREDITS for list of people who contributed to this
* See file CREDITS for list of people who contributed to this
...
@@ -27,6 +27,7 @@
...
@@ -27,6 +27,7 @@
#include <common.h>
#include <common.h>
#include <asm/processor.h>
#include <asm/processor.h>
#include <asm/immap.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR
;
DECLARE_GLOBAL_DATA_PTR
;
...
@@ -34,10 +35,10 @@ DECLARE_GLOBAL_DATA_PTR;
...
@@ -34,10 +35,10 @@ DECLARE_GLOBAL_DATA_PTR;
int
get_clocks
(
void
)
int
get_clocks
(
void
)
{
{
#if defined(CONFIG_M5208)
#if defined(CONFIG_M5208)
volatile
pll_t
*
pll
=
(
pll_t
*
)
MMAP_PLL
;
pll_t
*
pll
=
(
pll_t
*
)
MMAP_PLL
;
pll
->
odr
=
CONFIG_SYS_PLL_ODR
;
out_8
(
&
pll
->
odr
,
CONFIG_SYS_PLL_ODR
)
;
pll
->
fdr
=
CONFIG_SYS_PLL_FDR
;
out_8
(
&
pll
->
fdr
,
CONFIG_SYS_PLL_FDR
)
;
#endif
#endif
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
...
@@ -70,14 +71,14 @@ int get_clocks (void)
...
@@ -70,14 +71,14 @@ int get_clocks (void)
#endif
/* CONFIG_M5249 || CONFIG_M5253 */
#endif
/* CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5275)
#if defined(CONFIG_M5275)
volatile
pll_t
*
pll
=
(
volatile
pll_t
*
)(
MMAP_PLL
);
pll_t
*
pll
=
(
pll_t
*
)(
MMAP_PLL
);
/* Setup PLL */
/* Setup PLL */
pll
->
syncr
=
0x01080000
;
out_be32
(
&
pll
->
syncr
,
0x01080000
)
;
while
(
!
(
pll
->
synsr
&
FMPLL_SYNSR_LOCK
))
while
(
!
(
in_be32
(
&
pll
->
synsr
)
&
FMPLL_SYNSR_LOCK
))
;
;
pll
->
syncr
=
0x01000000
;
out_be32
(
&
pll
->
syncr
,
0x01000000
)
;
while
(
!
(
pll
->
synsr
&
FMPLL_SYNSR_LOCK
))
while
(
!
(
in_be32
(
&
pll
->
synsr
)
&
FMPLL_SYNSR_LOCK
))
;
;
#endif
#endif
...
...
board/freescale/m5208evbe/m5208evbe.c
浏览文件 @
32dbaafa
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2008
, 2012
Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
*
* See file CREDITS for list of people who contributed to this
* See file CREDITS for list of people who contributed to this
...
@@ -27,6 +27,7 @@
...
@@ -27,6 +27,7 @@
#include <config.h>
#include <config.h>
#include <common.h>
#include <common.h>
#include <asm/immap.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR
;
DECLARE_GLOBAL_DATA_PTR
;
...
@@ -39,7 +40,7 @@ int checkboard(void)
...
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t
initdram
(
int
board_type
)
phys_size_t
initdram
(
int
board_type
)
{
{
volatile
sdram_t
*
sdram
=
(
volatile
sdram_t
*
)(
MMAP_SDRAM
);
sdram_t
*
sdram
=
(
sdram_t
*
)(
MMAP_SDRAM
);
u32
dramsize
,
i
;
u32
dramsize
,
i
;
dramsize
=
CONFIG_SYS_SDRAM_SIZE
*
0x100000
;
dramsize
=
CONFIG_SYS_SDRAM_SIZE
*
0x100000
;
...
@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
...
@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
}
}
i
--
;
i
--
;
sdram
->
cs0
=
(
CONFIG_SYS_SDRAM_BASE
|
i
);
out_be32
(
&
sdram
->
cs0
,
CONFIG_SYS_SDRAM_BASE
|
i
);
#ifdef CONFIG_SYS_SDRAM_BASE1
#ifdef CONFIG_SYS_SDRAM_BASE1
sdram
->
cs1
=
(
CONFIG_SYS_SDRAM_BASE
|
i
);
out_be32
(
&
sdram
->
cs1
,
CONFIG_SYS_SDRAM_BASE
|
i
);
#endif
#endif
sdram
->
cfg1
=
CONFIG_SYS_SDRAM_CFG1
;
out_be32
(
&
sdram
->
cfg1
,
CONFIG_SYS_SDRAM_CFG1
)
;
sdram
->
cfg2
=
CONFIG_SYS_SDRAM_CFG2
;
out_be32
(
&
sdram
->
cfg2
,
CONFIG_SYS_SDRAM_CFG2
)
;
udelay
(
500
);
udelay
(
500
);
/* Issue PALL */
/* Issue PALL */
sdram
->
ctrl
=
(
CONFIG_SYS_SDRAM_CTRL
|
2
);
out_be32
(
&
sdram
->
ctrl
,
CONFIG_SYS_SDRAM_CTRL
|
2
);
asm
(
"nop"
);
asm
(
"nop"
);
/* Perform two refresh cycles */
/* Perform two refresh cycles */
sdram
->
ctrl
=
CONFIG_SYS_SDRAM_CTRL
|
4
;
out_be32
(
&
sdram
->
ctrl
,
CONFIG_SYS_SDRAM_CTRL
|
4
)
;
sdram
->
ctrl
=
CONFIG_SYS_SDRAM_CTRL
|
4
;
out_be32
(
&
sdram
->
ctrl
,
CONFIG_SYS_SDRAM_CTRL
|
4
)
;
asm
(
"nop"
);
asm
(
"nop"
);
/* Issue LEMR */
/* Issue LEMR */
sdram
->
mode
=
CONFIG_SYS_SDRAM_MODE
;
out_be32
(
&
sdram
->
mode
,
CONFIG_SYS_SDRAM_MODE
)
;
asm
(
"nop"
);
asm
(
"nop"
);
sdram
->
mode
=
CONFIG_SYS_SDRAM_EMOD
;
out_be32
(
&
sdram
->
mode
,
CONFIG_SYS_SDRAM_EMOD
)
;
asm
(
"nop"
);
asm
(
"nop"
);
sdram
->
ctrl
=
(
CONFIG_SYS_SDRAM_CTRL
|
2
);
out_be32
(
&
sdram
->
ctrl
,
CONFIG_SYS_SDRAM_CTRL
|
2
);
asm
(
"nop"
);
asm
(
"nop"
);
sdram
->
ctrl
=
(
CONFIG_SYS_SDRAM_CTRL
&
~
0x80000000
)
|
0x10000F00
;
out_be32
(
&
sdram
->
ctrl
,
(
CONFIG_SYS_SDRAM_CTRL
&
~
0x80000000
)
|
0x10000F00
);
asm
(
"nop"
);
asm
(
"nop"
);
udelay
(
100
);
udelay
(
100
);
...
...
board/freescale/m5253demo/m5253demo.c
浏览文件 @
32dbaafa
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
*
* See file CREDITS for list of people who contributed to this
* See file CREDITS for list of people who contributed to this
...
@@ -109,7 +109,7 @@ int ide_preinit(void)
...
@@ -109,7 +109,7 @@ int ide_preinit(void)
void
ide_set_reset
(
int
idereset
)
void
ide_set_reset
(
int
idereset
)
{
{
volatile
atac_t
*
ata
=
(
atac_t
*
)
CONFIG_SYS_ATA_BASE_ADDR
;
atac_t
*
ata
=
(
atac_t
*
)
CONFIG_SYS_ATA_BASE_ADDR
;
long
period
;
long
period
;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int
piotms
[
5
][
9
]
=
{
{
70
,
165
,
60
,
30
,
50
,
5
,
20
,
0
,
35
},
/* PIO 0 */
int
piotms
[
5
][
9
]
=
{
{
70
,
165
,
60
,
30
,
50
,
5
,
20
,
0
,
35
},
/* PIO 0 */
...
@@ -120,7 +120,8 @@ void ide_set_reset(int idereset)
...
@@ -120,7 +120,8 @@ void ide_set_reset(int idereset)
};
};
if
(
idereset
)
{
if
(
idereset
)
{
ata
->
cr
=
0
;
/* control reset */
/* control reset */
out_8
(
&
ata
->
cr
,
0
);
udelay
(
100
);
udelay
(
100
);
}
else
{
}
else
{
mbar2_writeLong
(
CIM_MISCCR
,
CIM_MISCCR_CPUEND
);
mbar2_writeLong
(
CIM_MISCCR
,
CIM_MISCCR_CPUEND
);
...
@@ -129,17 +130,19 @@ void ide_set_reset(int idereset)
...
@@ -129,17 +130,19 @@ void ide_set_reset(int idereset)
period
=
1000000000
/
(
CONFIG_SYS_CLK
/
2
);
/* period in ns */
period
=
1000000000
/
(
CONFIG_SYS_CLK
/
2
);
/* period in ns */
/*ata->ton = CALC_TIMING (180); */
/*ata->ton = CALC_TIMING (180); */
ata
->
t1
=
CALC_TIMING
(
piotms
[
2
][
0
]);
out_8
(
&
ata
->
t1
,
CALC_TIMING
(
piotms
[
2
][
0
]));
ata
->
t2w
=
CALC_TIMING
(
piotms
[
2
][
1
]);
out_8
(
&
ata
->
t2w
,
CALC_TIMING
(
piotms
[
2
][
1
]));
ata
->
t2r
=
CALC_TIMING
(
piotms
[
2
][
1
]);
out_8
(
&
ata
->
t2r
,
CALC_TIMING
(
piotms
[
2
][
1
]));
ata
->
ta
=
CALC_TIMING
(
piotms
[
2
][
8
]);
out_8
(
&
ata
->
ta
,
CALC_TIMING
(
piotms
[
2
][
8
]));
ata
->
trd
=
CALC_TIMING
(
piotms
[
2
][
7
]);
out_8
(
&
ata
->
trd
,
CALC_TIMING
(
piotms
[
2
][
7
]));
ata
->
t4
=
CALC_TIMING
(
piotms
[
2
][
3
]);
out_8
(
&
ata
->
t4
,
CALC_TIMING
(
piotms
[
2
][
3
]));
ata
->
t9
=
CALC_TIMING
(
piotms
[
2
][
6
]);
out_8
(
&
ata
->
t9
,
CALC_TIMING
(
piotms
[
2
][
6
]));
ata
->
cr
=
0x40
;
/* IORDY enable */
/* IORDY enable */
out_8
(
&
ata
->
cr
,
0x40
);
udelay
(
2000
);
udelay
(
2000
);
ata
->
cr
|=
0x01
;
/* IORDY enable */
/* IORDY enable */
setbits_8
(
&
ata
->
cr
,
0x01
);
}
}
}
}
#endif
/* CONFIG_CMD_IDE */
#endif
/* CONFIG_CMD_IDE */
...
...
board/freescale/m5253evbe/m5253evbe.c
浏览文件 @
32dbaafa
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
*
* See file CREDITS for list of people who contributed to this
* See file CREDITS for list of people who contributed to this
...
@@ -26,6 +26,7 @@
...
@@ -26,6 +26,7 @@
#include <common.h>
#include <common.h>
#include <asm/immap.h>
#include <asm/immap.h>
#include <asm/io.h>
int
checkboard
(
void
)
int
checkboard
(
void
)
{
{
...
@@ -101,7 +102,7 @@ int ide_preinit(void)
...
@@ -101,7 +102,7 @@ int ide_preinit(void)
void
ide_set_reset
(
int
idereset
)
void
ide_set_reset
(
int
idereset
)
{
{
volatile
atac_t
*
ata
=
(
atac_t
*
)
CONFIG_SYS_ATA_BASE_ADDR
;
atac_t
*
ata
=
(
atac_t
*
)
CONFIG_SYS_ATA_BASE_ADDR
;
long
period
;
long
period
;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int
piotms
[
5
][
9
]
=
{
{
70
,
165
,
60
,
30
,
50
,
5
,
20
,
0
,
35
},
/* PIO 0 */
int
piotms
[
5
][
9
]
=
{
{
70
,
165
,
60
,
30
,
50
,
5
,
20
,
0
,
35
},
/* PIO 0 */
...
@@ -112,7 +113,8 @@ void ide_set_reset(int idereset)
...
@@ -112,7 +113,8 @@ void ide_set_reset(int idereset)
};
};
if
(
idereset
)
{
if
(
idereset
)
{
ata
->
cr
=
0
;
/* control reset */
/* control reset */
out_8
(
&
ata
->
cr
,
0
);
udelay
(
100
);
udelay
(
100
);
}
else
{
}
else
{
mbar2_writeLong
(
CIM_MISCCR
,
CIM_MISCCR_CPUEND
);
mbar2_writeLong
(
CIM_MISCCR
,
CIM_MISCCR_CPUEND
);
...
@@ -121,17 +123,19 @@ void ide_set_reset(int idereset)
...
@@ -121,17 +123,19 @@ void ide_set_reset(int idereset)
period
=
1000000000
/
(
CONFIG_SYS_CLK
/
2
);
/* period in ns */
period
=
1000000000
/
(
CONFIG_SYS_CLK
/
2
);
/* period in ns */
/*ata->ton = CALC_TIMING (180); */
/*ata->ton = CALC_TIMING (180); */
ata
->
t1
=
CALC_TIMING
(
piotms
[
2
][
0
]);
out_8
(
&
ata
->
t1
,
CALC_TIMING
(
piotms
[
2
][
0
]));
ata
->
t2w
=
CALC_TIMING
(
piotms
[
2
][
1
]);
out_8
(
&
ata
->
t2w
,
CALC_TIMING
(
piotms
[
2
][
1
]));
ata
->
t2r
=
CALC_TIMING
(
piotms
[
2
][
1
]);
out_8
(
&
ata
->
t2r
,
CALC_TIMING
(
piotms
[
2
][
1
]));
ata
->
ta
=
CALC_TIMING
(
piotms
[
2
][
8
]);
out_8
(
&
ata
->
ta
,
CALC_TIMING
(
piotms
[
2
][
8
]));
ata
->
trd
=
CALC_TIMING
(
piotms
[
2
][
7
]);
out_8
(
&
ata
->
trd
,
CALC_TIMING
(
piotms
[
2
][
7
]));
ata
->
t4
=
CALC_TIMING
(
piotms
[
2
][
3
]);
out_8
(
&
ata
->
t4
,
CALC_TIMING
(
piotms
[
2
][
3
]));
ata
->
t9
=
CALC_TIMING
(
piotms
[
2
][
6
]);
out_8
(
&
ata
->
t9
,
CALC_TIMING
(
piotms
[
2
][
6
]));
ata
->
cr
=
0x40
;
/* IORDY enable */
/* IORDY enable */
out_8
(
&
ata
->
cr
,
0x40
);
udelay
(
2000
);
udelay
(
2000
);
ata
->
cr
|=
0x01
;
/* IORDY enable */
/* IORDY enable */
setbits_8
(
&
ata
->
cr
,
0x01
);
}
}
}
}
#endif
/* CONFIG_CMD_IDE */
#endif
/* CONFIG_CMD_IDE */
board/freescale/m5272c3/m5272c3.c
浏览文件 @
32dbaafa
...
@@ -2,6 +2,8 @@
...
@@ -2,6 +2,8 @@
* (C) Copyright 2000-2003
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
*
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* See file CREDITS for list of people who contributed to this
* See file CREDITS for list of people who contributed to this
* project.
* project.
*
*
...
@@ -23,6 +25,7 @@
...
@@ -23,6 +25,7 @@
#include <common.h>
#include <common.h>
#include <asm/immap.h>
#include <asm/immap.h>
#include <asm/io.h>
int
checkboard
(
void
)
{
int
checkboard
(
void
)
{
...
@@ -32,10 +35,10 @@ int checkboard (void) {
...
@@ -32,10 +35,10 @@ int checkboard (void) {
};
};
phys_size_t
initdram
(
int
board_type
)
{
phys_size_t
initdram
(
int
board_type
)
{
volatile
sdramctrl_t
*
sdp
=
(
sdramctrl_t
*
)(
MMAP_SDRAM
);
sdramctrl_t
*
sdp
=
(
sdramctrl_t
*
)(
MMAP_SDRAM
);
sdp
->
sdram_sdtr
=
0xf539
;
out_be16
(
&
sdp
->
sdram_sdtr
,
0xf539
)
;
sdp
->
sdram_sdcr
=
0x4211
;
out_be16
(
&
sdp
->
sdram_sdcr
,
0x4211
)
;
/* Dummy write to start SDRAM */
/* Dummy write to start SDRAM */
*
((
volatile
unsigned
long
*
)
0
)
=
0
;
*
((
volatile
unsigned
long
*
)
0
)
=
0
;
...
...
board/freescale/m5275evb/m5275evb.c
浏览文件 @
32dbaafa
...
@@ -4,6 +4,8 @@
...
@@ -4,6 +4,8 @@
*
*
* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
*
*
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* See file CREDITS for list of people who contributed to this
* See file CREDITS for list of people who contributed to this
* project.
* project.
*
*
...
@@ -25,6 +27,7 @@
...
@@ -25,6 +27,7 @@
#include <common.h>
#include <common.h>
#include <asm/immap.h>
#include <asm/immap.h>
#include <asm/io.h>
#define PERIOD 13
/* system bus period in ns */
#define PERIOD 13
/* system bus period in ns */
#define SDRAM_TREFI 7800
/* in ns */
#define SDRAM_TREFI 7800
/* in ns */
...
@@ -38,67 +41,68 @@ int checkboard(void)
...
@@ -38,67 +41,68 @@ int checkboard(void)
phys_size_t
initdram
(
int
board_type
)
phys_size_t
initdram
(
int
board_type
)
{
{
volatile
sdramctrl_t
*
sdp
=
(
sdramctrl_t
*
)(
MMAP_SDRAM
);
sdramctrl_t
*
sdp
=
(
sdramctrl_t
*
)(
MMAP_SDRAM
);
volatile
gpio_t
*
gpio_reg
=
(
gpio_t
*
)(
MMAP_GPIO
);
gpio_t
*
gpio_reg
=
(
gpio_t
*
)(
MMAP_GPIO
);
gpio_reg
->
par_sdram
=
0x3FF
;
/* Enable SDRAM */
/* Enable SDRAM */
out_be16
(
&
gpio_reg
->
par_sdram
,
0x3FF
);
/* Set up chip select */
/* Set up chip select */
sdp
->
sdbar0
=
CONFIG_SYS_SDRAM_BASE
;
out_be32
(
&
sdp
->
sdbar0
,
CONFIG_SYS_SDRAM_BASE
)
;
sdp
->
sdbmr0
=
MCF_SDRAMC_SDMRn_BAM_32M
|
MCF_SDRAMC_SDMRn_V
;
out_be32
(
&
sdp
->
sdbmr0
,
MCF_SDRAMC_SDMRn_BAM_32M
|
MCF_SDRAMC_SDMRn_V
)
;
/* Set up timing */
/* Set up timing */
sdp
->
sdcfg1
=
0x83711630
;
out_be32
(
&
sdp
->
sdcfg1
,
0x83711630
)
;
sdp
->
sdcfg2
=
0x46770000
;
out_be32
(
&
sdp
->
sdcfg2
,
0x46770000
)
;
/* Enable clock */
/* Enable clock */
sdp
->
sdcr
=
MCF_SDRAMC_SDCR_MODE_EN
|
MCF_SDRAMC_SDCR_CKE
;
out_be32
(
&
sdp
->
sdcr
,
MCF_SDRAMC_SDCR_MODE_EN
|
MCF_SDRAMC_SDCR_CKE
)
;
/* Set precharge */
/* Set precharge */
s
dp
->
sdcr
|=
MCF_SDRAMC_SDCR_IPALL
;
s
etbits_be32
(
&
sdp
->
sdcr
,
MCF_SDRAMC_SDCR_IPALL
)
;
/* Dummy write to start SDRAM */
/* Dummy write to start SDRAM */
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
/* Send LEMR */
/* Send LEMR */
s
dp
->
sdmr
=
MCF_SDRAMC_SDMR_BNKAD_LEMR
s
etbits_be32
(
&
sdp
->
sdmr
,
|
MCF_SDRAMC_SDMR_AD
(
0x0
)
MCF_SDRAMC_SDMR_BNKAD_LEMR
|
MCF_SDRAMC_SDMR_AD
(
0x0
)
|
|
MCF_SDRAMC_SDMR_CMD
;
MCF_SDRAMC_SDMR_CMD
)
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
/* Send LMR */
/* Send LMR */
sdp
->
sdmr
=
0x058d0000
;
out_be32
(
&
sdp
->
sdmr
,
0x058d0000
)
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
/* Stop sending commands */
/* Stop sending commands */
sdp
->
sdmr
&=
~
(
MCF_SDRAMC_SDMR_CMD
);
clrbits_be32
(
&
sdp
->
sdmr
,
MCF_SDRAMC_SDMR_CMD
);
/* Set precharge */
/* Set precharge */
s
dp
->
sdcr
|=
MCF_SDRAMC_SDCR_IPALL
;
s
etbits_be32
(
&
sdp
->
sdcr
,
MCF_SDRAMC_SDCR_IPALL
)
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
/* Stop manual precharge, send 2 IREF */
/* Stop manual precharge, send 2 IREF */
sdp
->
sdcr
&=
~
(
MCF_SDRAMC_SDCR_IPALL
);
clrbits_be32
(
&
sdp
->
sdcr
,
MCF_SDRAMC_SDCR_IPALL
);
s
dp
->
sdcr
|=
MCF_SDRAMC_SDCR_IREF
;
s
etbits_be32
(
&
sdp
->
sdcr
,
MCF_SDRAMC_SDCR_IREF
)
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
/* Write mode register, clear reset DLL */
sdp
->
sdmr
=
0x018d0000
;
out_be32
(
&
sdp
->
sdmr
,
0x018d0000
)
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
*
((
volatile
unsigned
long
*
)
CONFIG_SYS_SDRAM_BASE
)
=
0xa5a59696
;
/* Stop sending commands */
/* Stop sending commands */
sdp
->
sdmr
&=
~
(
MCF_SDRAMC_SDMR_CMD
);
clrbits_be32
(
&
sdp
->
sdmr
,
MCF_SDRAMC_SDMR_CMD
);
sdp
->
sdcr
&=
~
(
MCF_SDRAMC_SDCR_MODE_EN
);
clrbits_be32
(
&
sdp
->
sdcr
,
MCF_SDRAMC_SDCR_MODE_EN
);
/* Turn on auto refresh, lock SDMR */
/* Turn on auto refresh, lock SDMR */
sdp
->
sdcr
=
out_be32
(
&
sdp
->
sdcr
,
MCF_SDRAMC_SDCR_CKE
MCF_SDRAMC_SDCR_CKE
|
MCF_SDRAMC_SDCR_REF
|
MCF_SDRAMC_SDCR_REF
|
MCF_SDRAMC_SDCR_MUX
(
1
)
|
MCF_SDRAMC_SDCR_MUX
(
1
)
/* 1 added to round up */
/* 1 added to round up */
|
MCF_SDRAMC_SDCR_RCNT
((
SDRAM_TREFI
/
(
PERIOD
*
64
))
-
1
+
1
)
|
MCF_SDRAMC_SDCR_RCNT
((
SDRAM_TREFI
/
(
PERIOD
*
64
))
-
1
+
1
)
|
MCF_SDRAMC_SDCR_DQS_OE
(
0x3
);
|
MCF_SDRAMC_SDCR_DQS_OE
(
0x3
)
)
;
return
CONFIG_SYS_SDRAM_SIZE
*
1024
*
1024
;
return
CONFIG_SYS_SDRAM_SIZE
*
1024
*
1024
;
};
};
...
...
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