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2bf95577
编写于
1月 08, 2014
作者:
M
Masahiro Yamada
提交者:
Tom Rini
1月 24, 2014
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电子邮件补丁
差异文件
blackfin: delete unused header files
Signed-off-by:
N
Masahiro Yamada
<
yamada.m@jp.panasonic.com
>
上级
4d54b43a
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
0 addition
and
151 deletion
+0
-151
arch/blackfin/include/asm/mach-common/bits/lockbox.h
arch/blackfin/include/asm/mach-common/bits/lockbox.h
+0
-62
arch/blackfin/include/asm/mach-common/bits/sport.h
arch/blackfin/include/asm/mach-common/bits/sport.h
+0
-89
未找到文件。
arch/blackfin/include/asm/mach-common/bits/lockbox.h
已删除
100644 → 0
浏览文件 @
4d54b43a
/*
* Lockbox/Security Masks
*/
#ifndef __BFIN_PERIPHERAL_LOCKBOX__
#define __BFIN_PERIPHERAL_LOCKBOX__
#ifndef __ASSEMBLY__
#include "bootrom.h"
/* SESR argument structure. Expected to reside at 0xFF900018. */
typedef
struct
SESR_args
{
unsigned
short
usFlags
;
/* security firmware flags */
unsigned
short
usIRQMask
;
/* interrupt mask */
unsigned
long
ulMessageSize
;
/* message length in bytes */
unsigned
long
ulSFEntryPoint
;
/* entry point of secure function */
unsigned
long
ulMessagePtr
;
/* pointer to the buffer containing
the digital signature and message */
unsigned
long
ulReserved1
;
/* reserved */
unsigned
long
ulReserved2
;
/* reserved */
}
tSESR_args
;
/* Secure Entry Service Routine */
static
void
(
*
const
sesr
)(
void
)
=
(
void
*
)
_BOOTROM_SESR
;
#endif
/* SESR flags argument bitfields */
#define SESR_FLAGS_STAY_AT_NMI 0x0000
#define SESR_FLAGS_DROP_BELOW_NMI 0x0001
#define SESR_FLAGS_NO_SF_DMA 0x0000
#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002
#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000
#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100
/* Bit masks for SECURE_SYSSWT */
#define EMUDABL 0x00000001
/* Emulation Disable */
#define RSTDABL 0x00000002
/* Reset Disable */
#define L1IDABL 0x0000001c
/* L1 Instruction Memory Disable */
#define L1DADABL 0x000000e0
/* L1 Data Bank A Memory Disable */
#define L1DBDABL 0x00000700
/* L1 Data Bank B Memory Disable */
#define DMA0OVR 0x00000800
/* DMA0 Memory Access Override */
#define DMA1OVR 0x00001000
/* DMA1 Memory Access Override */
#define EMUOVR 0x00004000
/* Emulation Override */
#define OTPSEN 0x00008000
/* OTP Secrets Enable */
#define L2DABL 0x00070000
/* L2 Memory Disable */
/* Bit masks for SECURE_CONTROL */
#define SECURE0 0x0001
/* SECURE 0 */
#define SECURE1 0x0002
/* SECURE 1 */
#define SECURE2 0x0004
/* SECURE 2 */
#define SECURE3 0x0008
/* SECURE 3 */
/* Bit masks for SECURE_STATUS */
#define SECMODE 0x0003
/* Secured Mode Control State */
#define NMI 0x0004
/* Non Maskable Interrupt */
#define AFVALID 0x0008
/* Authentication Firmware Valid */
#define AFEXIT 0x0010
/* Authentication Firmware Exit */
#define SECSTAT 0x00e0
/* Secure Status */
#endif
arch/blackfin/include/asm/mach-common/bits/sport.h
已删除
100644 → 0
浏览文件 @
4d54b43a
/*
* SPORT Masks
*/
#ifndef __BFIN_PERIPHERAL_SPORT__
#define __BFIN_PERIPHERAL_SPORT__
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001
/* TX enable */
#define ITCLK 0x0002
/* Internal TX Clock Select */
#define TDTYPE 0x000C
/* TX Data Formatting Select */
#define DTYPE_NORM 0x0004
/* Data Format Normal */
#define DTYPE_ULAW 0x0008
/* Compand Using u-Law */
#define DTYPE_ALAW 0x000C
/* Compand Using A-Law */
#define TLSBIT 0x0010
/* TX Bit Order */
#define ITFS 0x0200
/* Internal TX Frame Sync Select */
#define TFSR 0x0400
/* TX Frame Sync Required Select */
#define DITFS 0x0800
/* Data Independent TX Frame Sync Select */
#define LTFS 0x1000
/* Low TX Frame Sync Select */
#define LATFS 0x2000
/* Late TX Frame Sync Select */
#define TCKFE 0x4000
/* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
#define SLEN 0x001F
/* TX Word Length */
#define TXSE 0x0100
/* TX Secondary Enable */
#define TSFSE 0x0200
/* TX Stereo Frame Sync Enable */
#define TRFST 0x0400
/* TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001
/* RX enable */
#define IRCLK 0x0002
/* Internal RX Clock Select */
#define RDTYPE 0x000C
/* RX Data Formatting Select */
#define DTYPE_NORM 0x0004
/* Data Format Normal */
#define DTYPE_ULAW 0x0008
/* Compand Using u-Law */
#define DTYPE_ALAW 0x000C
/* Compand Using A-Law */
#define RLSBIT 0x0010
/* RX Bit Order */
#define IRFS 0x0200
/* Internal RX Frame Sync Select */
#define RFSR 0x0400
/* RX Frame Sync Required Select */
#define LRFS 0x1000
/* Low RX Frame Sync Select */
#define LARFS 0x2000
/* Late RX Frame Sync Select */
#define RCKFE 0x4000
/* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN 0x001F
/* RX Word Length */
#define RXSE 0x0100
/* RX Secondary Enable */
#define RSFSE 0x0200
/* RX Stereo Frame Sync Enable */
#define RRFST 0x0400
/* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001
/* RX FIFO Not Empty Status */
#define RUVF 0x0002
/* RX Underflow Status */
#define ROVF 0x0004
/* RX Overflow Status */
#define TXF 0x0008
/* TX FIFO Full Status */
#define TUVF 0x0010
/* TX Underflow Status */
#define TOVF 0x0020
/* TX Overflow Status */
#define TXHRE 0x0040
/* TX Hold Register Empty */
/* SPORTx_MCMC1 Masks */
#define WSIZE 0xF000
/* Multichannel Window Size Field */
#define WOFF 0x03FF
/* Multichannel Window Offset Field */
/* SPORTx_MCMC2 Masks */
#define MCCRM 0x0003
/* Multichannel Clock Recovery Mode */
#define REC_BYPASS 0x0000
/* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002
/* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003
/* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004
/* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008
/* Multichannel DMA Receive Packing */
#define MCMEN 0x0010
/* Multichannel Frame Mode Enable */
#define FSDR 0x0080
/* Multichannel Frame Sync to Data Relationship */
#define MFD 0xF000
/* Multichannel Frame Delay */
#define MFD_0 0x0000
/* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000
/* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000
/* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000
/* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000
/* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000
/* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000
/* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000
/* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000
/* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000
/* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000
/* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000
/* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000
/* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000
/* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000
/* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000
/* Multichannel Frame Delay = 15 */
#endif
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