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提交 2b4ffbf6 编写于 作者: C Chris Packham 提交者： Stefan Roese
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ARM: mvebu: a38x: sync ddr training code with upstream 

This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdef

  find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
    xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
		-UCONFIG_APN806 -UCONFIG_MC_STATIC \
		-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
		-UCONFIG_64BIT

INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.

Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>
上级 00a77677
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Showing with 7944 addition and 5047 deletion
board/CZ.NIC/turris_omnia/turris_omnia.c
浏览文件 @ 2b4ffbf6
......@@ -27,7 +27,7 @@
# include <wdt.h>
#endif
#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -200,7 +200,8 @@ static bool omnia_read_eeprom(struct omnia_eeprom *oep)
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
static struct hws_topology_map board_topology_map_1g = {
static struct mv_ddr_topology_map board_topology_map_1g = {
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
......@@ -209,17 +210,19 @@ static struct hws_topology_map board_topology_map_1g = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1600K, /* speed_bin */
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
HWS_TEMP_NORMAL, /* temperature */
HWS_TIM_2T} }, /* timing (force 2t) */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
MV_DDR_TEMP_NORMAL} }, /* temperature */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
static struct hws_topology_map board_topology_map_2g = {
static struct mv_ddr_topology_map board_topology_map_2g = {
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
......@@ -228,17 +231,18 @@ static struct hws_topology_map board_topology_map_2g = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1600K, /* speed_bin */
BUS_WIDTH_16, /* memory_width */
MEM_8G, /* mem_size */
MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
MV_DDR_DIE_CAP_8GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
HWS_TEMP_NORMAL, /* temperature */
HWS_TIM_2T} }, /* timing (force 2t) */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
MV_DDR_TEMP_NORMAL} }, /* temperature */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
struct hws_topology_map *ddr3_get_topology_map(void)
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
static int mem = 0;
struct omnia_eeprom oep;
......
board/Marvell/db-88f6820-amc/db-88f6820-amc.c
浏览文件 @ 2b4ffbf6
......@@ -11,7 +11,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -55,7 +55,8 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
static struct hws_topology_map board_topology_map = {
static struct mv_ddr_topology_map board_topology_map = {
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
......@@ -64,17 +65,18 @@ static struct hws_topology_map board_topology_map = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1866L, /* speed_bin */
BUS_WIDTH_8, /* memory_width */
MEM_2G, /* mem_size */
MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
MV_DDR_DIE_CAP_2GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
MV_DDR_TEMP_LOW} }, /* temperature */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
struct hws_topology_map *ddr3_get_topology_map(void)
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
/* Return the board topology as defined in the board code */
return &board_topology_map;
......
board/Marvell/db-88f6820-gp/db-88f6820-gp.c
浏览文件 @ 2b4ffbf6
......@@ -11,7 +11,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -76,7 +76,8 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
static struct hws_topology_map board_topology_map = {
static struct mv_ddr_topology_map board_topology_map = {
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
......@@ -85,17 +86,18 @@ static struct hws_topology_map board_topology_map = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1866L, /* speed_bin */
BUS_WIDTH_8, /* memory_width */
MEM_4G, /* mem_size */
MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
MV_DDR_TEMP_LOW} }, /* temperature */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
struct hws_topology_map *ddr3_get_topology_map(void)
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
/* Return the board topology as defined in the board code */
return &board_topology_map;
......
board/gdsys/a38x/controlcenterdc.c
浏览文件 @ 2b4ffbf6
......@@ -12,7 +12,7 @@
#include <asm/arch/cpu.h>
#include <asm-generic/gpio.h>
#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
#include "keyprogram.h"
......@@ -39,7 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
static struct hws_topology_map ddr_topology_map = {
static struct mv_ddr_topology_map ddr_topology_map = {
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
......@@ -48,14 +49,16 @@ static struct hws_topology_map ddr_topology_map = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1600K, /* speed_bin */
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_533, /* frequency */
0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
MV_DDR_TEMP_LOW} }, /* temperature */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
static struct serdes_map serdes_topology_map[] = {
......@@ -121,7 +124,7 @@ void board_pex_config(void)
#endif
}
struct hws_topology_map *ddr3_get_topology_map(void)
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
return &ddr_topology_map;
}
......
board/solidrun/clearfog/clearfog.c
浏览文件 @ 2b4ffbf6
......@@ -11,7 +11,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -69,7 +69,8 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
static struct hws_topology_map board_topology_map = {
static struct mv_ddr_topology_map board_topology_map = {
DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
......@@ -78,17 +79,18 @@ static struct hws_topology_map board_topology_map = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1600K, /* speed_bin */
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
MV_DDR_TEMP_LOW} }, /* temperature */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
struct hws_topology_map *ddr3_get_topology_map(void)
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
/* Return the board topology as defined in the board code */
return &board_topology_map;
......
drivers/ddr/marvell/a38x/Makefile
浏览文件 @ 2b4ffbf6
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_SPL_BUILD) += ddr3_a38x.o
obj-$(CONFIG_SPL_BUILD) += ddr3_a38x_training.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_plat.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_sys_env_lib.o
obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o
obj-$(CONFIG_SPL_BUILD) += ddr3_hws_hw_training.o
obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o
......@@ -13,5 +12,8 @@ obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_static.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_build_message.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_common.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_spd.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_topology.o
obj-$(CONFIG_SPL_BUILD) += xor.o
drivers/ddr/marvell/a38x/ddr3_a38x.c 已删除 100644 → 0
浏览文件 @ 00a77677
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "ddr3_init.h"
#define A38X_NUMBER_OF_INTERFACES 5
#define SAR_DEV_ID_OFFS 27
#define SAR_DEV_ID_MASK 0x7
/* Termal Sensor Registers */
#define TSEN_STATE_REG 0xe4070
#define TSEN_STATE_OFFSET 31
#define TSEN_STATE_MASK (0x1 << TSEN_STATE_OFFSET)
#define TSEN_CONF_REG 0xe4074
#define TSEN_CONF_RST_OFFSET 8
#define TSEN_CONF_RST_MASK (0x1 << TSEN_CONF_RST_OFFSET)
#define TSEN_STATUS_REG 0xe4078
#define TSEN_STATUS_READOUT_VALID_OFFSET 10
#define TSEN_STATUS_READOUT_VALID_MASK (0x1 << \
TSEN_STATUS_READOUT_VALID_OFFSET)
#define TSEN_STATUS_TEMP_OUT_OFFSET 0
#define TSEN_STATUS_TEMP_OUT_MASK (0x3ff << TSEN_STATUS_TEMP_OUT_OFFSET)
static struct dfx_access interface_map[] = {
/* Pipe Client */
{ 0, 17 },
{ 1, 7 },
{ 1, 11 },
{ 0, 3 },
{ 1, 25 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 }
};
/* This array hold the board round trip delay (DQ and CK) per <interface,bus> */
struct trip_delay_element a38x_board_round_trip_delay_array[] = {
/* 1st board */
/* Interface bus DQS-delay CK-delay */
{ 3952, 5060 },
{ 3192, 4493 },
{ 4785, 6677 },
{ 3413, 7267 },
{ 4282, 6086 }, /* ECC PUP */
{ 3952, 5134 },
{ 3192, 4567 },
{ 4785, 6751 },
{ 3413, 7341 },
{ 4282, 6160 }, /* ECC PUP */
/* 2nd board */
/* Interface bus DQS-delay CK-delay */
{ 3952, 5060 },
{ 3192, 4493 },
{ 4785, 6677 },
{ 3413, 7267 },
{ 4282, 6086 }, /* ECC PUP */
{ 3952, 5134 },
{ 3192, 4567 },
{ 4785, 6751 },
{ 3413, 7341 },
{ 4282, 6160 } /* ECC PUP */
};
static u8 a38x_bw_per_freq[DDR_FREQ_LIMIT] = {
0x3, /* DDR_FREQ_100 */
0x4, /* DDR_FREQ_400 */
0x4, /* DDR_FREQ_533 */
0x5, /* DDR_FREQ_667 */
0x5, /* DDR_FREQ_800 */
0x5, /* DDR_FREQ_933 */
0x5, /* DDR_FREQ_1066 */
0x3, /* DDR_FREQ_311 */
0x3, /* DDR_FREQ_333 */
0x4, /* DDR_FREQ_467 */
0x5, /* DDR_FREQ_850 */
0x5, /* DDR_FREQ_600 */
0x3, /* DDR_FREQ_300 */
0x5, /* DDR_FREQ_900 */
0x3, /* DDR_FREQ_360 */
0x5 /* DDR_FREQ_1000 */
};
static u8 a38x_rate_per_freq[DDR_FREQ_LIMIT] = {
/*TBD*/ 0x1, /* DDR_FREQ_100 */
0x2, /* DDR_FREQ_400 */
0x2, /* DDR_FREQ_533 */
0x2, /* DDR_FREQ_667 */
0x2, /* DDR_FREQ_800 */
0x3, /* DDR_FREQ_933 */
0x3, /* DDR_FREQ_1066 */
0x1, /* DDR_FREQ_311 */
0x1, /* DDR_FREQ_333 */
0x2, /* DDR_FREQ_467 */
0x2, /* DDR_FREQ_850 */
0x2, /* DDR_FREQ_600 */
0x1, /* DDR_FREQ_300 */
0x2, /* DDR_FREQ_900 */
0x1, /* DDR_FREQ_360 */
0x2 /* DDR_FREQ_1000 */
};
static u16 a38x_vco_freq_per_sar[] = {
666, /* 0 */
1332,
800,
1600,
1066,
2132,
1200,
2400,
1332,
1332,
1500,
1500,
1600, /* 12 */
1600,
1700,
1700,
1866,
1866,
1800, /* 18 */
2000,
2000,
4000,
2132,
2132,
2300,
2300,
2400,
2400,
2500,
2500,
800
};
u32 pipe_multicast_mask;
u32 dq_bit_map_2_phy_pin[] = {
1, 0, 2, 6, 9, 8, 3, 7, /* 0 */
8, 9, 1, 7, 2, 6, 3, 0, /* 1 */
3, 9, 7, 8, 1, 0, 2, 6, /* 2 */
1, 0, 6, 2, 8, 3, 7, 9, /* 3 */
0, 1, 2, 9, 7, 8, 3, 6, /* 4 */
};
static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
enum hws_ddr_freq freq);
/*
* Read temperature TJ value
*/
u32 ddr3_ctrl_get_junc_temp(u8 dev_num)
{
int reg = 0;
/* Initiates TSEN hardware reset once */
if ((reg_read(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0)
reg_bit_set(TSEN_CONF_REG, TSEN_CONF_RST_MASK);
mdelay(10);
/* Check if the readout field is valid */
if ((reg_read(TSEN_STATUS_REG) & TSEN_STATUS_READOUT_VALID_MASK) == 0) {
printf("%s: TSEN not ready\n", __func__);
return 0;
}
reg = reg_read(TSEN_STATUS_REG);
reg = (reg & TSEN_STATUS_TEMP_OUT_MASK) >> TSEN_STATUS_TEMP_OUT_OFFSET;
return ((((10000 * reg) / 21445) * 1000) - 272674) / 1000;
}
/*
* Name: ddr3_tip_a38x_get_freq_config.
* Desc:
* Args:
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
struct hws_tip_freq_config_info
*freq_config_info)
{
if (a38x_bw_per_freq[freq] == 0xff)
return MV_NOT_SUPPORTED;
if (freq_config_info == NULL)
return MV_BAD_PARAM;
freq_config_info->bw_per_freq = a38x_bw_per_freq[freq];
freq_config_info->rate_per_freq = a38x_rate_per_freq[freq];
freq_config_info->is_supported = 1;
return MV_OK;
}
/*
* Name: ddr3_tip_a38x_pipe_enable.
* Desc:
* Args:
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_tip_a38x_pipe_enable(u8 dev_num, enum hws_access_type interface_access,
u32 if_id, int enable)
{
u32 data_value, pipe_enable_mask = 0;
if (enable == 0) {
pipe_enable_mask = 0;
} else {
if (interface_access == ACCESS_TYPE_MULTICAST)
pipe_enable_mask = pipe_multicast_mask;
else
pipe_enable_mask = (1 << interface_map[if_id].pipe);
}
CHECK_STATUS(ddr3_tip_reg_read
(dev_num, PIPE_ENABLE_ADDR, &data_value, MASK_ALL_BITS));
data_value = (data_value & (~0xff)) | pipe_enable_mask;
CHECK_STATUS(ddr3_tip_reg_write(dev_num, PIPE_ENABLE_ADDR, data_value));
return MV_OK;
}
/*
* Name: ddr3_tip_a38x_if_write.
* Desc:
* Args:
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
u32 if_id, u32 reg_addr, u32 data_value,
u32 mask)
{
u32 ui_data_read;
if (mask != MASK_ALL_BITS) {
CHECK_STATUS(ddr3_tip_a38x_if_read
(dev_num, ACCESS_TYPE_UNICAST, if_id, reg_addr,
&ui_data_read, MASK_ALL_BITS));
data_value = (ui_data_read & (~mask)) | (data_value & mask);
}
reg_write(reg_addr, data_value);
return MV_OK;
}
/*
* Name: ddr3_tip_a38x_if_read.
* Desc:
* Args:
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
u32 if_id, u32 reg_addr, u32 *data, u32 mask)
{
*data = reg_read(reg_addr) & mask;
return MV_OK;
}
/*
* Name: ddr3_tip_a38x_select_ddr_controller.
* Desc: Enable/Disable access to Marvell's server.
* Args: dev_num - device number
* enable - whether to enable or disable the server
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable)
{
u32 reg;
reg = reg_read(CS_ENABLE_REG);
if (enable)
reg |= (1 << 6);
else
reg &= ~(1 << 6);
reg_write(CS_ENABLE_REG, reg);
return MV_OK;
}
/*
* Name: ddr3_tip_init_a38x_silicon.
* Desc: init Training SW DB.
* Args:
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
static int ddr3_tip_init_a38x_silicon(u32 dev_num, u32 board_id)
{
struct hws_tip_config_func_db config_func;
enum hws_ddr_freq ddr_freq;
int status;
struct hws_topology_map *tm = ddr3_get_topology_map();
/* new read leveling version */
config_func.tip_dunit_read_func = ddr3_tip_a38x_if_read;
config_func.tip_dunit_write_func = ddr3_tip_a38x_if_write;
config_func.tip_dunit_mux_select_func =
ddr3_tip_a38x_select_ddr_controller;
config_func.tip_get_freq_config_info_func =
ddr3_tip_a38x_get_freq_config;
config_func.tip_set_freq_divider_func = ddr3_tip_a38x_set_divider;
config_func.tip_get_device_info_func = ddr3_tip_a38x_get_device_info;
config_func.tip_get_temperature = ddr3_ctrl_get_junc_temp;
ddr3_tip_init_config_func(dev_num, &config_func);
ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin);
status = ddr3_tip_a38x_get_init_freq(dev_num, &ddr_freq);
if (MV_OK != status) {
DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
("DDR3 silicon get target frequency - FAILED 0x%x\n",
status));
return status;
}
rl_version = 1;
mask_tune_func = (SET_LOW_FREQ_MASK_BIT |
LOAD_PATTERN_MASK_BIT |
SET_MEDIUM_FREQ_MASK_BIT | WRITE_LEVELING_MASK_BIT |
/* LOAD_PATTERN_2_MASK_BIT | */
WRITE_LEVELING_SUPP_MASK_BIT |
READ_LEVELING_MASK_BIT |
PBS_RX_MASK_BIT |
PBS_TX_MASK_BIT |
SET_TARGET_FREQ_MASK_BIT |
WRITE_LEVELING_TF_MASK_BIT |
WRITE_LEVELING_SUPP_TF_MASK_BIT |
READ_LEVELING_TF_MASK_BIT |
CENTRALIZATION_RX_MASK_BIT |
CENTRALIZATION_TX_MASK_BIT);
rl_mid_freq_wa = 1;
if ((ddr_freq == DDR_FREQ_333) || (ddr_freq == DDR_FREQ_400)) {
mask_tune_func = (WRITE_LEVELING_MASK_BIT |
LOAD_PATTERN_2_MASK_BIT |
WRITE_LEVELING_SUPP_MASK_BIT |
READ_LEVELING_MASK_BIT |
PBS_RX_MASK_BIT |
PBS_TX_MASK_BIT |
CENTRALIZATION_RX_MASK_BIT |
CENTRALIZATION_TX_MASK_BIT);
rl_mid_freq_wa = 0; /* WA not needed if 333/400 is TF */
}
/* Supplementary not supported for ECC modes */
if (1 == ddr3_if_ecc_enabled()) {
mask_tune_func &= ~WRITE_LEVELING_SUPP_TF_MASK_BIT;
mask_tune_func &= ~WRITE_LEVELING_SUPP_MASK_BIT;
mask_tune_func &= ~PBS_TX_MASK_BIT;
mask_tune_func &= ~PBS_RX_MASK_BIT;
}
if (ck_delay == -1)
ck_delay = 160;
if (ck_delay_16 == -1)
ck_delay_16 = 160;
ca_delay = 0;
delay_enable = 1;
calibration_update_control = 1;
init_freq = tm->interface_params[first_active_if].memory_freq;
ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq);
return MV_OK;
}
int ddr3_a38x_update_topology_map(u32 dev_num, struct hws_topology_map *tm)
{
u32 if_id = 0;
enum hws_ddr_freq freq;
ddr3_tip_a38x_get_init_freq(dev_num, &freq);
tm->interface_params[if_id].memory_freq = freq;
/*
* re-calc topology parameters according to topology updates
* (if needed)
*/
CHECK_STATUS(hws_ddr3_tip_load_topology_map(dev_num, tm));
return MV_OK;
}
int ddr3_tip_init_a38x(u32 dev_num, u32 board_id)
{
struct hws_topology_map *tm = ddr3_get_topology_map();
if (NULL == tm)
return MV_FAIL;
ddr3_a38x_update_topology_map(dev_num, tm);
ddr3_tip_init_a38x_silicon(dev_num, board_id);
return MV_OK;
}
int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq)
{
u32 reg;
/* Read sample at reset setting */
reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
switch (reg) {
case 0x0:
case 0x1:
*freq = DDR_FREQ_333;
break;
case 0x2:
case 0x3:
*freq = DDR_FREQ_400;
break;
case 0x4:
case 0xd:
*freq = DDR_FREQ_533;
break;
case 0x6:
*freq = DDR_FREQ_600;
break;
case 0x8:
case 0x11:
case 0x14:
*freq = DDR_FREQ_667;
break;
case 0xc:
case 0x15:
case 0x1b:
*freq = DDR_FREQ_800;
break;
case 0x10:
*freq = DDR_FREQ_933;
break;
case 0x12:
*freq = DDR_FREQ_900;
break;
case 0x13:
*freq = DDR_FREQ_900;
break;
default:
*freq = 0;
return MV_NOT_SUPPORTED;
}
return MV_OK;
}
int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq)
{
u32 reg;
/* Read sample at reset setting */
reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
switch (reg) {
case 0x0:
case 0x1:
/* Medium is same as TF to run PBS in this freq */
*freq = DDR_FREQ_333;
break;
case 0x2:
case 0x3:
/* Medium is same as TF to run PBS in this freq */
*freq = DDR_FREQ_400;
break;
case 0x4:
case 0xd:
*freq = DDR_FREQ_533;
break;
case 0x8:
case 0x11:
case 0x14:
*freq = DDR_FREQ_333;
break;
case 0xc:
case 0x15:
case 0x1b:
*freq = DDR_FREQ_400;
break;
case 0x6:
*freq = DDR_FREQ_300;
break;
case 0x12:
*freq = DDR_FREQ_360;
break;
case 0x13:
*freq = DDR_FREQ_400;
break;
default:
*freq = 0;
return MV_NOT_SUPPORTED;
}
return MV_OK;
}
u32 ddr3_tip_get_init_freq(void)
{
enum hws_ddr_freq freq;
ddr3_tip_a38x_get_init_freq(0, &freq);
return freq;
}
static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
enum hws_ddr_freq frequency)
{
u32 divider = 0;
u32 sar_val;
if (if_id != 0) {
DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
("A38x does not support interface 0x%x\n",
if_id));
return MV_BAD_PARAM;
}
/* get VCO freq index */
sar_val = (reg_read(REG_DEVICE_SAR1_ADDR) >>
RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
divider = a38x_vco_freq_per_sar[sar_val] / freq_val[frequency];
/* Set Sync mode */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x20220, 0x0,
0x1000));
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe42f4, 0x0,
0x200));
/* cpupll_clkdiv_reset_mask */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0x1f,
0xff));
/* cpupll_clkdiv_reload_smooth */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
(0x2 << 8), (0xff << 8)));
/* cpupll_clkdiv_relax_en */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
(0x2 << 24), (0xff << 24)));
/* write the divider */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4268,
(divider << 8), (0x3f << 8)));
/* set cpupll_clkdiv_reload_ratio */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264,
(1 << 8), (1 << 8)));
/* undet cpupll_clkdiv_reload_ratio */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
(1 << 8)));
/* clear cpupll_clkdiv_reload_force */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
(0xff << 8)));
/* clear cpupll_clkdiv_relax_en */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
(0xff << 24)));
/* clear cpupll_clkdiv_reset_mask */
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
0xff));
/* Dunit training clock + 1:1 mode */
if ((frequency == DDR_FREQ_LOW_FREQ) || (freq_val[frequency] <= 400)) {
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
(1 << 16), (1 << 16)));
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
(0 << 15), (1 << 15)));
} else {
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
0, (1 << 16)));
CHECK_STATUS(ddr3_tip_a38x_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
(1 << 15), (1 << 15)));
}
return MV_OK;
}
/*
* external read from memory
*/
int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
u32 num_of_bursts, u32 *data)
{
u32 burst_num;
for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
data[burst_num] = readl(reg_addr + 4 * burst_num);
return MV_OK;
}
/*
* external write to memory
*/
int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
u32 num_of_bursts, u32 *data) {
u32 burst_num;
for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
writel(data[burst_num], reg_addr + 4 * burst_num);
return MV_OK;
}
int ddr3_silicon_pre_init(void)
{
return ddr3_silicon_init();
}
int ddr3_post_run_alg(void)
{
return MV_OK;
}
int ddr3_silicon_post_init(void)
{
struct hws_topology_map *tm = ddr3_get_topology_map();
/* Set half bus width */
if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)) {
CHECK_STATUS(ddr3_tip_if_write
(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
REG_SDRAM_CONFIG_ADDR, 0x0, 0x8000));
}
return MV_OK;
}
int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr)
{
info_ptr->device_id = 0x6800;
info_ptr->ck_delay = ck_delay;
return MV_OK;
}
drivers/ddr/marvell/a38x/ddr3_a38x_topology.h 已删除 100644 → 0
浏览文件 @ 00a77677
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_A38X_TOPOLOGY_H
#define _DDR3_A38X_TOPOLOGY_H
#include "ddr_topology_def.h"
/* Bus mask variants */
#define BUS_MASK_32BIT 0xf
#define BUS_MASK_32BIT_ECC 0x1f
#define BUS_MASK_16BIT 0x3
#define BUS_MASK_16BIT_ECC 0x13
#define BUS_MASK_16BIT_ECC_PUP3 0xb
#define DYNAMIC_CS_SIZE_CONFIG
#define DISABLE_L2_FILTERING_DURING_DDR_TRAINING
#endif /* _DDR3_A38X_TOPOLOGY_H */
drivers/ddr/marvell/a38x/ddr3_a38x_training.c 已删除 100644 → 0
浏览文件 @ 00a77677
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "ddr3_init.h"
/*
* Name: ddr3_tip_init_silicon
* Desc: initiate silicon parameters
* Args:
* Notes:
* Returns: required value
*/
int ddr3_silicon_init(void)
{
int status;
static int init_done;
if (init_done == 1)
return MV_OK;
status = ddr3_tip_init_a38x(0, 0);
if (MV_OK != status) {
printf("DDR3 A38x silicon init - FAILED 0x%x\n", status);
return status;
}
init_done = 1;
return MV_OK;
}
drivers/ddr/marvell/a38x/ddr3_hws_hw_training.c 已删除 100644 → 0
浏览文件 @ 00a77677
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "ddr3_init.h"
#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1f
#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
#define REG_READ_DATA_READY_DELAYS_ADDR 0x153c
#define REG_READ_DATA_READY_DELAYS_MASK 0x1f
#define REG_READ_DATA_READY_DELAYS_OFFS 8
int ddr3_if_ecc_enabled(void)
{
struct hws_topology_map *tm = ddr3_get_topology_map();
if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
return 1;
else
return 0;
}
int ddr3_pre_algo_config(void)
{
struct hws_topology_map *tm = ddr3_get_topology_map();
/* Set Bus3 ECC training mode */
if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) {
/* Set Bus3 ECC MUX */
CHECK_STATUS(ddr3_tip_if_write
(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
REG_SDRAM_PINS_MUX, 0x100, 0x100));
}
/* Set regular ECC training mode (bus4 and bus 3) */
if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
(DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
/* Enable ECC Write MUX */
CHECK_STATUS(ddr3_tip_if_write
(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
TRAINING_SW_2_REG, 0x100, 0x100));
/* General ECC enable */
CHECK_STATUS(ddr3_tip_if_write
(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
REG_SDRAM_CONFIG_ADDR, 0x40000, 0x40000));
/* Disable Read Data ECC MUX */
CHECK_STATUS(ddr3_tip_if_write
(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
TRAINING_SW_2_REG, 0x0, 0x2));
}
return MV_OK;
}
int ddr3_post_algo_config(void)
{
struct hws_topology_map *tm = ddr3_get_topology_map();
int status;
status = ddr3_post_run_alg();
if (MV_OK != status) {
printf("DDR3 Post Run Alg - FAILED 0x%x\n", status);
return status;
}
/* Un_set ECC training mode */
if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
(DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
/* Disable ECC Write MUX */
CHECK_STATUS(ddr3_tip_if_write
(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
TRAINING_SW_2_REG, 0x0, 0x100));
/* General ECC and Bus3 ECC MUX remains enabled */
}
return MV_OK;
}
int ddr3_hws_hw_training(void)
{
enum hws_algo_type algo_mode = ALGO_TYPE_DYNAMIC;
int status;
struct init_cntr_param init_param;
status = ddr3_silicon_pre_init();
if (MV_OK != status) {
printf("DDR3 Pre silicon Config - FAILED 0x%x\n", status);
return status;
}
init_param.do_mrs_phy = 1;
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
init_param.is_ctrl64_bit = 0;
#else
init_param.is_ctrl64_bit = 1;
#endif
#if defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_38X) || \
defined(CONFIG_ARMADA_39X)
init_param.init_phy = 1;
#else
init_param.init_phy = 0;
#endif
init_param.msys_init = 1;
status = hws_ddr3_tip_init_controller(0, &init_param);
if (MV_OK != status) {
printf("DDR3 init controller - FAILED 0x%x\n", status);
return status;
}
status = ddr3_silicon_post_init();
if (MV_OK != status) {
printf("DDR3 Post Init - FAILED 0x%x\n", status);
return status;
}
status = ddr3_pre_algo_config();
if (MV_OK != status) {
printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status);
return status;
}
/* run algorithm in order to configure the PHY */
status = hws_ddr3_tip_run_alg(0, algo_mode);
if (MV_OK != status) {
printf("DDR3 run algorithm - FAILED 0x%x\n", status);
return status;
}
status = ddr3_post_algo_config();
if (MV_OK != status) {
printf("DDR3 Post Algo Config - FAILED 0x%x\n", status);
return status;
}
return MV_OK;
}
drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h 已删除 100644 → 0
浏览文件 @ 00a77677
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_HWS_HW_TRAINING_H
#define _DDR3_HWS_HW_TRAINING_H
/* struct used for DLB configuration array */
struct dlb_config {
u32 reg_addr;
u32 reg_data;
};
/* Topology update structure */
struct topology_update_info {
int update_ecc;
u8 ecc;
int update_width;
u8 width;
int update_ecc_pup3_mode;
u8 ecc_pup_mode_offset;
};
/* Topology update defines */
#define TOPOLOGY_UPDATE_WIDTH_16BIT 1
#define TOPOLOGY_UPDATE_WIDTH_32BIT 0
#define TOPOLOGY_UPDATE_WIDTH_32BIT_MASK 0xf
#define TOPOLOGY_UPDATE_WIDTH_16BIT_MASK 0x3
#define TOPOLOGY_UPDATE_ECC_ON 1
#define TOPOLOGY_UPDATE_ECC_OFF 0
#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP4 4
#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP3 3
/*
* 1. L2 filter should be set at binary header to 0xd000000,
* to avoid conflict with internal register IO.
* 2. U-Boot modifies internal registers base to 0xf100000,
* and than should update L2 filter accordingly to 0xf000000 (3.75 GB)
*/
/* temporary limit l2 filter to 3GiB (LSP issue) */
#define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xc0000000
#define ADDRESS_FILTERING_END_REGISTER 0x8c04
#define SUB_VERSION 0
#endif /* _DDR3_HWS_HW_TRAINING_H */
drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h 已删除 100644 → 0
浏览文件 @ 00a77677
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_HWS_HW_TRAINING_DEF_H
#define _DDR3_HWS_HW_TRAINING_DEF_H
#define SAR_DDR3_FREQ_MASK 0xfe00000
#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | \
((fab & 0xf) << 24))
#define MAX_CS 4
#define MIN_DIMM_ADDR 0x50
#define FAR_END_DIMM_ADDR 0x50
#define MAX_DIMM_ADDR 0x60
#define SDRAM_CS_SIZE 0xfffffff
#define SDRAM_CS_BASE 0x0
#define SDRAM_DIMM_SIZE 0x80000000
#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
#define CPU_MRVL_ID_OFFSET 0x10
#define SAR1_CPU_CORE_MASK 0x38000000
#define SAR1_CPU_CORE_OFFSET 27
#define NEW_FABRIC_TWSI_ADDR 0x4e
#ifdef DB_784MP_GP
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4e
#else
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4f
#endif
#define MV_MAX_DDR3_STATIC_SIZE 50
#define MV_DDR3_MODES_NUMBER 30
#define RESUME_RL_PATTERNS_ADDR 0xfe0000
#define RESUME_RL_PATTERNS_SIZE 0x100
#define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + \
RESUME_RL_PATTERNS_SIZE)
#define RESUME_TRAINING_VALUES_MAX 0xcd0
#define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000)
#define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000)
#define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4)
#define SUSPEND_MAGIC_WORD 0xdeadb002
#define REGISTER_LIST_END 0xffffffff
/* MISC */
#define INTER_REGS_BASE SOC_REGS_PHY_BASE
/* DDR */
#define REG_SDRAM_CONFIG_ADDR 0x1400
#define REG_SDRAM_CONFIG_MASK 0x9fffffff
#define REG_SDRAM_CONFIG_RFRS_MASK 0x3fff
#define REG_SDRAM_CONFIG_WIDTH_OFFS 15
#define REG_SDRAM_CONFIG_REGDIMM_OFFS 17
#define REG_SDRAM_CONFIG_ECC_OFFS 18
#define REG_SDRAM_CONFIG_IERR_OFFS 19
#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28
#define REG_SDRAM_CONFIG_RSTRD_OFFS 30
#define REG_SDRAM_PINS_MUX 0x19d4
#define REG_DUNIT_CTRL_LOW_ADDR 0x1404
#define REG_DUNIT_CTRL_LOW_2T_OFFS 3
#define REG_DUNIT_CTRL_LOW_2T_MASK 0x3
#define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14
#define REG_SDRAM_TIMING_LOW_ADDR 0x1408
#define REG_SDRAM_TIMING_HIGH_ADDR 0x140c
#define REG_SDRAM_TIMING_H_R2R_OFFS 7
#define REG_SDRAM_TIMING_H_R2R_MASK 0x3
#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9
#define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3
#define REG_SDRAM_TIMING_H_W2W_OFFS 11
#define REG_SDRAM_TIMING_H_W2W_MASK 0x1f
#define REG_SDRAM_TIMING_H_R2R_H_OFFS 19
#define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7
#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22
#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7
#define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410
#define REG_SDRAM_ADDRESS_SIZE_OFFS 2
#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18
#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4
#define REG_SDRAM_OPEN_PAGES_ADDR 0x1414
#define REG_SDRAM_OPERATION_CS_OFFS 8
#define REG_SDRAM_OPERATION_ADDR 0x1418
#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24
#define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20
#define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xf
#define REG_SDRAM_OPERATION_CWA_RC_OFFS 16
#define REG_SDRAM_OPERATION_CWA_RC_MASK 0xf
#define REG_SDRAM_OPERATION_CMD_MR0 0xf03
#define REG_SDRAM_OPERATION_CMD_MR1 0xf04
#define REG_SDRAM_OPERATION_CMD_MR2 0xf08
#define REG_SDRAM_OPERATION_CMD_MR3 0xf09
#define REG_SDRAM_OPERATION_CMD_RFRS 0xf02
#define REG_SDRAM_OPERATION_CMD_CWA 0xf0e
#define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xf
#define REG_SDRAM_OPERATION_CMD_MASK 0xf
#define REG_SDRAM_OPERATION_CS_OFFS 8
#define REG_OUDDR3_TIMING_ADDR 0x142c
#define REG_SDRAM_MODE_ADDR 0x141c
#define REG_SDRAM_EXT_MODE_ADDR 0x1420
#define REG_DDR_CONT_HIGH_ADDR 0x1424
#define REG_ODT_TIME_LOW_ADDR 0x1428
#define REG_ODT_ON_CTL_RD_OFFS 12
#define REG_ODT_OFF_CTL_RD_OFFS 16
#define REG_SDRAM_ERROR_ADDR 0x1454
#define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474
#define REG_ODT_TIME_HIGH_ADDR 0x147c
#define REG_SDRAM_INIT_CTRL_ADDR 0x1480
#define REG_SDRAM_INIT_CTRL_OFFS 0
#define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2
#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3
#define REG_SDRAM_INIT_RESET_MASK_OFFS 1
#define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494
#define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498
#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0
#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3
#define REG_DUNIT_ODT_CTRL_ADDR 0x149c
#define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8
#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9
#define REG_DRAM_FIFO_CTRL_ADDR 0x14a0
#define REG_DRAM_AXI_CTRL_ADDR 0x14a8
#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0
#define REG_METAL_MASK_ADDR 0x14b0
#define REG_METAL_MASK_MASK 0xdfffffff
#define REG_METAL_MASK_RETRY_OFFS 0
#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14c0
#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14c4
#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8
#define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14cc
#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8
#define REG_CS_SIZE_SCRATCH_ADDR 0x1504
#define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520
#define REG_DDR_IO_ADDR 0x1524
#define REG_DDR_IO_CLK_RATIO_OFFS 15
#define REG_DFS_ADDR 0x1528
#define REG_DFS_DLLNEXTSTATE_OFFS 0
#define REG_DFS_BLOCK_OFFS 1
#define REG_DFS_SR_OFFS 2
#define REG_DFS_ATSR_OFFS 3
#define REG_DFS_RECONF_OFFS 4
#define REG_DFS_CL_NEXT_STATE_OFFS 8
#define REG_DFS_CL_NEXT_STATE_MASK 0xf
#define REG_DFS_CWL_NEXT_STATE_OFFS 12
#define REG_DFS_CWL_NEXT_STATE_MASK 0x7
#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1f
#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
#define REG_READ_DATA_READY_DELAYS_ADDR 0x153c
#define REG_READ_DATA_READY_DELAYS_MASK 0x1f
#define REG_READ_DATA_READY_DELAYS_OFFS 8
#define START_BURST_IN_ADDR 1
#define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488
#define REG_DRAM_TRAINING_ADDR 0x15b0
#define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0
#define REG_DRAM_TRAINING_PATTERNS_OFFS 4
#define REG_DRAM_TRAINING_MED_FREQ_OFFS 2
#define REG_DRAM_TRAINING_WL_OFFS 3
#define REG_DRAM_TRAINING_RL_OFFS 6
#define REG_DRAM_TRAINING_DQS_RX_OFFS 15
#define REG_DRAM_TRAINING_DQS_TX_OFFS 16
#define REG_DRAM_TRAINING_CS_OFFS 20
#define REG_DRAM_TRAINING_RETEST_OFFS 24
#define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27
#define REG_DRAM_TRAINING_DFS_REQ_OFFS 29
#define REG_DRAM_TRAINING_ERROR_OFFS 30
#define REG_DRAM_TRAINING_AUTO_OFFS 31
#define REG_DRAM_TRAINING_RETEST_PAR 0x3
#define REG_DRAM_TRAINING_RETEST_MASK 0xf8ffffff
#define REG_DRAM_TRAINING_CS_MASK 0xff0fffff
#define REG_DRAM_TRAINING_PATTERNS_MASK 0xff0f0000
#define REG_DRAM_TRAINING_1_ADDR 0x15b4
#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16
#define REG_DRAM_TRAINING_2_ADDR 0x15b8
#define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17
#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4
#define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3
#define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2
#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1
#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0
#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15bc
#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3
#define REG_TRAINING_DEBUG_2_ADDR 0x15c4
#define REG_TRAINING_DEBUG_2_OFFS 16
#define REG_TRAINING_DEBUG_2_MASK 0x3
#define REG_TRAINING_DEBUG_3_ADDR 0x15c8
#define REG_TRAINING_DEBUG_3_OFFS 3
#define REG_TRAINING_DEBUG_3_MASK 0x7
#define MR_CS_ADDR_OFFS 4
#define REG_DDR3_MR0_ADDR 0x15d0
#define REG_DDR3_MR0_CS_ADDR 0x1870
#define REG_DDR3_MR0_CL_MASK 0x74
#define REG_DDR3_MR0_CL_OFFS 2
#define REG_DDR3_MR0_CL_HIGH_OFFS 3
#define CL_MASK 0xf
#define REG_DDR3_MR1_ADDR 0x15d4
#define REG_DDR3_MR1_CS_ADDR 0x1874
#define REG_DDR3_MR1_RTT_MASK 0xfffffdbb
#define REG_DDR3_MR1_DLL_ENA_OFFS 0
#define REG_DDR3_MR1_RTT_DISABLED 0x0
#define REG_DDR3_MR1_RTT_RZQ2 0x40
#define REG_DDR3_MR1_RTT_RZQ4 0x2
#define REG_DDR3_MR1_RTT_RZQ6 0x42
#define REG_DDR3_MR1_RTT_RZQ8 0x202
#define REG_DDR3_MR1_RTT_RZQ12 0x4
/* WL-disabled, OB-enabled */
#define REG_DDR3_MR1_OUTBUF_WL_MASK 0xffffef7f
/* Output Buffer Disabled */
#define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12
#define REG_DDR3_MR1_WL_ENA_OFFS 7
#define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */
#define REG_DDR3_MR1_ODT_MASK 0xfffffdbb
#define REG_DDR3_MR2_ADDR 0x15d8
#define REG_DDR3_MR2_CS_ADDR 0x1878
#define REG_DDR3_MR2_CWL_OFFS 3
#define REG_DDR3_MR2_CWL_MASK 0x7
#define REG_DDR3_MR2_ODT_MASK 0xfffff9ff
#define REG_DDR3_MR3_ADDR 0x15dc
#define REG_DDR3_MR3_CS_ADDR 0x187c
#define REG_DDR3_RANK_CTRL_ADDR 0x15e0
#define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xf
#define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4
#define REG_ZQC_CONF_ADDR 0x15e4
#define REG_DRAM_PHY_CONFIG_ADDR 0x15ec
#define REG_DRAM_PHY_CONFIG_MASK 0x3fffffff
#define REG_ODPG_CNTRL_ADDR 0x1600
#define REG_ODPG_CNTRL_OFFS 21
#define REG_PHY_LOCK_MASK_ADDR 0x1670
#define REG_PHY_LOCK_MASK_MASK 0xfffff000
#define REG_PHY_LOCK_STATUS_ADDR 0x1674
#define REG_PHY_LOCK_STATUS_LOCK_OFFS 9
#define REG_PHY_LOCK_STATUS_LOCK_MASK 0xfff
#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7ff
#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16a0
#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xc0000000
#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000
#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000
#define REG_PHY_BC_OFFS 27
#define REG_PHY_CNTRL_OFFS 26
#define REG_PHY_CS_OFFS 16
#define REG_PHY_DQS_REF_DLY_OFFS 10
#define REG_PHY_PHASE_OFFS 8
#define REG_PHY_PUP_OFFS 22
#define REG_TRAINING_WL_ADDR 0x16ac
#define REG_TRAINING_WL_CS_MASK 0xfffffffc
#define REG_TRAINING_WL_UPD_OFFS 2
#define REG_TRAINING_WL_CS_DONE_OFFS 3
#define REG_TRAINING_WL_RATIO_MASK 0xffffff0f
#define REG_TRAINING_WL_1TO1 0x50
#define REG_TRAINING_WL_2TO1 0x10
#define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000
#define REG_TRAINING_WL_RESULTS_MASK 0x000001ff
#define REG_TRAINING_WL_RESULTS_OFFS 20
#define REG_REGISTERED_DRAM_CTRL_ADDR 0x16d0
#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15
#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3f
/* DLB */
#define REG_STATIC_DRAM_DLB_CONTROL 0x1700
#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704
#define DLB_AGING_REGISTER 0x1708
#define DLB_EVICTION_CONTROL_REG 0x170c
#define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710
#define DLB_USER_COMMAND_REG 0x1714
#define DLB_BUS_WEIGHTS_DIFF_CS 0x1770
#define DLB_BUS_WEIGHTS_DIFF_BG 0x1774
#define DLB_BUS_WEIGHTS_SAME_BG 0x1778
#define DLB_BUS_WEIGHTS_RD_WR 0x177c
#define DLB_BUS_WEIGHTS_ATTR_SYS_PRIO 0x1780
#define DLB_MAIN_QUEUE_MAP 0x1784
#define DLB_LINE_SPLIT 0x1788
#define DLB_ENABLE 0x1
#define DLB_WRITE_COALESING (0x1 << 2)
#define DLB_AXI_PREFETCH_EN (0x1 << 3)
#define DLB_MBUS_PREFETCH_EN (0x1 << 4)
#define PREFETCH_N_LN_SZ_TR (0x1 << 6)
#define DLB_INTERJECTION_ENABLE (0x1 << 3)
/* CPU */
#define REG_BOOTROM_ROUTINE_ADDR 0x182d0
#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12
#define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488
#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16
#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200ff
#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488
#define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700
#define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704
#define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708
#define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870c
#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xffffc0ff
#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8
#define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710
#define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718
#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8
#define REG_CPU_PLL_CTRL_0_ADDR 0x1871c
#define REG_CPU_PLL_STATUS_0_ADDR 0x18724
#define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740
#define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744
#define REG_DDRPHY_APLL_CTRL_ADDR 0x18780
#define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784
#define REG_SFABRIC_CLK_CTRL_ADDR 0x20858
#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8
/* DRAM Windows */
#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
#define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184
#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
/* SRAM */
#define REG_CDI_CONFIG_ADDR 0x20220
#define REG_SRAM_WINDOW_0_ADDR 0x20240
#define REG_SRAM_WINDOW_0_ENA_OFFS 0
#define REG_SRAM_WINDOW_1_ADDR 0x20244
#define REG_SRAM_L2_ENA_ADDR 0x8500
#define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87bc
/* Timers */
#define REG_TIMERS_CTRL_ADDR 0x20300
#define REG_TIMERS_EVENTS_ADDR 0x20304
#define REG_TIMER0_VALUE_ADDR 0x20314
#define REG_TIMER1_VALUE_ADDR 0x2031c
#define REG_TIMER0_ENABLE_MASK 0x1
#define MV_BOARD_REFCLK_25MHZ 25000000
#define CNTMR_RELOAD_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x10 + (tmr * 8))
#define CNTMR_VAL_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x14 + (tmr * 8))
#define CNTMR_CTRL_REG(tmr) (REG_TIMERS_CTRL_ADDR)
#define CTCR_ARM_TIMER_EN_OFFS(timer) (timer * 2)
#define CTCR_ARM_TIMER_EN_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
#define CTCR_ARM_TIMER_EN(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
#define CTCR_ARM_TIMER_AUTO_OFFS(timer) (1 + (timer * 2))
#define CTCR_ARM_TIMER_AUTO_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
#define CTCR_ARM_TIMER_AUTO_EN(timer) (1 << CTCR_ARM_TIMER_AUTO_OFFS(timer))
/* PMU */
#define REG_PMU_I_F_CTRL_ADDR 0x1c090
#define REG_PMU_DUNIT_BLK_OFFS 16
#define REG_PMU_DUNIT_RFRS_OFFS 20
#define REG_PMU_DUNIT_ACK_OFFS 24
/* MBUS */
#define MBUS_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x420)
#define FABRIC_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x424)
#define MBUS_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x428)
#define FABRIC_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x42c)
#define REG_PM_STAT_MASK_ADDR 0x2210c
#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16
#define REG_PM_EVENT_STAT_MASK_ADDR 0x22120
#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17
#define REG_PM_CTRL_CONFIG_ADDR 0x22104
#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18
#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218c4
#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18
/* Controller revision info */
#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
#define PCCRIR_REVID_OFFS 0 /* Revision ID */
#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
/* Power Management Clock Gating Control Register */
#define POWER_MNG_CTRL_REG 0x18220
#define PMC_PEXSTOPCLOCK_OFFS(p) ((p) < 8 ? (5 + (p)) : (18 + (p)))
#define PMC_PEXSTOPCLOCK_MASK(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p))
#define PMC_PEXSTOPCLOCK_EN(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p))
#define PMC_PEXSTOPCLOCK_STOP(p) (0 << PMC_PEXSTOPCLOCK_OFFS(p))
/* TWSI */
#define TWSI_DATA_ADDR_MASK 0x7
#define TWSI_DATA_ADDR_OFFS 1
/* General */
#define MAX_CS 4
/* Frequencies */
#define FAB_OPT 21
#define CLK_CPU 12
#define CLK_VCO (2 * CLK_CPU)
#define CLK_DDR 12
/* CPU Frequencies: */
#define CLK_CPU_1000 0
#define CLK_CPU_1066 1
#define CLK_CPU_1200 2
#define CLK_CPU_1333 3
#define CLK_CPU_1500 4
#define CLK_CPU_1666 5
#define CLK_CPU_1800 6
#define CLK_CPU_2000 7
#define CLK_CPU_600 8
#define CLK_CPU_667 9
#define CLK_CPU_800 0xa
/* Extra Cpu Frequencies: */
#define CLK_CPU_1600 11
#define CLK_CPU_2133 12
#define CLK_CPU_2200 13
#define CLK_CPU_2400 14
#endif /* _DDR3_HWS_HW_TRAINING_DEF_H */
drivers/ddr/marvell/a38x/ddr3_hws_sil_training.h 已删除 100644 → 0
浏览文件 @ 00a77677
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_HWS_SIL_TRAINING_H
#define _DDR3_HWS_SIL_TRAINING_H
#include "ddr3_training_ip.h"
#include "ddr3_training_ip_prv_if.h"
int ddr3_silicon_pre_config(void);
int ddr3_silicon_init(void);
int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
#endif /* _DDR3_HWS_SIL_TRAINING_H */
drivers/ddr/marvell/a38x/ddr3_init.h
浏览文件 @ 2b4ffbf6
......@@ -6,12 +6,12 @@
#ifndef _DDR3_INIT_H
#define _DDR3_INIT_H
#if defined(CONFIG_ARMADA_38X)
#include "ddr3_a38x.h"
#include "ddr3_a38x_topology.h"
#include "ddr_ml_wrapper.h"
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
#include "mv_ddr_plat.h"
#endif
#include "ddr3_hws_hw_training.h"
#include "ddr3_hws_sil_training.h"
#include "seq_exec.h"
#include "ddr3_logging_def.h"
#include "ddr3_training_hw_algo.h"
#include "ddr3_training_ip.h"
......@@ -20,119 +20,9 @@
#include "ddr3_training_ip_flow.h"
#include "ddr3_training_ip_pbs.h"
#include "ddr3_training_ip_prv_if.h"
#include "ddr3_training_ip_static.h"
#include "ddr3_training_leveling.h"
#include "xor.h"
/*
* MV_DEBUG_INIT need to be defines, otherwise the output of the
* DDR2 training code is not complete and misleading
*/
#define MV_DEBUG_INIT
#ifdef MV_DEBUG_INIT
#define DEBUG_INIT_S(s) puts(s)
#define DEBUG_INIT_D(d, l) printf("%x", d)
#define DEBUG_INIT_D_10(d, l) printf("%d", d)
#else
#define DEBUG_INIT_S(s)
#define DEBUG_INIT_D(d, l)
#define DEBUG_INIT_D_10(d, l)
#endif
#ifdef MV_DEBUG_INIT_FULL
#define DEBUG_INIT_FULL_S(s) puts(s)
#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
#define DEBUG_WR_REG(reg, val) \
{ DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
#define DEBUG_RD_REG(reg, val) \
{ DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
#else
#define DEBUG_INIT_FULL_S(s)
#define DEBUG_INIT_FULL_D(d, l)
#define DEBUG_INIT_FULL_D_10(d, l)
#define DEBUG_WR_REG(reg, val)
#define DEBUG_RD_REG(reg, val)
#endif
#define DEBUG_INIT_FULL_C(s, d, l) \
{ DEBUG_INIT_FULL_S(s); \
DEBUG_INIT_FULL_D(d, l); \
DEBUG_INIT_FULL_S("\n"); }
#define DEBUG_INIT_C(s, d, l) \
{ DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
/*
* Debug (Enable/Disable modules) and Error report
*/
#ifdef BASIC_DEBUG
#define MV_DEBUG_WL
#define MV_DEBUG_RL
#define MV_DEBUG_DQS_RESULTS
#endif
#ifdef FULL_DEBUG
#define MV_DEBUG_WL
#define MV_DEBUG_RL
#define MV_DEBUG_DQS
#define MV_DEBUG_PBS
#define MV_DEBUG_DFS
#define MV_DEBUG_MAIN_FULL
#define MV_DEBUG_DFS_FULL
#define MV_DEBUG_DQS_FULL
#define MV_DEBUG_RL_FULL
#define MV_DEBUG_WL_FULL
#endif
#if defined(CONFIG_ARMADA_38X)
#include "ddr3_a38x.h"
#include "ddr3_a38x_topology.h"
#endif
/* The following is a list of Marvell status */
#define MV_ERROR (-1)
#define MV_OK (0x00) /* Operation succeeded */
#define MV_FAIL (0x01) /* Operation failed */
#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
#define MV_BAD_PTR (0x05) /* Illegal pointer value */
#define MV_BAD_SIZE (0x06) /* Illegal size */
#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
#define MV_SET_ERROR (0x08) /* Set operation failed */
#define MV_GET_ERROR (0x09) /* Get operation failed */
#define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
#define MV_NOT_FOUND (0x0b) /* Item not found */
#define MV_NO_MORE (0x0c) /* No more items found */
#define MV_NO_SUCH (0x0d) /* No such item */
#define MV_TIMEOUT (0x0e) /* Time Out */
#define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
#define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
#define MV_HW_ERROR (0x17) /* Hardware error */
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
#define MV_NOT_READY (0x1a) /* The other side is not ready yet */
#define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
#define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
#define MV_NOT_STARTED (0x1d) /* Not started yet */
#define MV_BUSY (0x1e) /* Item is busy. */
#define MV_TERMINATE (0x1f) /* Item terminates it's work. */
#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
#define MV_WRITE_PROTECT (0x22) /* Write protected */
#define MV_INVALID (int)(-1)
/* For checking function return values */
#define CHECK_STATUS(orig_func) \
{ \
......@@ -142,6 +32,14 @@
return status; \
}
#define GET_MAX_VALUE(x, y) \
((x) > (y)) ? (x) : (y)
#define SUB_VERSION 0
/* max number of devices supported by driver */
#define MAX_DEVICE_NUM 1
enum log_level {
MV_LOG_LEVEL_0,
MV_LOG_LEVEL_1,
......@@ -150,28 +48,27 @@ enum log_level {
};
/* Globals */
extern u8 debug_training;
extern u8 debug_training, debug_calibration, debug_ddr4_centralization,
debug_tap_tuning, debug_dm_tuning;
extern u8 is_reg_dump;
extern u8 generic_init_controller;
extern u32 freq_val[];
/* list of allowed frequency listed in order of enum hws_ddr_freq */
extern u32 freq_val[DDR_FREQ_LAST];
extern u32 is_pll_old;
extern struct cl_val_per_freq cas_latency_table[];
extern struct pattern_info pattern_table[];
extern struct cl_val_per_freq cas_write_latency_table[];
extern u8 debug_training;
extern u8 debug_centralization, debug_training_ip, debug_training_bist,
debug_pbs, debug_training_static, debug_leveling;
extern u32 pipe_multicast_mask;
extern struct hws_tip_config_func_db config_func_info[];
extern u8 cs_mask_reg[];
extern u8 twr_mask_table[];
extern u8 cl_mask_table[];
extern u8 cwl_mask_table[];
extern u16 rfc_table[];
extern u32 speed_bin_table_t_rc[];
extern u32 speed_bin_table_t_rcd_t_rp[];
extern u32 ck_delay, ck_delay_16;
extern u32 vref_init_val;
extern u32 g_zpri_data;
extern u32 g_znri_data;
extern u32 g_zpri_ctrl;
......@@ -181,39 +78,28 @@ extern u32 g_znodt_data;
extern u32 g_zpodt_ctrl;
extern u32 g_znodt_ctrl;
extern u32 g_dic;
extern u32 g_odt_config_2cs;
extern u32 g_odt_config_1cs;
extern u32 g_odt_config;
extern u32 g_rtt_nom;
extern u32 g_rtt_wr;
extern u32 g_rtt_park;
extern u8 debug_training_access;
extern u8 debug_training_a38x;
extern u32 first_active_if;
extern enum hws_ddr_freq init_freq;
extern u32 delay_enable, ck_delay, ck_delay_16, ca_delay;
extern u32 delay_enable, ck_delay, ca_delay;
extern u32 mask_tune_func;
extern u32 rl_version;
extern int rl_mid_freq_wa;
extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
extern enum hws_ddr_freq medium_freq;
extern u32 ck_delay, ck_delay_16;
extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
extern u32 first_active_if;
extern u32 mask_tune_func;
extern u32 freq_val[];
extern enum hws_ddr_freq init_freq;
extern enum hws_ddr_freq low_freq;
extern enum hws_ddr_freq medium_freq;
extern u8 generic_init_controller;
extern enum auto_tune_stage training_stage;
extern u32 is_pll_before_init;
extern u32 is_adll_calib_before_init;
extern u32 is_dfs_in_init;
extern int wl_debug_delay;
extern u32 silicon_delay[HWS_MAX_DEVICE_NUM];
extern u32 p_finger;
extern u32 n_finger;
extern u32 freq_val[DDR_FREQ_LIMIT];
extern u32 silicon_delay[MAX_DEVICE_NUM];
extern u32 start_pattern, end_pattern;
extern u32 phy_reg0_val;
extern u32 phy_reg1_val;
......@@ -221,172 +107,93 @@ extern u32 phy_reg2_val;
extern u32 phy_reg3_val;
extern enum hws_pattern sweep_pattern;
extern enum hws_pattern pbs_pattern;
extern u8 is_rzq6;
extern u32 znri_data_phy_val;
extern u32 zpri_data_phy_val;
extern u32 znri_ctrl_phy_val;
extern u32 zpri_ctrl_phy_val;
extern u8 debug_training_access;
extern u32 g_znri_data;
extern u32 g_zpri_data;
extern u32 g_znri_ctrl;
extern u32 g_zpri_ctrl;
extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
n_finger_end, p_finger_step, n_finger_step;
extern u32 mode2_t;
extern u32 mode_2t;
extern u32 xsb_validate_type;
extern u32 xsb_validation_base_address;
extern u32 odt_additional;
extern u32 debug_mode;
extern u32 delay_enable;
extern u32 ca_delay;
extern u32 debug_dunit;
extern u32 clamp_tbl[];
extern u32 freq_mask[HWS_MAX_DEVICE_NUM][DDR_FREQ_LIMIT];
extern u32 start_pattern, end_pattern;
extern u32 freq_mask[MAX_DEVICE_NUM][DDR_FREQ_LAST];
extern u32 maxt_poll_tries;
extern u32 is_bist_reset_bit;
extern u8 debug_training_bist;
extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
extern u32 debug_mode;
extern u32 effective_cs;
extern int ddr3_tip_centr_skip_min_win_check;
extern u32 *dq_map_table;
extern enum auto_tune_stage training_stage;
extern u8 debug_centralization;
extern u32 delay_enable;
extern u32 start_pattern, end_pattern;
extern u32 freq_val[DDR_FREQ_LIMIT];
extern u8 debug_training_hw_alg;
extern enum auto_tune_stage training_stage;
extern u8 debug_training_ip;
extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
extern enum auto_tune_stage training_stage;
extern u32 effective_cs;
extern u8 debug_leveling;
extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
extern enum auto_tune_stage training_stage;
extern u32 rl_version;
extern struct cl_val_per_freq cas_latency_table[];
extern u32 start_xsb_offset;
extern u32 debug_mode;
extern u32 odt_config;
extern u32 effective_cs;
extern u32 phy_reg1_val;
extern u8 debug_pbs;
extern u32 effective_cs;
extern u16 mask_results_dq_reg_map[];
extern enum hws_ddr_freq medium_freq;
extern u32 freq_val[];
extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
extern enum auto_tune_stage training_stage;
extern u32 debug_mode;
extern u32 *dq_map_table;
extern u32 vref;
extern struct cl_val_per_freq cas_latency_table[];
extern u32 target_freq;
extern struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
extern u32 clamp_tbl[];
extern u32 init_freq;
/* list of allowed frequency listed in order of enum hws_ddr_freq */
extern u32 freq_val[];
extern u8 debug_training_static;
extern u32 first_active_if;
extern u32 dfs_low_freq;
extern u32 mem_size[];
extern u32 nominal_avs;
extern u32 extension_avs;
/* Prototypes */
int ddr3_init(void);
int ddr3_tip_enable_init_sequence(u32 dev_num);
int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
int ddr3_hws_hw_training(void);
int ddr3_silicon_pre_init(void);
int ddr3_hws_hw_training(enum hws_algo_type algo_mode);
int mv_ddr_early_init(void);
int mv_ddr_early_init2(void);
int ddr3_silicon_post_init(void);
int ddr3_post_run_alg(void);
int ddr3_if_ecc_enabled(void);
void ddr3_new_tip_ecc_scrub(void);
void ddr3_print_version(void);
void ddr3_new_tip_dlb_config(void);
struct hws_topology_map *ddr3_get_topology_map(void);
void mv_ddr_ver_print(void);
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void);
int ddr3_if_ecc_enabled(void);
int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
struct hws_tip_freq_config_info
*freq_config_info);
int ddr3_a38x_update_topology_map(u32 dev_num,
struct hws_topology_map *topology_map);
int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq);
int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq);
int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
u32 if_id, u32 reg_addr, u32 *data, u32 mask);
int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
u32 if_id, u32 reg_addr, u32 data, u32 mask);
int ddr3_tip_a38x_get_device_info(u8 dev_num,
struct ddr3_device_info *info_ptr);
int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
int reg_addr, u32 mask);
int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
int ddr3_tip_restore_dunit_regs(u32 dev_num);
void print_topology(struct hws_topology_map *topology_db);
void print_topology(struct mv_ddr_topology_map *tm);
u32 mv_board_id_get(void);
int ddr3_load_topology_map(void);
int ddr3_tip_init_specific_reg_config(u32 dev_num,
struct reg_data *reg_config_arr);
u32 ddr3_tip_get_init_freq(void);
void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
void mv_ddr_user_log_level_set(enum ddr_lib_debug_block block);
int ddr3_tip_tune_training_params(u32 dev_num,
struct tune_train_params *params);
void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
u32 ddr3_get_device_width(u32 cs);
u32 mv_board_id_index_get(u32 board_id);
u32 mv_board_id_get(void);
u32 ddr3_get_bus_width(void);
void ddr3_set_log_level(u32 n_log_level);
int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size);
int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num);
int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
struct trip_delay_element *table_ptr,
int is_wl, u32 *round_trip_delay_arr);
u32 hws_ddr3_tip_max_cs_get(void);
/*
* Accessor functions for the registers
*/
static inline void reg_write(u32 addr, u32 val)
{
writel(val, INTER_REGS_BASE + addr);
}
static inline u32 reg_read(u32 addr)
{
return readl(INTER_REGS_BASE + addr);
}
static inline void reg_bit_set(u32 addr, u32 mask)
{
setbits_le32(INTER_REGS_BASE + addr, mask);
}
static inline void reg_bit_clr(u32 addr, u32 mask)
{
clrbits_le32(INTER_REGS_BASE + addr, mask);
}
u32 mv_ddr_init_freq_get(void);
void mv_ddr_mc_config(void);
int mv_ddr_mc_init(void);
void mv_ddr_set_calib_controller(void);
#endif /* _DDR3_INIT_H */
drivers/ddr/marvell/a38x/ddr3_logging_def.h
浏览文件 @ 2b4ffbf6
......@@ -73,10 +73,14 @@
#endif
#endif
/* Logging defines */
#define DEBUG_LEVEL_TRACE 1
#define DEBUG_LEVEL_INFO 2
#define DEBUG_LEVEL_ERROR 3
enum mv_ddr_debug_level {
DEBUG_LEVEL_TRACE = 1,
DEBUG_LEVEL_INFO = 2,
DEBUG_LEVEL_ERROR = 3,
DEBUG_LEVEL_LAST
};
enum ddr_lib_debug_block {
DEBUG_BLOCK_STATIC,
......
drivers/ddr/marvell/a38x/ddr3_patterns_64bit.h
浏览文件 @ 2b4ffbf6
......@@ -6,6 +6,7 @@
#ifndef __DDR3_PATTERNS_64_H
#define __DDR3_PATTERNS_64_H
#define FAB_OPT 21
/*
* Patterns Declerations
*/
......
drivers/ddr/marvell/a38x/ddr3_topology_def.h
浏览文件 @ 2b4ffbf6
......@@ -6,8 +6,9 @@
#ifndef _DDR3_TOPOLOGY_DEF_H
#define _DDR3_TOPOLOGY_DEF_H
/* TOPOLOGY */
#define DEV_NUM_0 0
/* TOPOLOGY */
enum hws_speed_bin {
SPEED_BIN_DDR_800D,
SPEED_BIN_DDR_800E,
......@@ -53,7 +54,8 @@ enum hws_ddr_freq {
DDR_FREQ_900,
DDR_FREQ_360,
DDR_FREQ_1000,
DDR_FREQ_LIMIT
DDR_FREQ_LAST,
DDR_FREQ_SAR
};
enum speed_bin_table_elements {
......
drivers/ddr/marvell/a38x/ddr3_training_ip.h
浏览文件 @ 2b4ffbf6
......@@ -10,11 +10,10 @@
#include "ddr_topology_def.h"
#include "ddr_training_ip_db.h"
#define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.29."
#define MAX_CS_NUM 4
#define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM)
#define MAX_DQ_NUM 40
#define TIP_ENG_LOCK 0x02000000
#define TIP_TX_DLL_RANGE_MAX 64
#define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
#define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1)
......@@ -38,11 +37,15 @@
#define READ_LEVELING_TF_MASK_BIT 0x00010000
#define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000
#define DM_PBS_TX_MASK_BIT 0x00040000
#define RL_DQS_BURST_MASK_BIT 0x00080000
#define CENTRALIZATION_RX_MASK_BIT 0x00100000
#define CENTRALIZATION_TX_MASK_BIT 0x00200000
#define TX_EMPHASIS_MASK_BIT 0x00400000
#define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000
#define VREF_CALIBRATION_MASK_BIT 0x01000000
#define WRITE_LEVELING_LF_MASK_BIT 0x02000000
/* DDR4 Specific Training Mask bits */
enum hws_result {
TEST_FAILED = 0,
......@@ -79,6 +82,7 @@ enum auto_tune_stage {
TX_EMPHASIS,
LOAD_PATTERN_HIGH,
PER_BIT_READ_LEVELING_TF,
WRITE_LEVELING_LF,
MAX_STAGE_LIMIT
};
......@@ -110,7 +114,7 @@ struct pattern_info {
/* CL value for each frequency */
struct cl_val_per_freq {
u8 cl_val[DDR_FREQ_LIMIT];
u8 cl_val[DDR_FREQ_LAST];
};
struct cs_element {
......@@ -167,11 +171,14 @@ int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
int hws_ddr3_tip_init_controller(u32 dev_num,
struct init_cntr_param *init_cntr_prm);
int hws_ddr3_tip_load_topology_map(u32 dev_num,
struct hws_topology_map *topology);
struct mv_ddr_topology_map *topology);
int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
int hws_ddr3_tip_read_training_result(u32 dev_num,
enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
uint64_t mv_ddr_get_memory_size_per_cs_in_bits(void);
uint64_t mv_ddr_get_total_memory_size_in_bits(void);
#endif /* _DDR3_TRAINING_IP_H_ */
drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h
浏览文件 @ 2b4ffbf6
......@@ -45,9 +45,13 @@ int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
u32 cs_num);
int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
u32 mode);
int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num,
u32 direction, u32 mode);
int ddr3_tip_print_regs(u32 dev_num);
int ddr3_tip_reg_dump(u32 dev_num);
int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
u32 burst_length);
int mv_ddr_dm_to_dq_diff_get(u8 adll_byte_high, u8 adll_byte_low, u8 *vw_vector,
int *delta_h_adll, int *delta_l_adll);
int mv_ddr_dm_vw_get(enum hws_pattern pattern, u32 cs, u8 *vw_vector);
#endif /* _DDR3_TRAINING_IP_BIST_H_ */
drivers/ddr/marvell/a38x/ddr3_training_ip_db.h
浏览文件 @ 2b4ffbf6
......@@ -9,7 +9,10 @@
enum hws_pattern {
PATTERN_PBS1,
PATTERN_PBS2,
PATTERN_PBS3,
PATTERN_TEST,
PATTERN_RL,
PATTERN_RL2,
PATTERN_STATIC_PBS,
PATTERN_KILLER_DQ0,
PATTERN_KILLER_DQ1,
......@@ -19,15 +22,73 @@ enum hws_pattern {
PATTERN_KILLER_DQ5,
PATTERN_KILLER_DQ6,
PATTERN_KILLER_DQ7,
PATTERN_PBS3,
PATTERN_RL2,
PATTERN_TEST,
PATTERN_VREF,
PATTERN_FULL_SSO0,
PATTERN_FULL_SSO1,
PATTERN_FULL_SSO2,
PATTERN_FULL_SSO3,
PATTERN_VREF,
PATTERN_LIMIT
PATTERN_LAST,
PATTERN_SSO_FULL_XTALK_DQ0,
PATTERN_SSO_FULL_XTALK_DQ1,
PATTERN_SSO_FULL_XTALK_DQ2,
PATTERN_SSO_FULL_XTALK_DQ3,
PATTERN_SSO_FULL_XTALK_DQ4,
PATTERN_SSO_FULL_XTALK_DQ5,
PATTERN_SSO_FULL_XTALK_DQ6,
PATTERN_SSO_FULL_XTALK_DQ7,
PATTERN_SSO_XTALK_FREE_DQ0,
PATTERN_SSO_XTALK_FREE_DQ1,
PATTERN_SSO_XTALK_FREE_DQ2,
PATTERN_SSO_XTALK_FREE_DQ3,
PATTERN_SSO_XTALK_FREE_DQ4,
PATTERN_SSO_XTALK_FREE_DQ5,
PATTERN_SSO_XTALK_FREE_DQ6,
PATTERN_SSO_XTALK_FREE_DQ7,
PATTERN_ISI_XTALK_FREE
};
enum mv_wl_supp_mode {
WRITE_LEVELING_SUPP_REG_MODE,
WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS,
WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4,
WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3,
WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8
};
enum mv_ddr_dev_attribute {
MV_ATTR_TIP_REV,
MV_ATTR_PHY_EDGE,
MV_ATTR_OCTET_PER_INTERFACE,
MV_ATTR_PLL_BEFORE_INIT,
MV_ATTR_TUNE_MASK,
MV_ATTR_INIT_FREQ,
MV_ATTR_MID_FREQ,
MV_ATTR_DFS_LOW_FREQ,
MV_ATTR_DFS_LOW_PHY,
MV_ATTR_DELAY_ENABLE,
MV_ATTR_CK_DELAY,
MV_ATTR_CA_DELAY,
MV_ATTR_INTERLEAVE_WA,
MV_ATTR_LAST
};
enum mv_ddr_tip_revison {
MV_TIP_REV_NA,
MV_TIP_REV_1, /* NP5 */
MV_TIP_REV_2, /* BC2 */
MV_TIP_REV_3, /* AC3 */
MV_TIP_REV_4, /* A-380/A-390 */
MV_TIP_REV_LAST
};
enum mv_ddr_phy_edge {
MV_DDR_PHY_EDGE_POSITIVE,
MV_DDR_PHY_EDGE_NEGATIVE
};
/* Device attribute functions */
void ddr3_tip_dev_attr_init(u32 dev_num);
u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id);
void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value);
#endif /* _DDR3_TRAINING_IP_DB_H_ */
drivers/ddr/marvell/a38x/ddr3_training_leveling.h
浏览文件 @ 2b4ffbf6
......@@ -11,6 +11,6 @@
int ddr3_tip_print_wl_supp_result(u32 dev_num);
int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
u32 *cs_mask);
u32 hws_ddr3_tip_max_cs_get(void);
u32 ddr3_tip_max_cs_get(u32 dev_num);
#endif /* _DDR3_TRAINING_LEVELING_H_ */
drivers/ddr/marvell/a38x/ddr_ml_wrapper.h 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_build_message.c 0 → 100644
浏览文件 @ 2b4ffbf6
const char mv_ddr_build_message[] = ""; const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-17.10.4";
drivers/ddr/marvell/a38x/mv_ddr_common.c 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_common.h 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_plat.c 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_regs.h 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_spd.c 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_spd.h 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.c 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_topology.c 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/mv_ddr_topology.h 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/seq_exec.h 0 → 100644
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/silicon_if.h 已删除 100644 → 0
浏览文件 @ 00a77677
此差异已折叠。
drivers/ddr/marvell/a38x/xor.c
浏览文件 @ 2b4ffbf6
此差异已折叠。
drivers/ddr/marvell/a38x/xor.h
浏览文件 @ 2b4ffbf6
此差异已折叠。
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