Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

arch/powerpc/cpu/mpc85xx/b4860_serdes.c

@@ -18,12 +18,32 @@ struct serdes_config {
 #ifdef CONFIG_PPC_B4860
 static struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
+	{0x02, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x04, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x05, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x06, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x08, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x09, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x0A, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x0B, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x0C, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x0E, {CPRI8, CPRI7,	CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x12, {CPRI8, CPRI7,	CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
@@ -32,6 +52,9 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2F, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x30, {AURORA, AURORA,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
@@ -44,18 +67,38 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 	{0x34, {AURORA, AURORA,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x39, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x3A, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x3C, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x3D, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x3E, {CPRI8, CPRI7,	CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x5C, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x5D, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{}
 };
 static struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
+	{0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		AURORA, AURORA,	SRIO1, SRIO1} },
 	{0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		AURORA, AURORA,	SRIO1, SRIO1}},
 	{0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		AURORA, AURORA,	SRIO1, SRIO1}},
+	{0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		AURORA, AURORA, SRIO1, SRIO1} },
 	{0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2,
 		AURORA, AURORA, SRIO1, SRIO1}},
@@ -63,6 +106,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 		SRIO2, SRIO2,
 		AURORA, AURORA,
 		SRIO1, SRIO1}},
+	{0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
@@ -75,18 +121,30 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 	{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2, AURORA, AURORA,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2, AURORA, AURORA,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
 	{0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2, AURORA, AURORA,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
@@ -101,6 +159,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -229,6 +229,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (IS_SVR_REV(svr, 1, 0))
 		puts("Work-around for Erratum A005871 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
+	if (SVR_MAJ(get_svr()) == 1)
+		puts("Work-around for Erratum A006475 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
+	if (SVR_MAJ(get_svr()) == 1)
+		puts("Work-around for Erratum A006384 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
 	/* This work-around is implemented in PBI, so just check for it */
 	check_erratum_a4849(svr);
@@ -264,6 +272,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
 	    (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
 		puts("Work-around for Erratum I2C-A004447 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+	if (has_erratum_a006261())
+		puts("Work-around for Erratum A006261 enabled\n");
 #endif
 	return 0;
 }

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -36,6 +36,54 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
+{
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+	u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
+
+	/* Increase Disconnect Threshold by 50mV */
+	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+						INC_DCNT_THRESHOLD_50MV;
+	/* Enable programming of USB High speed Disconnect threshold */
+	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+	out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
+
+	xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
+	/* Increase Disconnect Threshold by 50mV */
+	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+						INC_DCNT_THRESHOLD_50MV;
+	/* Enable programming of USB High speed Disconnect threshold */
+	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+	out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
+#else
+
+	u32 temp = 0;
+	u32 status = in_be32(&usb_phy->status1);
+
+	u32 squelch_prog_rd_0_2 =
+		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+	u32 squelch_prog_rd_3_5 =
+		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+	setbits_be32(&usb_phy->config1,
+		     CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+	setbits_be32(&usb_phy->config2,
+		     CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+
+	temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
+
+	temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
+#endif
+}
+#endif
+
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -625,6 +673,10 @@ skip_l2:
 	{
 		struct ccsr_usb_phy __iomem *usb_phy1 =
 			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+		if (has_erratum_a006261())
+			fsl_erratum_a006261_workaround(usb_phy1);
+#endif
 		out_be32(&usb_phy1->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
@@ -633,6 +685,10 @@ skip_l2:
 	{
 		struct ccsr_usb_phy __iomem *usb_phy2 =
 			(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+		if (has_erratum_a006261())
+			fsl_erratum_a006261_workaround(usb_phy2);
+#endif
 		out_be32(&usb_phy2->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
@@ -672,8 +728,14 @@ skip_l2:
 			     CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 		setbits_be32(&usb_phy->port2.pwrfltcfg,
 			     CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+		if (has_erratum_a006261())
+			fsl_erratum_a006261_workaround(usb_phy);
 #endif
 
+#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
+
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
 #endif

arch/powerpc/include/asm/config_mpc85xx.h

@@ -154,6 +154,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
@@ -386,6 +387,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
 
 #elif defined(CONFIG_PPC_P3041)
@@ -424,6 +426,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x20
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
@@ -507,6 +510,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x20
 
 #elif defined(CONFIG_PPC_P5040)
@@ -538,6 +542,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004699
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 
@@ -633,6 +638,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
@@ -662,11 +668,14 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A006475
+#define CONFIG_SYS_FSL_ERRATUM_A006384
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
 #ifdef CONFIG_PPC_B4860
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS	2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
@@ -679,6 +688,7 @@
 #define CONFIG_SYS_FSL_SRIO_LIODN
 #else
 #define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS	1
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
@@ -722,6 +732,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)

arch/powerpc/include/asm/fsl_errata.h

@@ -26,4 +26,38 @@ static inline bool has_erratum_a006379(void)
 }
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+static inline bool has_erratum_a006261(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P2041:
+	case SVR_P2040:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P3041:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) ||
+			IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P5010:
+	case SVR_P5020:
+	case SVR_P5021:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T4240:
+	case SVR_T4160:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T1040:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_P5040:
+		return IS_SVR_REV(svr, 1, 0);
+	}
+
+	return false;
+}
+#endif
+
 #endif

arch/powerpc/include/asm/immap_85xx.h

@@ -1722,6 +1722,9 @@ typedef struct ccsr_gur {
 	u32	rstrqpblsr;	/* Reset request preboot loader status */
 	u8	res11[8];
 	u32	rstrqmr1;	/* Reset request mask */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK      0x00000800
+#endif
 	u8	res12[4];
 	u32	rstrqsr1;	/* Reset request status */
 	u8	res13[4];
@@ -1770,6 +1773,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL	0x00000080
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH	0x00000000
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT	0x80000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET	0x28
+#define PXCKEN_MASK	0x80000000
+#define PXCK_MASK	0x00FF0000
+#define PXCK_BITS_START	16
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
@@ -2492,6 +2499,7 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_SDEN	0x00000020
 #define SRDS_RSTCTL_SDRST_B	0x00000040
 #define SRDS_RSTCTL_PLLRST_B	0x00000080
+#define SRDS_RSTCTL_RSTERR_SHIFT  29
 		u32	pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_POFF		0x80000000
 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
@@ -2501,6 +2509,7 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
@@ -2508,9 +2517,22 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
 #define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
 #define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+#define SRDS_PLLCR0_DCBIAS_OVRD		0x000000F0
+#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT	4
 		u32	pllcr1; /* PLL Control Register 1 */
-#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
-		u32	res_0c;	/* 0x00c */
+#define SRDS_PLLCR1_BCAP_EN		0x20000000
+#define SRDS_PLLCR1_BCAP_OVD		0x10000000
+#define SRDS_PLLCR1_PLL_FCAP		0x001F8000
+#define SRDS_PLLCR1_PLL_FCAP_SHIFT	15
+#define SRDS_PLLCR1_PLL_BWSEL		0x08000000
+#define SRDS_PLLCR1_BYP_CAL		0x02000000
+		u32	pllsr2;	/* At 0x00c, PLL Status Register 2 */
+#define SRDS_PLLSR2_BCAP_EN		0x00800000
+#define SRDS_PLLSR2_BCAP_EN_SHIFT	23
+#define SRDS_PLLSR2_FCAP		0x003F0000
+#define SRDS_PLLSR2_FCAP_SHIFT		16
+#define SRDS_PLLSR2_DCBIAS		0x000F0000
+#define SRDS_PLLSR2_DCBIAS_SHIFT	16
 		u32	pllcr3;
 		u32	pllcr4;
 		u8	res_18[0x20-0x18];
@@ -2845,6 +2867,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
+#define CONFIG_SYS_FSL_SCFG_OFFSET		0xFC000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
@@ -2962,6 +2985,10 @@ struct ccsr_pman {
 
 #define CONFIG_SYS_FSL_CPC_ADDR	\
 	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_ADDR	\
+	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR	\
+	(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_BMAN_ADDR \

arch/powerpc/lib/bootm.c

@@ -53,6 +53,13 @@ static void boot_jump_linux(bootm_headers_t *images)
 
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
+#ifdef CONFIG_BOOTSTAGE_FDT
+	bootstage_fdt_add_report();
+#endif
+#ifdef CONFIG_BOOTSTAGE_REPORT
+	bootstage_report();
+#endif
+
 #if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500)
 	unlock_ram_in_cache();
 #endif

board/freescale/b4860qds/b4860qds.c

@@ -11,6 +11,7 @@
 #include <linux/compiler.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
+#include <asm/errno.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
@@ -28,7 +29,6 @@
 
 #define CLK_MUX_SEL_MASK	0x4
 #define ETH_PHY_CLK_OUT		0x4
-#define PLL_NUM			2
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -120,6 +120,7 @@ int configure_vsc3316_3308(void)
 	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
 
 	switch (serdes1_prtcl) {
+	case 0x29:
 	case 0x2a:
 	case 0x2C:
 	case 0x2D:
@@ -151,7 +152,55 @@ int configure_vsc3316_3308(void)
 		}
 		break;
 
+	case 0x02:
+	case 0x04:
+	case 0x05:
+	case 0x06:
+	case 0x08:
+	case 0x09:
+	case 0x0A:
+	case 0x0B:
+	case 0x0C:
+	case 0x30:
+	case 0x32:
+	case 0x33:
+	case 0x34:
+	case 0x39:
+	case 0x3A:
+	case 0x3C:
+	case 0x3D:
+	case 0x5C:
+	case 0x5D:
+			/*
+			 * Configuration:
+			 * SERDES: 1
+			 * Lanes: A,B: AURORA
+			 * Lanes: C,d: SGMII
+			 * Lanes: E,F,G,H: CPRI
+			 */
+		debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
+				" and CPRI. srds_prctl:%x\n", serdes1_prtcl);
+		num_vsc16_con = NUM_CON_VSC3316;
+		/* Configure VSC3316 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+		if (!ret) {
+			ret = vsc3316_config(VSC3316_TX_ADDRESS,
+					vsc16_tx_sfp_sgmii_aurora,
+					num_vsc16_con);
+			if (ret)
+				return ret;
+			ret = vsc3316_config(VSC3316_RX_ADDRESS,
+					vsc16_rx_sfp_sgmii_aurora,
+					num_vsc16_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+
 #ifdef CONFIG_PPC_B4420
+	case 0x17:
 	case 0x18:
 			/*
 			 * Configuration:
@@ -239,14 +288,191 @@ int configure_vsc3316_3308(void)
 	return 0;
 }
 
+static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
+{
+	u32 rst_err;
+
+	/* Steps For SerDes PLLs reset and reconfiguration
+	 * or PLL power-up procedure
+	 */
+	debug("CALIBRATE PLL:%d\n", pll_num);
+	clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+			SRDS_RSTCTL_SDRST_B);
+	udelay(10);
+	clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+		(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+	udelay(10);
+	setbits_be32(&srds_regs->bank[pll_num].rstctl,
+			SRDS_RSTCTL_RST);
+	setbits_be32(&srds_regs->bank[pll_num].rstctl,
+		(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+		| SRDS_RSTCTL_SDRST_B));
+
+	udelay(20);
+
+	/* Check whether PLL has been locked or not */
+	rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
+				SRDS_RSTCTL_RSTERR;
+	rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
+	debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
+	if (rst_err)
+		return rst_err;
+
+	return rst_err;
+}
+
+static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
+{
+	int ret = 0;
+	u32 fcap, dcbias, bcap, pllcr1, pllcr0;
+
+	if (calibrate_pll(srds_regs, pll_num)) {
+		/* STEP 1 */
+		/* Read fcap, dcbias and bcap value */
+		clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+				SRDS_PLLCR0_DCBIAS_OUT_EN);
+		fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+					SRDS_PLLSR2_FCAP;
+		fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
+		bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+					SRDS_PLLSR2_BCAP_EN;
+		bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
+		setbits_be32(&srds_regs->bank[pll_num].pllcr0,
+				SRDS_PLLCR0_DCBIAS_OUT_EN);
+		dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+					SRDS_PLLSR2_DCBIAS;
+		dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
+		debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
+					bcap, fcap, dcbias);
+		if (fcap == 0 && bcap == 1) {
+			/* Step 3 */
+			clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+				 | SRDS_RSTCTL_SDRST_B));
+			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BCAP_EN);
+			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BCAP_OVD);
+			if (calibrate_pll(srds_regs, pll_num)) {
+				/*save the fcap, dcbias and bcap values*/
+				clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+						SRDS_PLLCR0_DCBIAS_OUT_EN);
+				fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
+					& SRDS_PLLSR2_FCAP;
+				fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
+				bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
+					& SRDS_PLLSR2_BCAP_EN;
+				bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
+				setbits_be32(&srds_regs->bank[pll_num].pllcr0,
+						SRDS_PLLCR0_DCBIAS_OUT_EN);
+				dcbias = in_be32
+					(&srds_regs->bank[pll_num].pllsr2) &
+							SRDS_PLLSR2_DCBIAS;
+				dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
+
+				/* Step 4*/
+				clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+				 | SRDS_RSTCTL_SDRST_B));
+				setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+						SRDS_PLLCR1_BYP_CAL);
+				clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+						SRDS_PLLCR1_BCAP_EN);
+				setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+						SRDS_PLLCR1_BCAP_OVD);
+				/* change the fcap and dcbias to the saved
+				 * values from Step 3 */
+				clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+							SRDS_PLLCR1_PLL_FCAP);
+				pllcr1 = (in_be32
+					(&srds_regs->bank[pll_num].pllcr1)|
+					(fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
+				out_be32(&srds_regs->bank[pll_num].pllcr1,
+							pllcr1);
+				clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+						SRDS_PLLCR0_DCBIAS_OVRD);
+				pllcr0 = (in_be32
+				(&srds_regs->bank[pll_num].pllcr0)|
+				(dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
+				out_be32(&srds_regs->bank[pll_num].pllcr0,
+							pllcr0);
+				ret = calibrate_pll(srds_regs, pll_num);
+				if (ret)
+					return ret;
+			} else {
+				goto out;
+			}
+		} else { /* Step 5 */
+			clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+				 | SRDS_RSTCTL_SDRST_B));
+			udelay(10);
+			/* Change the fcap, dcbias, and bcap to the
+			 * values from Step 1 */
+			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BYP_CAL);
+			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+						SRDS_PLLCR1_PLL_FCAP);
+			pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
+				(fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
+			out_be32(&srds_regs->bank[pll_num].pllcr1,
+						pllcr1);
+			clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+						SRDS_PLLCR0_DCBIAS_OVRD);
+			pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
+				(dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
+			out_be32(&srds_regs->bank[pll_num].pllcr0,
+						pllcr0);
+			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BCAP_EN);
+			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BCAP_OVD);
+			ret = calibrate_pll(srds_regs, pll_num);
+			if (ret)
+				return ret;
+		}
+	}
+out:
+	return 0;
+}
+
+static int check_serdes_pll_locks(void)
+{
+	serdes_corenet_t *srds1_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	serdes_corenet_t *srds2_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+	int i, ret1, ret2;
+
+	debug("\nSerDes1 Lock check\n");
+	for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+		ret1 = check_pll_locks(srds1_regs, i);
+		if (ret1) {
+			printf("SerDes1, PLL:%d didnt lock\n", i);
+			return ret1;
+		}
+	}
+	debug("\nSerDes2 Lock check\n");
+	for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+		ret2 = check_pll_locks(srds2_regs, i);
+		if (ret2) {
+			printf("SerDes2, PLL:%d didnt lock\n", i);
+			return ret2;
+		}
+	}
+
+	return 0;
+}
+
 int config_serdes1_refclks(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	serdes_corenet_t *srds_regs =
 		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 	u32 serdes1_prtcl, lane;
-	unsigned int flag_sgmii_prtcl = 0;
-	int ret, i;
+	unsigned int flag_sgmii_aurora_prtcl = 0;
+	int i;
+	int ret = 0;
 
 	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
 			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -257,10 +483,12 @@ int config_serdes1_refclks(void)
 	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
 
-	/* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
+	/* To prevent generation of reset request from SerDes
+	 * while changing the refclks, By setting SRDS_RST_MSK bit,
+	 * SerDes reset event cannot cause a reset request
 	 */
-	for (i = 0; i < PLL_NUM; i++)
-		clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
+	setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
 	/* Reconfigure IDT idt8t49n222a device for CPRI to work
 	 * For this SerDes1's Refclk1 and refclk2 need to be set
 	 * to 122.88MHz
@@ -270,6 +498,25 @@ int config_serdes1_refclks(void)
 	case 0x2C:
 	case 0x2D:
 	case 0x2E:
+	case 0x02:
+	case 0x04:
+	case 0x05:
+	case 0x06:
+	case 0x08:
+	case 0x09:
+	case 0x0A:
+	case 0x0B:
+	case 0x0C:
+	case 0x30:
+	case 0x32:
+	case 0x33:
+	case 0x34:
+	case 0x39:
+	case 0x3A:
+	case 0x3C:
+	case 0x3D:
+	case 0x5C:
+	case 0x5D:
 		debug("Configuring idt8t49n222a for CPRI SerDes clks:"
 			" for srds_prctl:%x\n", serdes1_prtcl);
 		ret = select_i2c_ch_pca(I2C_CH_IDT);
@@ -279,16 +526,16 @@ int config_serdes1_refclks(void)
 					SERDES_REFCLK_122_88, 0);
 			if (ret) {
 				printf("IDT8T49N222A configuration failed.\n");
-				return ret;
+				goto out;
 			} else
-				printf("IDT8T49N222A configured.\n");
+				debug("IDT8T49N222A configured.\n");
 		} else {
-			return ret;
+			goto out;
 		}
 		select_i2c_ch_pca(I2C_CH_DEFAULT);
 
 		/* Change SerDes1's Refclk1 to 125MHz for on board
-		 * SGMIIs to work
+		 * SGMIIs or Aurora to work
 		 */
 		for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 			enum srds_prtcl lane_prtcl = serdes_get_prtcl
@@ -300,20 +547,21 @@ int config_serdes1_refclks(void)
 			case SGMII_FM1_DTSEC4:
 			case SGMII_FM1_DTSEC5:
 			case SGMII_FM1_DTSEC6:
-				flag_sgmii_prtcl++;
+			case AURORA:
+				flag_sgmii_aurora_prtcl++;
 				break;
 			default:
 				break;
 			}
 		}
 
-		if (flag_sgmii_prtcl)
+		if (flag_sgmii_aurora_prtcl)
 			QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
 
 		/* Steps For SerDes PLLs reset and reconfiguration after
 		 * changing SerDes's refclks
 		 */
-		for (i = 0; i < PLL_NUM; i++) {
+		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 			debug("For PLL%d reset and reconfiguration after"
 			       " changing refclks\n", i+1);
 			clrbits_be32(&srds_regs->bank[i].rstctl,
@@ -333,16 +581,101 @@ int config_serdes1_refclks(void)
 		printf("WARNING:IDT8T49N222A configuration not"
 			" supported for:%x SerDes1 Protocol.\n",
 			serdes1_prtcl);
-		return -1;
 	}
 
-	return 0;
+out:
+	/* Clearing SRDS_RST_MSK bit as now
+	 * SerDes reset event can cause a reset request
+	 */
+	clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+	return ret;
+}
+
+int config_serdes2_refclks(void)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	serdes_corenet_t *srds2_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+	u32 serdes2_prtcl;
+	int ret = 0;
+	int i;
+
+	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	if (!serdes2_prtcl) {
+		debug("SERDES2 is not enabled\n");
+		return -ENODEV;
+	}
+	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+	/* To prevent generation of reset request from SerDes
+	 * while changing the refclks, By setting SRDS_RST_MSK bit,
+	 * SerDes reset event cannot cause a reset request
+	 */
+	setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
+	/* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
+	 * For this SerDes2's Refclk1 need to be set to 100MHz
+	 */
+	switch (serdes2_prtcl) {
+	case 0x9E:
+	case 0x9A:
+	case 0xb2:
+		debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
+			serdes2_prtcl);
+		ret = select_i2c_ch_pca(I2C_CH_IDT);
+		if (!ret) {
+			ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
+					SERDES_REFCLK_100,
+					SERDES_REFCLK_156_25, 0);
+			if (ret) {
+				printf("IDT8T49N222A configuration failed.\n");
+				goto out;
+			} else
+				debug("IDT8T49N222A configured.\n");
+		} else {
+			goto out;
+		}
+		select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+		/* Steps For SerDes PLLs reset and reconfiguration after
+		 * changing SerDes's refclks
+		 */
+		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+			clrbits_be32(&srds2_regs->bank[i].rstctl,
+					SRDS_RSTCTL_SDRST_B);
+			udelay(10);
+			clrbits_be32(&srds2_regs->bank[i].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+			udelay(10);
+			setbits_be32(&srds2_regs->bank[i].rstctl,
+					SRDS_RSTCTL_RST);
+			setbits_be32(&srds2_regs->bank[i].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+				| SRDS_RSTCTL_SDRST_B));
+
+			udelay(10);
+		}
+		break;
+	default:
+		printf("IDT configuration not supported for:%x S2 Protocol.\n",
+			serdes2_prtcl);
+	}
+
+out:
+	/* Clearing SRDS_RST_MSK bit as now
+	 * SerDes reset event can cause a reset request
+	 */
+	clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+	return ret;
 }
 
 int board_early_init_r(void)
 {
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+	int ret;
 
 	/*
 	 * Remap Boot flash + PROMJET region to caching-inhibited
@@ -375,6 +708,35 @@ int board_early_init_r(void)
 	else
 		printf("SerDes1 Refclks have been set.\n");
 
+	/* SerDes2 refclks need to be set again, as default clks
+	 * are not suitable for PCIe SATA to work
+	 * This function will set SerDes2's Refclk1 and refclk2
+	 * for SerDes2 protocols having PCIe in them
+	 * for PCIe SATA to work
+	 */
+	ret = config_serdes2_refclks();
+	if (!ret)
+		printf("SerDes2 Refclks have been set.\n");
+	else if (ret == -ENODEV)
+		printf("SerDes disable, Refclks couldn't change.\n");
+	else
+		printf("SerDes2 Refclk reconfiguring failed.\n");
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
+			defined(CONFIG_SYS_FSL_ERRATUM_A006475)
+	/* Rechecking the SerDes locks after all SerDes configurations
+	 * are done, As SerDes PLLs may not lock reliably at 5 G VCO
+	 * and at cold temperatures.
+	 * Following sequence ensure the proper locking of SerDes PLLs.
+	 */
+	if (SVR_MAJ(get_svr()) == 1) {
+		if (check_serdes_pll_locks())
+			printf("SerDes plls still not locked properly.\n");
+		else
+			printf("SerDes plls have been locked well.\n");
+	}
+#endif
+
 	/* Configure VSC3316 and VSC3308 crossbar switches */
 	if (configure_vsc3316_3308())
 		printf("VSC:failed to configure VSC3316/3308.\n");

board/freescale/b4860qds/b4860qds_crossbar_con.h

@@ -24,6 +24,10 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
 				{7, 8}, {9, 0}, {5, 14}, {4, 15},
 				{-1, -1}, {-1, -1} };
 
+static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
+				{7, 8}, {9, 0}, {5, 14},
+				{4, 15}, {2, 12}, {12, 13} };
+
 #ifdef CONFIG_PPC_B4420
 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
@@ -46,6 +50,10 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
 				{7, 8}, {1, 9}, {14, 11}, {15, 10},
 				{-1, -1}, {-1, -1} };
 
+static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
+				{7, 8}, {1, 9}, {14, 11},
+				{15, 10}, {13, 3}, {12, 12} };
+
 #ifdef CONFIG_PPC_B4420
 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };

board/freescale/b4860qds/eth_b4860qds.c

@@ -66,6 +66,7 @@ static void initialize_lane_to_slot(void)
 			serdes2_prtcl);
 
 	switch (serdes2_prtcl) {
+	case 0x17:
 	case 0x18:
 		/*
 		 * Configuration:
@@ -198,6 +199,7 @@ int board_eth_init(bd_t *bis)
 	fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
 
 	switch (serdes1_prtcl) {
+	case 0x29:
 	case 0x2a:
 		/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
 		debug("Setting phy addresses for FM1_DTSEC5: %x and"
@@ -209,6 +211,7 @@ int board_eth_init(bd_t *bis)
 				CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
 		break;
 #ifdef CONFIG_PPC_B4420
+	case 0x17:
 	case 0x18:
 		/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
 		debug("Setting phy addresses for FM1_DTSEC3: %x and"
@@ -228,6 +231,7 @@ int board_eth_init(bd_t *bis)
 		break;
 	}
 	switch (serdes2_prtcl) {
+	case 0x17:
 	case 0x18:
 		debug("Setting phy addresses on SGMII Riser card for"
 				"FM1_DTSEC ports: \n");
@@ -240,6 +244,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC4,
 				CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
 		break;
+	case 0x48:
 	case 0x49:
 		debug("Setting phy addresses on SGMII Riser card for"
 				"FM1_DTSEC ports: \n");

board/freescale/t1040qds/Makefile

@@ -10,3 +10,4 @@ obj-$(CONFIG_PCI)     += pci.o
 obj-y	+= law.o
 obj-y	+= tlb.o
 obj-y	+= eth.o
+obj-y	+= diu.o

board/freescale/t1040qds/diu.c

+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include <fsl_diu_fb.h>
+#include "../common/qixis.h"
+#include "t1040qds.h"
+#include "t1040qds_qixis.h"
+#include <i2c.h>
+
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG		0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG		0x33
+#define I2C_DVI_PLL_DIVIDER_REG			0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG		0x35
+#define I2C_DVI_PLL_FILTER_REG			0x36
+#define I2C_DVI_TEST_PATTERN_REG		0x48
+#define I2C_DVI_POWER_MGMT_REG			0x49
+#define I2C_DVI_LOCK_STATE_REG			0x4D
+#define I2C_DVI_SYNC_POLARITY_REG		0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU->DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL		0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL	0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL	0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL	0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL	0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL	0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL	0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL		0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL			0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL		0x00
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register.  So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F		0x10000000
+#define AD_ALPHA_C_SHIFT	25
+#define AD_BLUE_C_SHIFT		23
+#define AD_GREEN_C_SHIFT	21
+#define AD_RED_C_SHIFT		19
+#define AD_PIXEL_S_SHIFT	16
+#define AD_COMP_3_SHIFT		12
+#define AD_COMP_2_SHIFT		8
+#define AD_COMP_1_SHIFT		4
+#define AD_COMP_0_SHIFT		0
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+	int ret;
+	u8 temp;
+	select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+
+	temp = I2C_DVI_TEST_PATTERN_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+			&temp, 1);
+	if (ret) {
+		puts("I2C: failed to select proper dvi test pattern\n");
+		return ret;
+	}
+	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+			1, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi input data format\n");
+		return ret;
+	}
+
+	/* Set Sync polarity register */
+	temp = I2C_DVI_SYNC_POLARITY_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+			&temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi syc polarity\n");
+		return ret;
+	}
+
+	/* Set PLL registers based on pixel clock rate*/
+	if (pixclock > 65000000) {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_CHARGE_CNTL_REG, 1,	&temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	} else {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	}
+
+	temp = I2C_DVI_POWER_MGMT_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
+			&temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi power mgmt\n");
+		return ret;
+	}
+
+	udelay(500);
+
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	return 0;
+}
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	unsigned long speed_ccb, temp;
+	u32 pixval;
+	int ret = 0;
+	speed_ccb = get_bus_freq(0);
+	temp = 1000000000 / pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+
+	/* Program HDMI encoder */
+	ret = diu_set_dvi_encoder(temp);
+	if (ret) {
+		puts("Failed to set DVI encoder\n");
+		return;
+	}
+
+	/* Program pixel clock */
+	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
+	/* enable clock*/
+	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+	u32 pixel_format;
+	u8 sw;
+
+	/*Route I2C4 to DIU system as HSYNC/VSYNC*/
+	sw = QIXIS_READ(brdcfg[5]);
+	QIXIS_WRITE(brdcfg[5],
+		    ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
+
+	/*Configure Display ouput port as HDMI*/
+	sw = QIXIS_READ(brdcfg[15]);
+	QIXIS_WRITE(brdcfg[15],
+		    ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
+		      | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
+
+	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+	printf("DIU:   Switching to monitor @ %ux%u\n",  xres, yres);
+
+
+	return fsl_diu_init(xres, yres, pixel_format, 0);
+}

board/freescale/t1040qds/t1040qds.h

@@ -9,5 +9,6 @@
 
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
+int select_i2c_ch_pca9547(u8 ch);
 
 #endif

board/freescale/t1040qds/t1040qds_qixis.h

@@ -13,6 +13,18 @@
 #define BRDCFG4_EMISEL_MASK		0xE0
 #define BRDCFG4_EMISEL_SHIFT		5
 
+/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
+#define BRDCFG5_IMX_MASK		0xC0
+#define BRDCFG5_IMX_DIU			0x80
+
+/* BRDCFG15[3] controls LCD Panel Powerdown*/
+#define BRDCFG15_LCDPD_MASK		0x10
+#define BRDCFG15_LCDPD_ENABLED		0x00
+
+/* BRDCFG15[6:7] controls DIU MUX selction*/
+#define BRDCFG15_DIUSEL_MASK		0x03
+#define BRDCFG15_DIUSEL_HDMI		0x00
+
 /* SYSCLK */
 #define QIXIS_SYSCLK_66			0x0
 #define QIXIS_SYSCLK_83			0x1

board/freescale/t104xrdb/ddr.c

@@ -46,7 +46,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 
 	pbsp = udimms[0];
 
-	/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+	/* Get clk_adjust according to the board ddr
 	 * freqency and n_banks specified in board_specific_parameters table.
 	 */
 	ddr_freq = get_ddr_freq(0) / 1000000;
@@ -54,14 +54,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		if (pbsp->n_ranks == pdimm->n_ranks &&
 		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
 			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
 				popts->clk_adjust = pbsp->clk_adjust;
 				popts->wrlvl_start = pbsp->wrlvl_start;
 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -74,13 +70,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		printf("for data rate %lu MT/s\n", ddr_freq);
 		printf("Trying to use the highest speed (%u) parameters\n",
 		       pbsp_highest->datarate_mhz_high);
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
@@ -112,8 +105,8 @@ found:
 	popts->zq_en = 1;
 
 	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
 }
 
 phys_size_t initdram(int board_type)

board/freescale/t104xrdb/ddr.h

@@ -6,7 +6,6 @@
 
 #ifndef __DDR_H__
 #define __DDR_H__
-
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 2,
 	.rank_density = 2147483648u,
@@ -14,22 +13,21 @@ dimm_params_t ddr_raw_timing = {
 	.primary_sdram_width = 64,
 	.ec_sdram_width = 8,
 	.registered_dimm = 0,
-	.mirrored_dimm = 1,
+	.mirrored_dimm = 0,
 	.n_row_addr = 15,
 	.n_col_addr = 10,
 	.n_banks_per_sdram_device = 8,
 	.edc_config = 2,	/* ECC */
 	.burst_lengths_bitmask = 0x0c,
-
 	.tckmin_x_ps = 1071,
-	.caslat_x = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
-	.taa_ps = 13910,
+	.caslat_x = 0xfe << 4,	/* 5,6,7,8,9,10,11 */
+	.taa_ps = 13125,
 	.twr_ps = 15000,
-	.trcd_ps = 13910,
+	.trcd_ps = 13125,
 	.trrd_ps = 6000,
-	.trp_ps = 13910,
+	.trp_ps = 13125,
 	.tras_ps = 34000,
-	.trc_ps = 48910,
+	.trc_ps = 48125,
 	.trfc_ps = 260000,
 	.twtr_ps = 7500,
 	.trtp_ps = 7500,
@@ -45,9 +43,6 @@ struct board_specific_parameters {
 	u32 wrlvl_start;
 	u32 wrlvl_ctl_2;
 	u32 wrlvl_ctl_3;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2t;
 };
 
 /*
@@ -59,14 +54,21 @@ struct board_specific_parameters {
 static const struct board_specific_parameters udimm0[] = {
 	/*
 	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2
 	 */
-	{2,  1066, 4, 8,     4, 0x05070609, 0x08090a08,   0xff,    2,  0},
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
+	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
+	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  833,  4, 4,     6, 0x06060607, 0x08080807},
+	{1,  833,  0, 4,     6, 0x06060607, 0x08080807},
+	{1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
 	{}
 };
 

board/freescale/t208xqds/eth_t208xqds.c

@@ -36,14 +36,15 @@
 #define EMI1_SLOT3	3
 #define EMI1_SLOT4	4
 #define EMI1_SLOT5	5
+#define EMI2            7
 #elif defined(CONFIG_T2081QDS)
 #define EMI1_SLOT2      3
 #define EMI1_SLOT3      4
 #define EMI1_SLOT5      5
 #define EMI1_SLOT6      6
 #define EMI1_SLOT7      7
-#endif
 #define EMI2		8
+#endif
 
 static int mdio_mux[NUM_FM_PORTS];
 

board/freescale/t208xrdb/Makefile

+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_T2080RDB) += t208xrdb.o
+obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
+obj-$(CONFIG_T2080RDB) += cpld.o
+obj-$(CONFIG_PCI)      += pci.o
+obj-y   += ddr.o
+obj-y   += law.o
+obj-y   += tlb.o

board/freescale/t208xrdb/README

+T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
+It can work in two mode: standalone mode and PCIe endpoint mode.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+   - Up to four 10 Gbps Ethernet MACs
+   - Up to eight 1 Gbps Ethernet MACs
+   - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+   - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 2.0) controllers
+   - Two high-speed USB 2.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+   - Enhanced serial peripheral interface (eSPI)
+   - Four I2C controllers
+   - Four 2-pin UARTs or two 4-pin UARTs
+   - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+Differences between T2080 and T2081
+-----------------------------------
+  Feature		T2080	 T2081
+  1G Ethernet numbers:  8	 6
+  10G Ethernet numbers: 4	 2
+  SerDes lanes:		16	 8
+  Serial RapidIO,RMan:  2	 no
+  SATA Controller:	2	 no
+  Aurora:		yes	 no
+  SoC Package:		896-pins 780-pins
+
+
+T2080PCIe-RDB board Overview
+----------------------------
+ - SERDES Configuration
+     - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+     - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
+     - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
+     - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
+     - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
+     - SerDes-2 Lane G-H: to SATA1 & SATA2
+ - Ethernet
+     - Two on-board 10M/100M/1G RGMII ethernet ports
+     - Two on-board 10Gbps XFI fiber ports
+     - Two on-board 10Gbps Base-T copper ports
+ - DDR Memory
+     - Supports 72bit 4GB DDR3-LP SODIMM
+ - PCIe
+     - One PCIe x4 gold-finger
+     - One PCIe x4 connector
+     - One PCIe x2 end-point device (C293 Crypto co-processor)
+ - IFC/Local Bus
+     - NOR:  128MB 16-bit NOR Flash
+     - NAND: 512MB 8-bit NAND flash
+     - CPLD: for system controlling with programable header on-board
+ - SATA
+     - Two SATA 2.0 onnectors on-board
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     - Two type A ports with 5V@1.5A per port.
+ - SDHC
+     - one TF-card connector on-board
+ - SPI
+     -  On-board 64MB SPI flash
+ - Other
+     - Two Serial ports
+     - Four I2C ports
+
+
+System Memory map
+-----------------
+Start Address  End Address      Description			Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD			4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
+0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space		64KB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal	32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal	32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
+0xC_4000_0000  0xC_4FFF_FFFF    PCI Express 4 Mem Space		256MB
+0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 3 Mem Space		256MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 2 Mem Space		256MB
+0xC_0000_0000  0xC_1FFF_FFFF    PCI Express 1 Mem Space		512MB
+0x0_0000_0000  0x0_ffff_ffff    DDR				4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address   End Address	Definition			Max size
+0xEFF40000	0xEFFFFFFF	u-boot (current bank)		768KB
+0xEFF20000	0xEFF3FFFF	u-boot env (current bank)	128KB
+0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
+0xEFE00000	0xEFE3FFFF	PHY CS4315 firmware		256KB
+0xED300000	0xEFEFFFFF	rootfs (alt bank)		44MB
+0xEC800000	0xEC8FFFFF	Hardware device tree (alt bank)	1MB
+0xEC020000	0xEC7FFFFF	Linux.uImage (alt bank)		7MB + 875KB
+0xEC000000	0xEC01FFFF	RCW (alt bank)			128KB
+0xEBF40000	0xEBFFFFFF	u-boot (alt bank)		768KB
+0xEBF20000	0xEBF3FFFF	u-boot env (alt bank)		128KB
+0xEBF00000	0xEBF1FFFF	FMAN ucode (alt bank)		128KB
+0xEBE00000	0xEBE3FFFF	PHY CS4315 firmware (alt bank)	256KB
+0xE9300000	0xEBEFFFFF	rootfs (current bank)		44MB
+0xE8800000	0xE88FFFFF	Hardware device tree (cur bank)	11MB + 512KB
+0xE8020000	0xE86FFFFF	Linux.uImage (current bank)	7MB + 875KB
+0xE8000000	0xE801FFFF	RCW (current bank)		128KB
+
+
+T2080PCIe-RDB Ethernet Port Map
+-------------------------------
+Label    In Uboot      In Linux     FMan Address   Comments    PHY
+ETH0     FM1@GTEC1     fm1-mac9     0xfe4f0000     10G SFP+   (CS4315)
+ETH1     FM1@GTEC2     fm1-mac10    0xfe4f2000     10G SFP+   (CS4315)
+ETH2     FM1@GTEC3     fm1-mac1     0xfe4e0000     10G Base-T (AQ1202)
+ETH3     FM1@GTEC4     fm1-mac2     0xfe4e2000     10G Base-T (AQ1202)
+ETH4     FM1@DTSEC3    fm1-mac3     0xfe4e4000     1G  RGMII  (RTL8211E)
+ETH5     FM1@DTSEC4    fm1-mac4     0xfe4e6000     1G  RGMII  (RTL8211E)
+
+
+T2080PCIe-RDB Default DIP-Switch setting
+----------------------------------------
+SW1[1:8] = '00010011'
+SW2[1:8] = '10111111'
+SW3[1:8] = '11100001'
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+   a. build NOR boot image
+	$ make T2080RDB
+   b. program u-boot.bin image to NOR flash
+	=> tftp 1000000 u-boot.bin
+	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+	set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+
+   Switching between default bank and alternate bank on NOR flash
+   To change boot source to vbank4:
+	via software:   run command 'cpld reset altbank' in u-boot.
+	via DIP-switch: set SW3[5:7] = '011'
+
+   To change boot source to vbank0:
+	via software:   run command 'cpld reset' in u-boot.
+	via DIP-Switch: set SW3[5:7] = '111'
+
+2. NAND Boot:
+   a. build PBL image for NAND boot
+	$ make T2080RDB_NAND_config
+	$ make u-boot.pbl
+   b. program u-boot.pbl to NAND flash
+	=> tftp 1000000 u-boot.pbl
+	=> nand erase 0 d0000
+	=> nand write 1000000 0 $filesize
+	set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
+
+3. SPI Boot:
+   a. build PBL image for SPI boot
+	$ make T2080RDB_SPIFLASH_config
+	$ make u-boot.pbl
+   b. program u-boot.pbl to SPI flash
+	=> tftp 1000000 u-boot.pbl
+	=> sf probe 0
+	=> sf erase 0 d0000
+	=> sf write 1000000 0 $filesize
+	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+   a. build PBL image for SD boot
+	$ make T2080RDB_SDCARD_config
+	$ make u-boot.pbl
+   b. program u-boot.pbl to TF card
+	=> tftp 1000000 u-boot.pbl
+	=> mmc write 1000000 8 1650
+	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+How to update the ucode of Cortina CS4315/CS4340 10G PHY
+--------------------------------------------------------
+=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
+=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080PCIe-RDB User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.

board/freescale/t208xrdb/cpld.c

+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Freescale T2080RDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+	u8 reg = CPLD_READ(flash_csr);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+	CPLD_WRITE(flash_csr, reg);
+	CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+	u8 reg = CPLD_READ(flash_csr);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+	CPLD_WRITE(flash_csr, reg);
+	CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else
+			cpld_set_defbank();
+	} else {
+		rc = cmd_usage(cmdtp);
+	}
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset: reset to default bank\n"
+	"cpld reset altbank: reset to alternate bank\n"
+);

board/freescale/t208xrdb/cpld.h

+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPLD register set of T2080RDB board-specific.
+ */
+struct cpld_data {
+	u8 chip_id1;		/* 0x00 - Chip ID1 register */
+	u8 chip_id2;		/* 0x01 - Chip ID2 register */
+	u8 hw_ver;		/* 0x02 - Hardware Revision Register */
+	u8 sw_ver;		/* 0x03 - Software Revision register */
+	u8 res0[12];		/* 0x04 - 0x0F - not used */
+	u8 reset_ctl;		/* 0x10 - Reset control Register */
+	u8 flash_csr;		/* 0x11 - Flash control and status register */
+	u8 thermal_csr;		/* 0x12 - Thermal control and status register */
+	u8 led_csr;		/* 0x13 - LED control and status register */
+	u8 sfp_csr;		/* 0x14 - SFP+ control and status register */
+	u8 misc_csr;		/* 0x15 - Misc control and status register */
+	u8 boot_or;		/* 0x16 - Boot config override register */
+	u8 boot_cfg1;		/* 0x17 - Boot configuration register 1 */
+	u8 boot_cfg2;		/* 0x18 - Boot configuration register 2 */
+} cpld_data_t;
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)  \
+	cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK		0x3F
+#define CPLD_BANK_SEL_MASK	0x07
+#define CPLD_BANK_OVERRIDE	0x40
+#define CPLD_LBMAP_ALTBANK	0x43 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK	0x47 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_RESET	0xFF
+#define CPLD_LBMAP_SHIFT	0x03
+#define CPLD_BOOT_SEL		0x80

board/freescale/t208xrdb/ddr.c

+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}

board/freescale/t208xrdb/ddr.h

+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
+	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
+	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+#endif

board/freescale/t208xrdb/eth_t208xrdb.c

+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+	int i, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	struct mii_dev *dev;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+	switch (srds_s1) {
+	case 0x66:
+	case 0x6b:
+		fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
+		fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
+		fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
+		break;
+	default:
+		printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
+		       srds_s1);
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_RGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	return;
+}

board/freescale/t208xrdb/law.c

+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/t208xrdb/pci.c

+/*
+ * Copyright 2007-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}

board/freescale/t208xrdb/t2080_pbi.cfg

+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000

board/freescale/t208xrdb/t2080_rcw.cfg

+#PBL preamble and RCW header for T2080RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x66_0x16
+#Core/DDR: 1533Mhz/1600MT/s
+120c0017 15000000 00000000 00000000
+66160002 00008400 ec104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004

board/freescale/t208xrdb/t208xrdb.c

+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include "t208xrdb.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	struct cpu_type *cpu = gd->arch.cpu;
+	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+
+	printf("Board: %sRDB, ", cpu->name);
+	printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
+	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+#ifdef CONFIG_SDCARD
+	puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+	puts("SPI\n");
+#else
+	u8 reg;
+
+	reg = CPLD_READ(flash_csr);
+
+	if (reg & CPLD_BOOT_SEL) {
+		puts("NAND\n");
+	} else {
+		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+		printf("NOR vBank%d\n", ~reg & 0x7);
+	}
+#endif
+
+	puts("SERDES Reference Clocks:\n");
+	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}

board/freescale/t208xrdb/t208xrdb.h

+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif

board/freescale/t208xrdb/tlb.c

+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 1, 0x80000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+
+	/* *I*G* - PCIe 2, 0xa0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 3, 0xb0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+	/* *I*G* - PCIe 4, 0xc0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+#if defined(CONFIG_SYS_RAMBOOT)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);

boards.cfg

@@ -983,6 +983,11 @@ Active  powerpc     mpc85xx        -           freescale       t208xqds
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH     T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_NAND         T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SRIO_PCIE_BOOT      T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB              T208xRDB:PPC_T2080
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SDCARD       T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SPIFLASH     T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND         T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SRIO_PCIE_BOOT  T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS                             T4240QDS:PPC_T4160                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SDCARD                      T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SPIFLASH                    T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -

include/configs/T1040QDS.h

@@ -375,7 +375,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
@@ -401,6 +401,25 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
+/* Video */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
@@ -426,6 +445,11 @@ unsigned long get_board_ddr_clk(void);
 
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
+#define I2C_MUX_CH_DIU		0xC
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR         0x38
+#define CONFIG_SYS_I2C_DVI_ADDR         0x75
 
 /*
  * RTC configuration
@@ -703,6 +727,7 @@ unsigned long get_board_ddr_clk(void);
 	"bank_intlv=cs0_cs1;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
+	"video-mode=fslfb:1024x768-32@60,monitor=dvi\0"		\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\

include/configs/T1040RDB.h

@@ -147,7 +147,7 @@
 
 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING

include/configs/T1042RDB_PI.h

@@ -147,7 +147,7 @@
 
 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING

include/configs/T208xQDS.h

@@ -242,7 +242,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 

include/fsl_usb.h

@@ -52,13 +52,32 @@ struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
+
+#define INC_DCNT_THRESHOLD_25MV        (0 << 4)
+#define INC_DCNT_THRESHOLD_50MV        (1 << 4)
+#define DEC_DCNT_THRESHOLD_25MV        (2 << 4)
+#define DEC_DCNT_THRESHOLD_50MV        (3 << 4)
 #else
 struct ccsr_usb_phy {
-	u8	res0[0x18];
+	u32     config1;
+	u32     config2;
+	u32     config3;
+	u32     config4;
+	u32     config5;
+	u32     status1;
 	u32	usb_enable_override;
 	u8	res[0xe4];
 };
-#define	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE	1
+#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
+#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
 #endif
 
 #endif /*_ASM_FSL_USB_H_ */