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体验新版 GitCode,发现更多精彩内容 >>
提交
1c64692d
编写于
4月 26, 2019
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-socfpga
上级
7d994067
bf068c76
变更
36
隐藏空白更改
内联
并排
Showing
36 changed file
with
104 addition
and
288 deletion
+104
-288
MAINTAINERS
MAINTAINERS
+1
-0
arch/arm/Kconfig
arch/arm/Kconfig
+2
-0
arch/arm/mach-socfpga/Kconfig
arch/arm/mach-socfpga/Kconfig
+23
-0
arch/arm/mach-socfpga/mailbox_s10.c
arch/arm/mach-socfpga/mailbox_s10.c
+2
-2
board/ebv/socrates/qts/iocsr_config.h
board/ebv/socrates/qts/iocsr_config.h
+1
-1
board/samtec/vining_fpga/socfpga.c
board/samtec/vining_fpga/socfpga.c
+1
-8
cmd/Kconfig
cmd/Kconfig
+0
-1
cmd/eeprom.c
cmd/eeprom.c
+15
-8
configs/socfpga_arria10_defconfig
configs/socfpga_arria10_defconfig
+0
-6
configs/socfpga_arria5_defconfig
configs/socfpga_arria5_defconfig
+0
-10
configs/socfpga_cyclone5_defconfig
configs/socfpga_cyclone5_defconfig
+0
-10
configs/socfpga_dbm_soc1_defconfig
configs/socfpga_dbm_soc1_defconfig
+0
-10
configs/socfpga_de0_nano_soc_defconfig
configs/socfpga_de0_nano_soc_defconfig
+0
-10
configs/socfpga_de10_nano_defconfig
configs/socfpga_de10_nano_defconfig
+0
-10
configs/socfpga_de1_soc_defconfig
configs/socfpga_de1_soc_defconfig
+0
-10
configs/socfpga_is1_defconfig
configs/socfpga_is1_defconfig
+0
-8
configs/socfpga_sockit_defconfig
configs/socfpga_sockit_defconfig
+0
-10
configs/socfpga_socrates_defconfig
configs/socfpga_socrates_defconfig
+2
-10
configs/socfpga_sr1500_defconfig
configs/socfpga_sr1500_defconfig
+0
-10
configs/socfpga_stratix10_defconfig
configs/socfpga_stratix10_defconfig
+0
-2
configs/socfpga_vining_fpga_defconfig
configs/socfpga_vining_fpga_defconfig
+7
-11
doc/git-mailrc
doc/git-mailrc
+2
-1
drivers/i2c/designware_i2c.c
drivers/i2c/designware_i2c.c
+14
-6
drivers/rtc/m41t62.c
drivers/rtc/m41t62.c
+11
-0
include/configs/socfpga_arria10_socdk.h
include/configs/socfpga_arria10_socdk.h
+0
-6
include/configs/socfpga_arria5_socdk.h
include/configs/socfpga_arria5_socdk.h
+0
-2
include/configs/socfpga_common.h
include/configs/socfpga_common.h
+23
-93
include/configs/socfpga_cyclone5_socdk.h
include/configs/socfpga_cyclone5_socdk.h
+0
-2
include/configs/socfpga_de0_nano_soc.h
include/configs/socfpga_de0_nano_soc.h
+0
-2
include/configs/socfpga_de10_nano.h
include/configs/socfpga_de10_nano.h
+0
-2
include/configs/socfpga_de1_soc.h
include/configs/socfpga_de1_soc.h
+0
-2
include/configs/socfpga_is1.h
include/configs/socfpga_is1.h
+0
-2
include/configs/socfpga_sockit.h
include/configs/socfpga_sockit.h
+0
-2
include/configs/socfpga_socrates.h
include/configs/socfpga_socrates.h
+0
-2
include/configs/socfpga_sr1500.h
include/configs/socfpga_sr1500.h
+0
-11
include/configs/socfpga_vining_fpga.h
include/configs/socfpga_vining_fpga.h
+0
-18
未找到文件。
MAINTAINERS
浏览文件 @
1c64692d
...
...
@@ -90,6 +90,7 @@ F: cmd/arm/
ARM ALTERA SOCFPGA
M: Marek Vasut <marex@denx.de>
M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
S: Maintainted
T: git git://git.denx.de/u-boot-socfpga.git
F: arch/arm/mach-socfpga/
...
...
arch/arm/Kconfig
浏览文件 @
1c64692d
...
...
@@ -839,6 +839,8 @@ config ARCH_SOCFPGA
imply DM_SPI
imply DM_SPI_FLASH
imply FAT_WRITE
imply SPL
imply SPL_DM
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC_SUPPORT
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
...
...
arch/arm/mach-socfpga/Kconfig
浏览文件 @
1c64692d
if ARCH_SOCFPGA
config NR_DRAM_BANKS
default 1
config SPL_STACK_R_ADDR
default 0x00800000 if TARGET_SOCFPGA_GEN5
config SPL_SYS_MALLOC_F_LEN
default 0x800 if TARGET_SOCFPGA_GEN5
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2
config SYS_MALLOC_F_LEN
default 0x2000 if TARGET_SOCFPGA_ARRIA10
default 0x2000 if TARGET_SOCFPGA_GEN5
config SYS_TEXT_BASE
default 0x01000040 if TARGET_SOCFPGA_ARRIA10
default 0x01000040 if TARGET_SOCFPGA_GEN5
config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
...
...
@@ -21,6 +38,8 @@ config TARGET_SOCFPGA_ARRIA10
select SYSCON
select SPL_SYSCON if SPL
select ETH_DESIGNWARE_SOCFPGA
imply FPGA_SOCFPGA
imply USE_TINY_PRINTF
config TARGET_SOCFPGA_CYCLONE5
bool
...
...
@@ -29,6 +48,10 @@ config TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_GEN5
bool
select ALTERA_SDRAM
imply FPGA_SOCFPGA
imply SPL_STACK_R
imply SPL_SYS_MALLOC_SIMPLE
imply USE_TINY_PRINTF
config TARGET_SOCFPGA_STRATIX10
bool
...
...
arch/arm/mach-socfpga/mailbox_s10.c
浏览文件 @
1c64692d
...
...
@@ -55,11 +55,11 @@ static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
cout
=
MBOX_READL
(
MBOX_COUT
)
%
MBOX_CMD_BUFFER_SIZE
;
/* if command buffer is full or not enough free space
* to fit the data
* to fit the data
. Note, len is in u32 unit.
*/
if
(((
cin
+
1
)
%
MBOX_CMD_BUFFER_SIZE
)
==
cout
||
((
MBOX_CMD_BUFFER_SIZE
-
cin
+
cout
-
1
)
%
MBOX_CMD_BUFFER_SIZE
)
<
len
)
MBOX_CMD_BUFFER_SIZE
)
<
(
len
+
1
)
)
return
-
ENOMEM
;
/* write header to circular buffer */
...
...
board/ebv/socrates/qts/iocsr_config.h
浏览文件 @
1c64692d
...
...
@@ -108,7 +108,7 @@ const unsigned long iocsr_scan_chain2_table[] = {
0x00018004
,
0x06001209
,
0x00004000
,
0x200
0
2412
,
0x200
4
2412
,
0x00904800
,
0x00000030
,
0x80000000
,
...
...
board/samtec/vining_fpga/socfpga.c
浏览文件 @
1c64692d
...
...
@@ -52,14 +52,7 @@ int misc_init_r(void)
u32
serial
;
int
ret
;
/* EEPROM is at bus 0. */
ret
=
i2c_set_bus_num
(
0
);
if
(
ret
)
{
puts
(
"Cannot select EEPROM I2C bus.
\n
"
);
return
0
;
}
/* EEPROM is at address 0x50. */
/* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */
ret
=
eeprom_read
(
0x50
,
0
,
data
,
sizeof
(
data
));
if
(
ret
)
{
puts
(
"Cannot read I2C EEPROM.
\n
"
);
...
...
cmd/Kconfig
浏览文件 @
1c64692d
...
...
@@ -466,7 +466,6 @@ config CRC32_VERIFY
config CMD_EEPROM
bool "eeprom - EEPROM subsystem"
depends on !DM_I2C || DM_I2C_COMPAT
help
(deprecated, needs conversion to driver model)
Provides commands to read and write EEPROM (Electrically Erasable
...
...
cmd/eeprom.c
浏览文件 @
1c64692d
...
...
@@ -59,6 +59,10 @@
#endif
#endif
#if defined(CONFIG_DM_I2C)
int
eeprom_i2c_bus
;
#endif
__weak
int
eeprom_write_enable
(
unsigned
dev_addr
,
int
state
)
{
return
0
;
...
...
@@ -67,7 +71,9 @@ __weak int eeprom_write_enable(unsigned dev_addr, int state)
void
eeprom_init
(
int
bus
)
{
/* I2C EEPROM */
#if defined(CONFIG_SYS_I2C)
#if defined(CONFIG_DM_I2C)
eeprom_i2c_bus
=
bus
;
#elif defined(CONFIG_SYS_I2C)
if
(
bus
>=
0
)
i2c_set_bus_num
(
bus
);
i2c_init
(
CONFIG_SYS_I2C_SPEED
,
CONFIG_SYS_I2C_SLAVE
);
...
...
@@ -124,14 +130,14 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen,
{
int
ret
=
0
;
#if defined(CONFIG_DM_I2C)
&& defined(CONFIG_SYS_I2C_EEPROM_BUS)
#if defined(CONFIG_DM_I2C)
struct
udevice
*
dev
;
ret
=
i2c_get_chip_for_busnum
(
CONFIG_SYS_I2C_EEPROM_BUS
,
addr
[
0
],
ret
=
i2c_get_chip_for_busnum
(
eeprom_i2c_bus
,
addr
[
0
],
alen
-
1
,
&
dev
);
if
(
ret
)
{
printf
(
"%s: Cannot find udev for a bus %d
\n
"
,
__func__
,
CONFIG_SYS_I2C_EEPROM_BUS
);
eeprom_i2c_bus
);
return
CMD_RET_FAILURE
;
}
...
...
@@ -141,15 +147,12 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen,
ret
=
dm_i2c_write
(
dev
,
offset
,
buffer
,
len
);
#else
/* Non DM I2C support - will be removed */
#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
i2c_set_bus_num
(
CONFIG_SYS_I2C_EEPROM_BUS
);
#endif
if
(
read
)
ret
=
i2c_read
(
addr
[
0
],
offset
,
alen
-
1
,
buffer
,
len
);
else
ret
=
i2c_write
(
addr
[
0
],
offset
,
alen
-
1
,
buffer
,
len
);
#endif
/* CONFIG_DM_I2C
&& CONFIG_SYS_I2C_EEPROM_BUS
*/
#endif
/* CONFIG_DM_I2C */
if
(
ret
)
ret
=
CMD_RET_FAILURE
;
...
...
@@ -164,6 +167,10 @@ static int eeprom_rw(unsigned dev_addr, unsigned offset, uchar *buffer,
int
rcode
=
0
;
uchar
addr
[
3
];
#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
eeprom_init
(
CONFIG_SYS_I2C_EEPROM_BUS
);
#endif
while
(
offset
<
end
)
{
alen
=
eeprom_addr
(
dev_addr
,
offset
,
addr
);
...
...
configs/socfpga_arria10_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
CONFIG_SPL=y
CONFIG_IDENT_STRING="socfpga_arria10"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
# CONFIG_USE_BOOTCOMMAND is not set
...
...
@@ -28,9 +25,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
...
...
@@ -42,4 +37,3 @@ CONFIG_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DESIGNWARE_APB_TIMER=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_arria5_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
...
...
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
...
...
@@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
@@ -72,4 +63,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_cyclone5_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
...
...
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
...
...
@@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
@@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_dbm_soc1_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
...
...
@@ -15,8 +10,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
...
...
@@ -41,9 +34,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
@@ -67,4 +58,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_de0_nano_soc_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
...
...
@@ -17,8 +12,6 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
...
...
@@ -40,9 +33,7 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
@@ -68,4 +59,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_de10_nano_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
...
...
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de10_nano.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
...
...
@@ -36,9 +29,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
@@ -64,4 +55,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_de1_soc_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
...
...
@@ -17,8 +12,6 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
...
...
@@ -36,8 +29,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
@@ -55,5 +46,4 @@ CONFIG_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USE_TINY_PRINTF=y
# CONFIG_EFI_LOADER is not set
configs/socfpga_is1_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_IS1=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
...
...
@@ -17,7 +12,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
...
...
@@ -36,11 +30,9 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
configs/socfpga_sockit_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
...
...
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
...
...
@@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
@@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_socrates_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
...
...
@@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
...
...
@@ -40,10 +33,8 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
@@ -61,6 +52,8 @@ CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_DM_RESET=y
CONFIG_DM_RTC=y
CONFIG_RTC_M41T62=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
...
...
@@ -73,4 +66,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_sr1500_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SR1500=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
...
...
@@ -18,8 +13,6 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
...
...
@@ -40,11 +33,9 @@ CONFIG_CMD_UBI=y
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
...
...
@@ -64,4 +55,3 @@ CONFIG_MII=y
CONFIG_DM_RESET=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_USE_TINY_PRINTF=y
configs/socfpga_stratix10_defconfig
浏览文件 @
1c64692d
...
...
@@ -3,7 +3,6 @@ CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x1000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_SPL=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
CONFIG_NR_DRAM_BANKS=2
...
...
@@ -30,7 +29,6 @@ CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
...
...
configs/socfpga_vining_fpga_defconfig
浏览文件 @
1c64692d
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x01000040
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
...
...
@@ -19,12 +14,10 @@ CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
...
...
@@ -45,14 +38,13 @@ CONFIG_CMD_UBI=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
...
...
@@ -64,6 +56,11 @@ CONFIG_LED_STATUS_BIT2=54
CONFIG_LED_STATUS3=y
CONFIG_LED_STATUS_BIT3=65
CONFIG_LED_STATUS_CMD=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
...
...
@@ -90,4 +87,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
doc/git-mailrc
浏览文件 @
1c64692d
...
...
@@ -37,6 +37,7 @@ alias monstr Michal Simek <monstr@monstr.eu>
alias prom Minkyu Kang <mk7.kang@samsung.com>
alias ptomsich Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
alias sbabic Stefano Babic <sbabic@denx.de>
alias simongoldschmidt Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
alias sjg Simon Glass <sjg@chromium.org>
alias smcnutt Scott McNutt <smcnutt@psyent.com>
alias stroese Stefan Roese <sr@denx.de>
...
...
@@ -62,7 +63,7 @@ alias s3c samsung
alias s5pc samsung
alias samsung uboot, prom
alias snapdragon uboot, mateusz
alias socfpga uboot, marex, dinh
alias socfpga uboot, marex, dinh
, simongoldschmidt
alias sunxi uboot, jagan, maxime
alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
...
...
drivers/i2c/designware_i2c.c
浏览文件 @
1c64692d
...
...
@@ -34,7 +34,7 @@ static struct dw_scl_sda_cfg byt_config = {
struct
dw_i2c
{
struct
i2c_regs
*
regs
;
struct
dw_scl_sda_cfg
*
scl_sda_cfg
;
struct
reset_ctl
reset_ctl
;
struct
reset_ctl
_bulk
resets
;
};
#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
...
...
@@ -562,16 +562,22 @@ static int designware_i2c_probe(struct udevice *bus)
priv
->
regs
=
(
struct
i2c_regs
*
)
devfdt_get_addr_ptr
(
bus
);
}
ret
=
reset_get_b
y_name
(
bus
,
"i2c"
,
&
priv
->
reset_ctl
);
ret
=
reset_get_b
ulk
(
bus
,
&
priv
->
resets
);
if
(
ret
)
pr_info
(
"reset_get_by_name() failed: %d
\n
"
,
ret
);
if
(
&
priv
->
reset_ctl
)
reset_deassert
(
&
priv
->
reset_ctl
);
dev_warn
(
bus
,
"Can't get reset: %d
\n
"
,
ret
);
else
reset_deassert_bulk
(
&
priv
->
resets
);
return
__dw_i2c_init
(
priv
->
regs
,
0
,
0
);
}
static
int
designware_i2c_remove
(
struct
udevice
*
dev
)
{
struct
dw_i2c
*
priv
=
dev_get_priv
(
dev
);
return
reset_release_bulk
(
&
priv
->
resets
);
}
static
int
designware_i2c_bind
(
struct
udevice
*
dev
)
{
static
int
num_cards
;
...
...
@@ -613,6 +619,8 @@ U_BOOT_DRIVER(i2c_designware) = {
.
bind
=
designware_i2c_bind
,
.
probe
=
designware_i2c_probe
,
.
priv_auto_alloc_size
=
sizeof
(
struct
dw_i2c
),
.
remove
=
designware_i2c_remove
,
.
flags
=
DM_FLAG_OS_PREPARE
,
.
ops
=
&
designware_i2c_ops
,
};
...
...
drivers/rtc/m41t62.c
浏览文件 @
1c64692d
...
...
@@ -155,6 +155,15 @@ static int m41t62_rtc_reset(struct udevice *dev)
return
ret
;
}
/*
* Make sure HT bit is cleared. This bit is set on entering battery backup
* mode, so do this before the first read access.
*/
static
int
m41t62_rtc_probe
(
struct
udevice
*
dev
)
{
return
m41t62_rtc_reset
(
dev
);
}
static
const
struct
rtc_ops
m41t62_rtc_ops
=
{
.
get
=
m41t62_rtc_get
,
.
set
=
m41t62_rtc_set
,
...
...
@@ -163,6 +172,7 @@ static const struct rtc_ops m41t62_rtc_ops = {
static
const
struct
udevice_id
m41t62_rtc_ids
[]
=
{
{
.
compatible
=
"st,m41t62"
},
{
.
compatible
=
"st,m41t82"
},
{
.
compatible
=
"microcrystal,rv4162"
},
{
}
};
...
...
@@ -172,6 +182,7 @@ U_BOOT_DRIVER(rtc_m41t62) = {
.
id
=
UCLASS_RTC
,
.
of_match
=
m41t62_rtc_ids
,
.
ops
=
&
m41t62_rtc_ops
,
.
probe
=
&
m41t62_rtc_probe
,
};
#else
/* NON DM RTC code - will be removed */
...
...
include/configs/socfpga_arria10_socdk.h
浏览文件 @
1c64692d
...
...
@@ -19,12 +19,6 @@
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000
/* Ethernet on SoC (EMAC) */
/*
* U-Boot environment configurations
*/
/*
* Serial / UART configurations
*/
...
...
include/configs/socfpga_arria5_socdk.h
浏览文件 @
1c64692d
...
...
@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
...
...
include/configs/socfpga_common.h
浏览文件 @
1c64692d
...
...
@@ -10,8 +10,6 @@
*/
#define CONFIG_CLOCKS
#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
#define CONFIG_TIMESTAMP
/* Print image info with timestamp */
/*
...
...
@@ -26,7 +24,13 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
/* 256KB */
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
#endif
#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)
#endif
/*
...
...
@@ -38,12 +42,23 @@
#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
(CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)))
#define CONFIG_S
YS_INIT_SP_ADDR
CONFIG_SYS_BOOTCOUNT_ADDR
#define CONFIG_S
PL_STACK
CONFIG_SYS_BOOTCOUNT_ADDR
#else
#define CONFIG_S
YS_INIT_SP_ADDR
\
#define CONFIG_S
PL_STACK
\
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#endif
/*
* U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
* phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
* in U-Boot pre-reloc is higher than in SPL.
*/
#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
#else
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
...
...
@@ -55,29 +70,12 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#ifndef CONFIG_SYS_HOSTNAME
#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
#endif
/*
* Cache
*/
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
* EPCS/EPCQx1 Serial Flash Controller
*/
#ifdef CONFIG_ALTERA_SPI
/*
* The base address is configurable in QSys, each board must specify the
* base address based on it's particular FPGA configuration. Please note
* that the address here is incremented by 0x400 from the Base address
* selected in QSys, since the SPI registers are at offset +0x400.
* #define CONFIG_SYS_SPI_BASE 0xff240400
*/
#endif
/*
* Ethernet on SoC (EMAC)
*/
...
...
@@ -132,32 +130,6 @@
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
/*
* I2C support
*/
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
/* Using standard mode which the speed up to 100Kb/s */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SPEED1 100000
#define CONFIG_SYS_I2C_SPEED2 100000
#define CONFIG_SYS_I2C_SPEED3 100000
/* Address of device when used as slave */
#define CONFIG_SYS_I2C_SLAVE 0x02
#define CONFIG_SYS_I2C_SLAVE1 0x02
#define CONFIG_SYS_I2C_SLAVE2 0x02
#define CONFIG_SYS_I2C_SLAVE3 0x02
#ifndef __ASSEMBLY__
/* Clock supplied to I2C controller in unit of MHz */
unsigned
int
cm_get_l4_sp_clk_hz
(
void
);
#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
#endif
#endif
/* CONFIG_DM_I2C */
/*
* QSPI support
*/
...
...
@@ -171,15 +143,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
#endif
/*
* Designware SPI support
*/
/*
* Serial Driver
*/
#define CONFIG_SYS_NS16550_SERIAL
/*
* USB
*/
...
...
@@ -215,20 +178,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#endif
/*
* mtd partitioning for serial NOR flash
*
* device nor0 <ff705000.spi.0>, # parts = 6
* #: name size offset mask_flags
* 0: u-boot 0x00100000 0x00000000 0
* 1: env1 0x00040000 0x00100000 0
* 2: env2 0x00040000 0x00140000 0
* 3: UBI 0x03e80000 0x00180000 0
* 4: boot 0x00e80000 0x00180000 0
* 5: rootfs 0x01000000 0x01000000 0
*
*/
/*
* SPL
*
...
...
@@ -236,9 +185,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
*
* 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down)
* 0xFFFF_yyyy ......
Malloc are
a
* 0xFFFF_zzzz ......
Global Dat
a
* 0xFFFF_FF
00
...... End of SRAM
* 0xFFFF_yyyy ......
Global Dat
a
* 0xFFFF_zzzz ......
Malloc are
a
* 0xFFFF_FF
FF
...... End of SRAM
*
* SRAM Memory layout for Arria 10:
* 0xFFE0_0000 ...... Start of SRAM (bottom)
...
...
@@ -252,16 +201,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#endif
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_START
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE + \
CONFIG_SYS_INIT_RAM_ADDR)
#endif
#endif
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
...
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@@ -292,15 +231,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#endif
/*
* Stack setup
*/
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
#endif
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
...
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include/configs/socfpga_cyclone5_socdk.h
浏览文件 @
1c64692d
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@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
...
...
include/configs/socfpga_de0_nano_soc.h
浏览文件 @
1c64692d
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@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
...
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include/configs/socfpga_de10_nano.h
浏览文件 @
1c64692d
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@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
...
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include/configs/socfpga_de1_soc.h
浏览文件 @
1c64692d
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@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
...
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include/configs/socfpga_is1.h
浏览文件 @
1c64692d
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@@ -19,8 +19,6 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_ARP_TIMEOUT 500UL
/* PHY */
#endif
/* The rest of the configuration is shared */
...
...
include/configs/socfpga_sockit.h
浏览文件 @
1c64692d
...
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@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
...
...
include/configs/socfpga_socrates.h
浏览文件 @
1c64692d
...
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@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
...
...
include/configs/socfpga_sr1500.h
浏览文件 @
1c64692d
...
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@@ -19,8 +19,6 @@
/* The PHY is autodetected, so no MII PHY address is needed here */
#define PHY_ANEG_TIMEOUT 8000
/* Environment */
/* Enable SPI NOR flash reset, needed for SPI booting */
#define CONFIG_SPI_N25Q256A_RESET
...
...
@@ -36,15 +34,6 @@
#define CONFIG_ENV_OFFSET 0x000e0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
/*
* The QSPI NOR flash layout on SR1500:
*
* 0000.0000 - 0003.ffff: SPL (4 times)
* 0004.0000 - 000d.ffff: U-Boot
* 000e.0000 - 000e.ffff: env1
* 000f.0000 - 000f.ffff: env2
*/
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
...
...
include/configs/socfpga_vining_fpga.h
浏览文件 @
1c64692d
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@@ -16,27 +16,9 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* I2C EEPROM */
#ifdef CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 0
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
#endif
/*
* Status LEDs:
* 0 ... Top Green
* 1 ... Top Red
* 2 ... Bottom Green
* 3 ... Bottom Red
*/
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_BOOTP_SEND_HOSTNAME
/* PHY */
#endif
/* Extra Environment */
...
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