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提交 1730edf7 编写于 作者: W Wolfgang Denk
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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

上级 5ea67393 b2815f79
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Showing with 2782 addition and 5648 deletion
board/amcc/acadia/memory.c
浏览文件 @ 1730edf7
......@@ -33,14 +33,6 @@
extern void board_pll_init_f(void);
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
......@@ -116,10 +108,3 @@ long int initdram(int board_type)
return (CFG_MBYTES_RAM << 20);
}
#ifndef CONFIG_NAND_SPL
int testdram(void)
{
return (0);
}
#endif
board/amcc/bamboo/bamboo.c
浏览文件 @ 1730edf7
......@@ -466,73 +466,6 @@ long int initdram (int board_type)
#endif
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n, *p32, ctr;
const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
mtmsr(0);
for (k = 0; k < CFG_MBYTES_SDRAM*1024;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
/*
* Perform a sequence test to ensure that all
* memory locations are uniquely addressable
*/
ctr = 0;
p32 = 0;
while ((unsigned long)p32 != bend) {
if (0 == ((unsigned long)p32 & ((1<<20)-1)))
printf("Writing %3d MB\r", (unsigned long)p32 >> 20);
*p32++ = ctr++;
}
ctr = 0;
p32 = 0;
while ((unsigned long)p32 != bend) {
if (0 == ((unsigned long)p32 & ((1<<20)-1)))
printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
if (*p32 != ctr) {
printf("SDRAM test fails at: %08x\n", p32);
return 1;
}
ctr++;
p32++;
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
board/amcc/bubinga/bubinga.c
浏览文件 @ 1730edf7
......@@ -66,14 +66,6 @@ int checkboard(void)
return (0);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
/* -------------------------------------------------------------------------
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
......@@ -85,11 +77,3 @@ long int initdram(int board_type)
ret = spd_sdram();
return ret;
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("test: xxx MB - ok\n");
return (0);
}
board/amcc/canyonlands/canyonlands.c
浏览文件 @ 1730edf7
......@@ -211,44 +211,6 @@ long int initdram(int board_type)
}
#endif
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*
* pci_target_init
*
......
board/amcc/ebony/ebony.c
浏览文件 @ 1730edf7
......@@ -116,36 +116,6 @@ long int initdram(int board_type)
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
......
board/amcc/katmai/katmai.c
浏览文件 @ 1730edf7
......@@ -258,36 +258,6 @@ u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
board/amcc/kilauea/Makefile
浏览文件 @ 1730edf7
......@@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_pll.o memory.o
SOBJS = init.o
COBJS = $(BOARD).o cmd_pll.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
......
board/amcc/kilauea/init.S 已删除 100644 → 0
浏览文件 @ 5ea67393
/*
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Based on code provided from UDTech and AMCC
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#define mtsdram_as(reg, value) \
addi r4,0,reg ; \
mtdcr memcfga,r4 ; \
addis r4,0,value@h ; \
ori r4,r4,value@l ; \
mtdcr memcfgd,r4 ;
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
/*
* DDR2 setup
*/
/* Following the DDR Core Manual, here is the initialization */
/* Step 1 */
/* Step 2 */
/* Step 3 */
/* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
mtsdram_as(SDRAM_MB0CF, 0x00006701);
/* SET SDRAM_MB1CF - Not enabled */
mtsdram_as(SDRAM_MB1CF, 0x00000000);
/* SET SDRAM_MB2CF - Not enabled */
mtsdram_as(SDRAM_MB2CF, 0x00000000);
/* SET SDRAM_MB3CF - Not enabled */
mtsdram_as(SDRAM_MB3CF, 0x00000000);
/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
mtsdram_as(SDRAM_CLKTR, 0x80000000);
/* Refresh Time register (0x30) Refresh every 7.8125uS */
mtsdram_as(SDRAM_RTR, 0x06180000);
/* SDRAM_SDTR1 */
mtsdram_as(SDRAM_SDTR1, 0x80201000);
/* SDRAM_SDTR2 */
mtsdram_as(SDRAM_SDTR2, 0x32204232);
/* SDRAM_SDTR3 */
mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
mtsdram_as(SDRAM_MMODE, 0x00000442);
mtsdram_as(SDRAM_MEMODE, 0x00000404);
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
mtsdram_as(SDRAM_MCOPT1, 0x04322000);
/* NOP */
mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
/* precharge 3 DDR clock cycle */
mtsdram_as(SDRAM_INITPLR1, 0x81900400);
/* EMR2 twr = 2tck */
mtsdram_as(SDRAM_INITPLR2, 0x81020000);
/* EMR3 twr = 2tck */
mtsdram_as(SDRAM_INITPLR3, 0x81030000);
/* EMR DLL ENABLE twr = 2tck */
mtsdram_as(SDRAM_INITPLR4, 0x81010404);
/* MR w/ DLL reset
* Note: 5 is CL. May need to be changed
*/
mtsdram_as(SDRAM_INITPLR5, 0x81000542);
/* precharge 3 DDR clock cycle */
mtsdram_as(SDRAM_INITPLR6, 0x81900400);
/* Auto-refresh trfc = 26tck */
mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
/* Auto-refresh trfc = 26tck */
mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
/* Auto-refresh */
mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
/* Auto-refresh */
mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
mtsdram_as(SDRAM_INITPLR11, 0x81000442);
mtsdram_as(SDRAM_INITPLR12, 0x81010780);
mtsdram_as(SDRAM_INITPLR13, 0x81010400);
mtsdram_as(SDRAM_INITPLR14, 0x00000000);
mtsdram_as(SDRAM_INITPLR15, 0x00000000);
/* SET MCIF0_CODT Die Termination On */
mtsdram_as(SDRAM_CODT, 0x0080f837);
mtsdram_as(SDRAM_MODT0, 0x01800000);
mtsdram_as(SDRAM_MODT1, 0x00000000);
mtsdram_as(SDRAM_WRDTR, 0x00000000);
/* SDRAM0_MCOPT2 (0X21) Start initialization */
mtsdram_as(SDRAM_MCOPT2, 0x20000000);
/* Step 5 */
lis r3,0x1 /* 400000 = wait 100ms */
mtctr r3
pll_wait:
bdnz pll_wait
/* Step 6 */
/* SDRAM_DLCR */
mtsdram_as(SDRAM_DLCR, 0x030000a5);
/* SDRAM_RDCC */
mtsdram_as(SDRAM_RDCC, 0x40000000);
/* SDRAM_RQDC */
mtsdram_as(SDRAM_RQDC, 0x80000038);
/* SDRAM_RFDC */
mtsdram_as(SDRAM_RFDC, 0x00000209);
/* Enable memory controller */
mtsdram_as(SDRAM_MCOPT2, 0x28000000);
#endif /* #ifndef CONFIG_NAND_U_BOOT */
blr
board/amcc/kilauea/memory.c 已删除 100644 → 0
浏览文件 @ 5ea67393
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <i2c.h>
void sdram_init(void)
{
return;
}
long int initdram(int board_type)
{
return (CFG_MBYTES_SDRAM << 20);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
printf ("testdram\n");
#if defined (CONFIG_NAND_U_BOOT)
return 0;
#endif
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x00001000;
uint *p;
for (p = pstart; p < pend; p++) {
*p = 0xaaaaaaaa;
}
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test fails at: %08x\n", (uint) p);
#endif
return 1;
}
}
for (p = pstart; p < pend; p++) {
*p = 0x55555555;
}
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test fails at: %08x\n", (uint) p);
#endif
return 1;
}
}
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test passed!!!\n");
#endif
return 0;
}
#endif
board/amcc/luan/luan.c
浏览文件 @ 1730edf7
......@@ -125,50 +125,6 @@ u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
}
/*************************************************************************
* int testdram()
*
************************************************************************/
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *) 0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
board/amcc/makalu/Makefile
浏览文件 @ 1730edf7
......@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_pll.o memory.o
COBJS = $(BOARD).o cmd_pll.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
......
board/amcc/makalu/init.S
浏览文件 @ 1730edf7
/*
* Copyright (c) 2008 Nuovation System Designs, LLC
* Grant Erickson <gerickson@nuovations.com>
*
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Based on code provided from Senao and AMCC
* Originally based on code provided from Senao and AMCC
*
* See file CREDITS for list of people who contributed to this
* project.
......@@ -23,126 +26,6 @@
* MA 02111-1307 USA
*/
#include <config.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#define mtsdram_as(reg, value) \
addi r4,0,reg ; \
mtdcr memcfga,r4 ; \
addis r4,0,value@h ; \
ori r4,r4,value@l ; \
mtdcr memcfgd,r4 ;
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
/*
* DDR2 setup
*/
/* Following the DDR Core Manual, here is the initialization */
/* Step 1 */
/* Step 2 */
/* Step 3 */
/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
mtsdram_as(SDRAM_MB0CF, 0x00005201);
/* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
mtsdram_as(SDRAM_CLKTR,0x80000000);
/* Refresh Time register (0x30) Refresh every 7.8125uS */
mtsdram_as(SDRAM_RTR, 0x06180000);
/* SDRAM_SDTR1 */
mtsdram_as(SDRAM_SDTR1, 0x80201000);
/* SDRAM_SDTR2 */
mtsdram_as(SDRAM_SDTR2, 0x32204232);
/* SDRAM_SDTR3 */
mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
mtsdram_as(SDRAM_MMODE, 0x00000442);
mtsdram_as(SDRAM_MEMODE, 0x00000404);
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
mtsdram_as(SDRAM_MCOPT1, 0x04322000);
/* NOP */
mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
/* precharge 3 DDR clock cycle */
mtsdram_as(SDRAM_INITPLR1, 0x81900400);
/* EMR2 twr = 2tck */
mtsdram_as(SDRAM_INITPLR2, 0x81020000);
/* EMR3 twr = 2tck */
mtsdram_as(SDRAM_INITPLR3, 0x81030000);
/* EMR DLL ENABLE twr = 2tck */
mtsdram_as(SDRAM_INITPLR4, 0x81010404);
/* MR w/ DLL reset
* Note: 5 is CL. May need to be changed
*/
mtsdram_as(SDRAM_INITPLR5, 0x81000542);
/* precharge 3 DDR clock cycle */
mtsdram_as(SDRAM_INITPLR6, 0x81900400);
/* Auto-refresh trfc = 26tck */
mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
/* Auto-refresh trfc = 26tck */
mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
/* Auto-refresh */
mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
/* Auto-refresh */
mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
mtsdram_as(SDRAM_INITPLR11, 0x81000442);
mtsdram_as(SDRAM_INITPLR12, 0x81010780);
mtsdram_as(SDRAM_INITPLR13, 0x81010400);
mtsdram_as(SDRAM_INITPLR14, 0x00000000);
mtsdram_as(SDRAM_INITPLR15, 0x00000000);
/* SET MCIF0_CODT Die Termination On */
mtsdram_as(SDRAM_CODT, 0x0080f837);
mtsdram_as(SDRAM_MODT0, 0x01800000);
#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
mtsdram_as(SDRAM_MODT1, 0x00000000);
#endif
mtsdram_as(SDRAM_WRDTR, 0x00000000);
/* SDRAM0_MCOPT2 (0X21) Start initialization */
mtsdram_as(SDRAM_MCOPT2, 0x20000000);
/* Step 5 */
lis r3,0x1 /* 400000 = wait 100ms */
mtctr r3
pll_wait:
bdnz pll_wait
/* Step 6 */
/* SDRAM_DLCR */
mtsdram_as(SDRAM_DLCR, 0x030000a5);
/* SDRAM_RDCC */
mtsdram_as(SDRAM_RDCC, 0x40000000);
/* SDRAM_RQDC */
mtsdram_as(SDRAM_RQDC, 0x80000038);
/* SDRAM_RFDC */
mtsdram_as(SDRAM_RFDC, 0x00000209);
/* Enable memory controller */
mtsdram_as(SDRAM_MCOPT2, 0x28000000);
blr
board/amcc/makalu/memory.c 已删除 100644 → 0
浏览文件 @ 5ea67393
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
void sdram_init(void)
{
return;
}
long int initdram(int board_type)
{
/*
* Same as on Kilauea, Makalu generates exception 0x200
* (machine check) after trap_init() in board_init_f,
* when SDRAM is initialized here (late) and d-cache is
* used earlier as INIT_RAM.
* So for now, initialize DDR2 in init.S very early and
* also use it for INIT_RAM. Then this exception doesn't
* occur.
*/
#if 0
u32 val;
/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
mtsdram(SDRAM_MB0CF, 0x00005201);
/* SET SDRAM_MB1CF - Not enabled */
mtsdram(SDRAM_MB1CF, 0x00000000);
/* SET SDRAM_MB2CF - Not enabled */
mtsdram(SDRAM_MB2CF, 0x00000000);
/* SET SDRAM_MB3CF - Not enabled */
mtsdram(SDRAM_MB3CF, 0x00000000);
/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
mtsdram(SDRAM_CLKTR, 0x80000000);
/* Refresh Time register (0x30) Refresh every 7.8125uS */
mtsdram(SDRAM_RTR, 0x06180000);
/* SDRAM_SDTR1 */
mtsdram(SDRAM_SDTR1, 0x80201000);
/* SDRAM_SDTR2 */
mtsdram(SDRAM_SDTR2, 0x32204232);
/* SDRAM_SDTR3 */
mtsdram(SDRAM_SDTR3, 0x080b0d1a);
mtsdram(SDRAM_MMODE, 0x00000442);
mtsdram(SDRAM_MEMODE, 0x00000404);
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
mtsdram(SDRAM_MCOPT1, 0x04322000);
/* NOP */
mtsdram(SDRAM_INITPLR0, 0xa8380000);
/* precharge 3 DDR clock cycle */
mtsdram(SDRAM_INITPLR1, 0x81900400);
/* EMR2 twr = 2tck */
mtsdram(SDRAM_INITPLR2, 0x81020000);
/* EMR3 twr = 2tck */
mtsdram(SDRAM_INITPLR3, 0x81030000);
/* EMR DLL ENABLE twr = 2tck */
mtsdram(SDRAM_INITPLR4, 0x81010404);
/* MR w/ DLL reset
* Note: 5 is CL. May need to be changed
*/
mtsdram(SDRAM_INITPLR5, 0x81000542);
/* precharge 3 DDR clock cycle */
mtsdram(SDRAM_INITPLR6, 0x81900400);
/* Auto-refresh trfc = 26tck */
mtsdram(SDRAM_INITPLR7, 0x8D080000);
/* Auto-refresh trfc = 26tck */
mtsdram(SDRAM_INITPLR8, 0x8D080000);
/* Auto-refresh */
mtsdram(SDRAM_INITPLR9, 0x8D080000);
/* Auto-refresh */
mtsdram(SDRAM_INITPLR10, 0x8D080000);
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
mtsdram(SDRAM_INITPLR11, 0x81000442);
mtsdram(SDRAM_INITPLR12, 0x81010780);
mtsdram(SDRAM_INITPLR13, 0x81010400);
mtsdram(SDRAM_INITPLR14, 0x00000000);
mtsdram(SDRAM_INITPLR15, 0x00000000);
/* SET MCIF0_CODT Die Termination On */
mtsdram(SDRAM_CODT, 0x0080f837);
mtsdram(SDRAM_MODT0, 0x01800000);
mtsdram(SDRAM_MODT1, 0x00000000);
mtsdram(SDRAM_WRDTR, 0x00000000);
/* SDRAM0_MCOPT2 (0X21) Start initialization */
mtsdram(SDRAM_MCOPT2, 0x20000000);
/* Step 5 */
do {
mfsdram(SDRAM_MCSTAT, val);
} while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP);
/* Step 6 */
/* SDRAM_DLCR */
mtsdram(SDRAM_DLCR, 0x030000a5);
/* SDRAM_RDCC */
mtsdram(SDRAM_RDCC, 0x40000000);
/* SDRAM_RQDC */
mtsdram(SDRAM_RQDC, 0x80000038);
/* SDRAM_RFDC */
mtsdram(SDRAM_RFDC, 0x00000209);
/* Enable memory controller */
mfsdram(SDRAM_MCOPT2, val);
val |= SDRAM_MCOPT2_DCEN_ENABLE;
mtsdram(SDRAM_MCOPT2, val);
#endif
return (CFG_MBYTES_SDRAM << 20);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
printf ("testdram\n");
#if defined (CONFIG_NAND_U_BOOT)
return 0;
#endif
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x00001000;
uint *p;
for (p = pstart; p < pend; p++) {
*p = 0xaaaaaaaa;
}
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test fails at: %08x\n", (uint) p);
#endif
return 1;
}
}
for (p = pstart; p < pend; p++) {
*p = 0x55555555;
}
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test fails at: %08x\n", (uint) p);
#endif
return 1;
}
}
#if !defined (CONFIG_NAND_SPL)
printf ("SDRAM test passed!!!\n");
#endif
return 0;
}
#endif
board/amcc/ocotea/ocotea.c
浏览文件 @ 1730edf7
......@@ -214,36 +214,6 @@ long int initdram (int board_type)
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
......
board/amcc/sequoia/config.mk
浏览文件 @ 1730edf7
......@@ -28,6 +28,10 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0xFFFA0000
#
# When defining CONFIG_VIDEO, TEXT_BASE needs to be 0xFFF80000
# TEXT_BASE = 0xFFF80000
#
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
......
board/amcc/sequoia/sequoia.c
浏览文件 @ 1730edf7
......@@ -329,44 +329,6 @@ int checkboard(void)
return (0);
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_MBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
/*
* Assign interrupts to PCI devices.
......
board/amcc/taihu/taihu.c
浏览文件 @ 1730edf7
......@@ -200,45 +200,3 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* CONFIG_PCI */
#ifdef CFG_DRAM_TEST
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
unsigned long msr;
unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
msr = mfmsr();
mtmsr(msr & ~(MSR_EE));
for (k = 0; k < total_kbytes ;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0)
printf("%3d MB\r", k / 1024);
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
mtmsr(msr);
return 0;
}
#endif /* CFG_DRAM_TEST */
board/amcc/taishan/taishan.c
浏览文件 @ 1730edf7
......@@ -196,36 +196,6 @@ int checkboard (void)
return (0);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x04000000;
uint *pend = (uint *) 0x0fc00000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
board/amcc/walnut/walnut.c
浏览文件 @ 1730edf7
......@@ -85,14 +85,6 @@ int checkboard(void)
return (0);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
/*
* initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
......@@ -101,11 +93,3 @@ long int initdram(int board_type)
{
return spd_sdram();
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("test: xxx MB - ok\n");
return (0);
}
board/amcc/yosemite/yosemite.c
浏览文件 @ 1730edf7
......@@ -200,7 +200,7 @@ int checkboard(void)
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
* initdram -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
......@@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
*tr1_value = (first_good + last_bad) / 2;
}
void sdram_init(void)
long int initdram(int board)
{
register uint reg;
int tr1_bank1, tr1_bank2;
......@@ -327,57 +327,11 @@ void sdram_init(void)
sdram_tr1_set(0x00000000, &tr1_bank1);
sdram_tr1_set(0x08000000, &tr1_bank2);
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
}
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram(int board)
{
sdram_init();
return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
board/amcc/yucca/yucca.c
浏览文件 @ 1730edf7
......@@ -586,36 +586,6 @@ u32 ddr_clktr(u32 default_val) {
return default_val;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
board/amirix/ap1000/init.S
浏览文件 @ 1730edf7
......@@ -28,7 +28,3 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
.globl sdram_init
sdram_init:
blr
board/cray/L1/init.S
浏览文件 @ 1730edf7
......@@ -134,14 +134,3 @@ ext_bus_cntlr_init:
mtdcr ebccfgd,r4
blr
/*----------------------------------------------------------------------------- */
/* Function: sdram_init */
/* Description: Configures SDRAM memory banks. */
/* NOTE: for CrayL1 we have ECC memory, so enable it. */
/*....now done in C in L1.c:init_sdram for readability. */
/*----------------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr
board/csb272/csb272.c
浏览文件 @ 1730edf7
......@@ -27,6 +27,8 @@
#include <miiphy.h>
#include <ppc4xx_enet.h>
void sdram_init(void);
/*
* Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
*
......@@ -124,6 +126,13 @@ long initdram (int board_type)
ulong bank_size;
ulong tmp;
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
......
board/csb472/csb472.c
浏览文件 @ 1730edf7
......@@ -27,6 +27,8 @@
#include <miiphy.h>
#include <ppc4xx_enet.h>
void sdram_init(void);
/*
* board_early_init_f: do early board initialization
*
......@@ -92,6 +94,13 @@ long initdram (int board_type)
ulong bank_size;
ulong tmp;
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
......
board/eric/eric.c
浏览文件 @ 1730edf7
......@@ -31,6 +31,8 @@
#define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
#define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */
void sdram_init(void);
int board_early_init_f (void)
{
......@@ -127,6 +129,12 @@ long int initdram (int board_type)
int TotalSize;
#endif
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
#ifdef CONFIG_ERIC
/*
......
board/esd/ar405/ar405.c
浏览文件 @ 1730edf7
......@@ -190,28 +190,6 @@ int checkboard (void)
return 0;
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
unsigned long val;
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
#if 1 /* test-only: some internal test routines... */
/*
......
board/esd/canbt/canbt.c
浏览文件 @ 1730edf7
......@@ -181,22 +181,3 @@ int checkboard (void)
return 0;
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
return (16 * 1024 * 1024);
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
board/exbitgen/exbitgen.c
浏览文件 @ 1730edf7
......@@ -3,6 +3,8 @@
#include <common.h>
#include "exbitgen.h"
void sdram_init(void);
/* ************************************************************************ */
int board_early_init_f (void)
/* ------------------------------------------------------------------------ --
......@@ -83,6 +85,13 @@ long int initdram (int board_type)
ulong bank_size;
ulong tmp;
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
......
board/g2000/g2000.c
浏览文件 @ 1730edf7
......@@ -149,41 +149,6 @@ long int initdram (int board_type)
}
#if 1 /* test-only */
void sdram_init(void)
{
init_sdram_static_settings();
}
#endif
#if 0 /* test-only */
long int initdram (int board_type)
{
unsigned long val;
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
#endif
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
......
board/jse/init.S
浏览文件 @ 1730edf7
......@@ -93,13 +93,3 @@ ext_bus_cntlr_init:
mtdcr ebccfgd,r4
blr
/*----------------------------------------------------------------------- */
/* Function: sdram_init */
/* Description: This function is called by cpu/ppc4xx/start.S code */
/* to get the SDRAM initialized. */
/*----------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr
board/lwmon5/lwmon5.c
浏览文件 @ 1730edf7
......@@ -275,44 +275,6 @@ int checkboard(void)
return (0);
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_MBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
board/ml2/init.S
浏览文件 @ 1730edf7
......@@ -28,7 +28,3 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
.globl sdram_init
sdram_init:
blr
board/mpl/mip405/init.S
浏览文件 @ 1730edf7
......@@ -178,19 +178,6 @@ ext_bus_cntlr_init:
nop /* pass2 DCR errata #8 */
blr
/*-----------------------------------------------------------------------------
* Function: sdram_init
* Description: Configures the internal SRAM memory. and setup the
* Stackpointer in it.
*----------------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr
#if defined(CONFIG_BOOT_PCI)
.section .bootpg,"ax"
.globl _start_pci
......
board/mpl/pip405/init.S
浏览文件 @ 1730edf7
......@@ -175,19 +175,6 @@
nop /* pass2 DCR errata #8 */
blr
/*-----------------------------------------------------------------------------
* Function: sdram_init
* Description: Configures the internal SRAM memory. and setup the
* Stackpointer in it.
*----------------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr
#if defined(CONFIG_BOOT_PCI)
.section .bootpg,"ax"
.globl _start_pci
......
board/netstal/hcu4/hcu4.c
浏览文件 @ 1730edf7
......@@ -120,15 +120,6 @@ void hcu_led_set(u32 value)
out_be32((u32 *)GPIO0_OR, tmp);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram or initdram
* used for HCUx
*/
void sdram_init(void)
{
return;
}
/*
* hcu_get_slot
*/
......
board/netstal/hcu5/sdram.c
浏览文件 @ 1730edf7
......@@ -40,28 +40,6 @@
void hcu_led_set(u32 value);
void dcbz_area(u32 start_address, u32 num_bytes);
#define DDR_DCR_BASE 0x10
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
#define DDR0_01_INT_MASK_MASK 0x000000FF
#define DDR0_00_INT_ACK_ALL 0x7F000000
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
#define DDR0_22 0x16
/* ECC */
#define DDR0_22_CTRL_RAW_MASK 0x03000000
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define ECC_RAM 0x03267F0B
#define NO_ECC_RAM 0x00267F0B
......@@ -111,11 +89,11 @@ static int wait_for_dlllock(void)
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_17);
mtdcr(memcfga, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
val = mfdcr(memcfgd);
if ((val & DDR0_17_DLLLOCKREG_MASK) ==
DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */
......
board/netstal/mcu25/mcu25.c
浏览文件 @ 1730edf7
......@@ -127,15 +127,6 @@ void hcu_led_set(u32 value)
out_be16((u16 *)MCU25_LED_REGISTER_ADDRESS, value);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram or initdram
* used for HCUx
*/
void sdram_init(void)
{
return;
}
/*
* hcu_get_slot
*/
......
board/pcs440ep/pcs440ep.c
浏览文件 @ 1730edf7
......@@ -553,44 +553,6 @@ long int initdram (int board_type)
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
board/prodrive/alpr/alpr.c
浏览文件 @ 1730edf7
......@@ -132,36 +132,6 @@ int checkboard (void)
return (0);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
board/w7o/w7o.c
浏览文件 @ 1730edf7
......@@ -31,6 +31,7 @@
#include <watchdog.h>
unsigned long get_dram_size (void);
void sdram_init(void);
/*
* Macros to transform values
......@@ -153,6 +154,13 @@ int checkboard (void)
long int initdram (int board_type)
{
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
return get_dram_size ();
}
......
board/xilinx/ml300/init.S
浏览文件 @ 1730edf7
......@@ -42,7 +42,3 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
.globl sdram_init
sdram_init:
blr
board/zeus/zeus.c
浏览文件 @ 1730edf7
......@@ -213,51 +213,6 @@ long int initdram (int board_type)
return detect_sdram_size();
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
unsigned long msr;
unsigned long total_kbytes;
total_kbytes = detect_sdram_size();
msr = mfmsr();
mtmsr(msr & ~(MSR_EE));
for (k = 0; k < total_kbytes ;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
mtmsr(msr);
return 0;
}
#endif
static int default_env_var(char *buf, char *var)
{
char *ptr;
......
cpu/ppc4xx/44x_spd_ddr.c
浏览文件 @ 1730edf7
......@@ -53,6 +53,8 @@
#include <ppc4xx.h>
#include <asm/mmu.h>
#include "ecc.h"
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR))
......@@ -79,157 +81,6 @@ void __spd_ddr_init_hang (void)
}
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
/*-----------------------------------------------------------------------------
| Memory Controller Options 0
+-----------------------------------------------------------------------------*/
#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
/*-----------------------------------------------------------------------------
| Memory Controller Options 1
+-----------------------------------------------------------------------------*/
#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
/*-----------------------------------------------------------------------------+
| SDRAM DEVPOT Options
+-----------------------------------------------------------------------------*/
#define SDRAM_DEVOPT_DLL 0x80000000
#define SDRAM_DEVOPT_DS 0x40000000
/*-----------------------------------------------------------------------------+
| SDRAM MCSTS Options
+-----------------------------------------------------------------------------*/
#define SDRAM_MCSTS_MRSC 0x80000000
#define SDRAM_MCSTS_SRMS 0x40000000
#define SDRAM_MCSTS_CIS 0x20000000
/*-----------------------------------------------------------------------------
| SDRAM Refresh Timer Register
+-----------------------------------------------------------------------------*/
#define SDRAM_RTR_RINT_MASK 0xFFFF0000
#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
/*-----------------------------------------------------------------------------+
| SDRAM UABus Base Address Reg
+-----------------------------------------------------------------------------*/
#define SDRAM_UABBA_UBBA_MASK 0x0000000F
/*-----------------------------------------------------------------------------+
| Memory Bank 0-7 configuration
+-----------------------------------------------------------------------------*/
#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
/*-----------------------------------------------------------------------------+
| SDRAM TR0 Options
+-----------------------------------------------------------------------------*/
#define SDRAM_TR0_SDWR_MASK 0x80000000
#define SDRAM_TR0_SDWR_2_CLK 0x00000000
#define SDRAM_TR0_SDWR_3_CLK 0x80000000
#define SDRAM_TR0_SDWD_MASK 0x40000000
#define SDRAM_TR0_SDWD_0_CLK 0x00000000
#define SDRAM_TR0_SDWD_1_CLK 0x40000000
#define SDRAM_TR0_SDCL_MASK 0x01800000
#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
#define SDRAM_TR0_SDPA_MASK 0x000C0000
#define SDRAM_TR0_SDPA_2_CLK 0x00040000
#define SDRAM_TR0_SDPA_3_CLK 0x00080000
#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
#define SDRAM_TR0_SDCP_MASK 0x00030000
#define SDRAM_TR0_SDCP_2_CLK 0x00000000
#define SDRAM_TR0_SDCP_3_CLK 0x00010000
#define SDRAM_TR0_SDCP_4_CLK 0x00020000
#define SDRAM_TR0_SDCP_5_CLK 0x00030000
#define SDRAM_TR0_SDLD_MASK 0x0000C000
#define SDRAM_TR0_SDLD_1_CLK 0x00000000
#define SDRAM_TR0_SDLD_2_CLK 0x00004000
#define SDRAM_TR0_SDRA_MASK 0x0000001C
#define SDRAM_TR0_SDRA_6_CLK 0x00000000
#define SDRAM_TR0_SDRA_7_CLK 0x00000004
#define SDRAM_TR0_SDRA_8_CLK 0x00000008
#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
#define SDRAM_TR0_SDRA_10_CLK 0x00000010
#define SDRAM_TR0_SDRA_11_CLK 0x00000014
#define SDRAM_TR0_SDRA_12_CLK 0x00000018
#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
#define SDRAM_TR0_SDRD_MASK 0x00000003
#define SDRAM_TR0_SDRD_2_CLK 0x00000001
#define SDRAM_TR0_SDRD_3_CLK 0x00000002
#define SDRAM_TR0_SDRD_4_CLK 0x00000003
/*-----------------------------------------------------------------------------+
| SDRAM TR1 Options
+-----------------------------------------------------------------------------*/
#define SDRAM_TR1_RDSS_MASK 0xC0000000
#define SDRAM_TR1_RDSS_TR0 0x00000000
#define SDRAM_TR1_RDSS_TR1 0x40000000
#define SDRAM_TR1_RDSS_TR2 0x80000000
#define SDRAM_TR1_RDSS_TR3 0xC0000000
#define SDRAM_TR1_RDSL_MASK 0x00C00000
#define SDRAM_TR1_RDSL_STAGE1 0x00000000
#define SDRAM_TR1_RDSL_STAGE2 0x00400000
#define SDRAM_TR1_RDSL_STAGE3 0x00800000
#define SDRAM_TR1_RDCD_MASK 0x00000800
#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
#define SDRAM_TR1_RDCT_MASK 0x000001FF
#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
#define SDRAM_TR1_RDCT_MIN 0x00000000
#define SDRAM_TR1_RDCT_MAX 0x000001FF
/*-----------------------------------------------------------------------------+
| SDRAM WDDCTR Options
+-----------------------------------------------------------------------------*/
#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
/*-----------------------------------------------------------------------------+
| SDRAM CLKTR Options
+-----------------------------------------------------------------------------*/
#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
/*-----------------------------------------------------------------------------+
| SDRAM DLYCAL Options
+-----------------------------------------------------------------------------*/
#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
/*-----------------------------------------------------------------------------+
| General Definition
+-----------------------------------------------------------------------------*/
......@@ -296,10 +147,6 @@ static void program_tr0(unsigned long *dimm_populated,
unsigned long num_dimm_banks);
static void program_tr1(void);
#ifdef CONFIG_DDR_ECC
static void program_ecc(unsigned long num_bytes);
#endif
static unsigned long program_bxcr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
......@@ -418,7 +265,7 @@ long int spd_sdram(void) {
/*
* If ecc is enabled, initialize the parity bits.
*/
program_ecc(total_size);
ecc_init(CFG_SDRAM_BASE, total_size);
#endif
return total_size;
......@@ -1402,45 +1249,4 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
return(bank_base_addr);
}
#ifdef CONFIG_DDR_ECC
static void program_ecc(unsigned long num_bytes)
{
unsigned long bank_base_addr;
unsigned long current_address;
unsigned long end_address;
unsigned long address_increment;
unsigned long cfg0;
/*
* get Memory Controller Options 0 data
*/
mfsdram(mem_cfg0, cfg0);
/*
* reset the bank_base address
*/
bank_base_addr = CFG_SDRAM_BASE;
if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN);
if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32)
address_increment = 4;
else
address_increment = 8;
current_address = (unsigned long)(bank_base_addr);
end_address = (unsigned long)(bank_base_addr) + num_bytes;
while (current_address < end_address) {
*((unsigned long*)current_address) = 0x00000000;
current_address += address_increment;
}
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
SDRAM_CFG0_MCHK_CHK);
}
}
#endif /* CONFIG_DDR_ECC */
#endif /* CONFIG_SPD_EEPROM */
cpu/ppc4xx/44x_spd_ddr2.c
浏览文件 @ 1730edf7
......@@ -3,9 +3,12 @@
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those currently are:
*
* 405: 405EX
* 405: 405EX(r)
* 440/460: 440SP/440SPe/460EX/460GT
*
* Copyright (c) 2008 Nuovation System Designs, LLC
* Grant Erickson <gerickson@nuovations.com>
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
......@@ -45,6 +48,8 @@
#include <asm/mmu.h>
#include <asm/cache.h>
#include "ecc.h"
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT))
......@@ -3064,9 +3069,127 @@ static void ppc440sp_sdram_register_dump(void)
dcr_data = mfdcr(SDRAM_R3BAS);
printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
}
#else
#else /* !defined(DEBUG) */
static void ppc440sp_sdram_register_dump(void)
{
}
#endif
#endif /* CONFIG_SPD_EEPROM */
#endif /* defined(DEBUG) */
#elif defined(CONFIG_405EX)
/*-----------------------------------------------------------------------------
* Function: initdram
* Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
* banks. The configuration is performed using static, compile-
* time parameters.
*---------------------------------------------------------------------------*/
long initdram(int board_type)
{
/*
* Only run this SDRAM init code once. For NAND booting
* targets like Kilauea, we call initdram() early from the
* 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
* Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
* which calls initdram() again. This time the controller
* mustn't be reconfigured again since we're already running
* from SDRAM.
*/
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;
/* Set Memory Bank Configuration Registers */
mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
/* Set Memory Clock Timing Register */
mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
/* Set Refresh Time Register */
mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
/* Set SDRAM Timing Registers */
mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
/* Set Mode and Extended Mode Registers */
mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
/* Set Memory Controller Options 1 Register */
mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
/* Set Manual Initialization Control Registers */
mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
/* Set On-Die Termination Registers */
mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
/* Set Write Timing Register */
mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
/*
* Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
* SDRAM0_MCOPT2[IPTR] = 1
*/
mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
SDRAM_MCOPT2_IPTR_EXECUTE));
/*
* Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
* completion of initialization.
*/
do {
mfsdram(SDRAM_MCSTAT, val);
} while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
/* Set Delay Control Registers */
mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
/*
* Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
*/
mfsdram(SDRAM_MCOPT2, val);
mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
#if defined(CONFIG_DDR_ECC)
ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
return (CFG_MBYTES_SDRAM << 20);
}
#endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */
cpu/ppc4xx/4xx_uart.c
浏览文件 @ 1730edf7
......@@ -98,14 +98,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define UDIV_SUBTRACT 0
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPe) || \
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UART2_SDR sdr_uart2
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UART3_SDR sdr_uart3
#endif
......
cpu/ppc4xx/Makefile
浏览文件 @ 1730edf7
......@@ -45,6 +45,7 @@ COBJS += cpu.o
COBJS += cpu_init.o
COBJS += denali_data_eye.o
COBJS += denali_spd_ddr2.o
COBJS += ecc.o
COBJS += fdt.o
COBJS += gpio.o
COBJS += i2c.o
......
cpu/ppc4xx/cpu_init.c
浏览文件 @ 1730edf7
......@@ -32,73 +32,6 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CFG_INIT_DCACHE_CS
# if (CFG_INIT_DCACHE_CS == 0)
# define PBxAP pb0ap
# define PBxCR pb0cr
# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
# define PBxAP_VAL CFG_EBC_PB0AP
# define PBxCR_VAL CFG_EBC_PB0CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 1)
# define PBxAP pb1ap
# define PBxCR pb1cr
# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
# define PBxAP_VAL CFG_EBC_PB1AP
# define PBxCR_VAL CFG_EBC_PB1CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 2)
# define PBxAP pb2ap
# define PBxCR pb2cr
# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
# define PBxAP_VAL CFG_EBC_PB2AP
# define PBxCR_VAL CFG_EBC_PB2CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 3)
# define PBxAP pb3ap
# define PBxCR pb3cr
# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
# define PBxAP_VAL CFG_EBC_PB3AP
# define PBxCR_VAL CFG_EBC_PB3CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 4)
# define PBxAP pb4ap
# define PBxCR pb4cr
# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
# define PBxAP_VAL CFG_EBC_PB4AP
# define PBxCR_VAL CFG_EBC_PB4CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 5)
# define PBxAP pb5ap
# define PBxCR pb5cr
# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
# define PBxAP_VAL CFG_EBC_PB5AP
# define PBxCR_VAL CFG_EBC_PB5CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 6)
# define PBxAP pb6ap
# define PBxCR pb6cr
# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
# define PBxAP_VAL CFG_EBC_PB6AP
# define PBxCR_VAL CFG_EBC_PB6CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 7)
# define PBxAP pb7ap
# define PBxCR pb7cr
# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
# define PBxAP_VAL CFG_EBC_PB7AP
# define PBxCR_VAL CFG_EBC_PB7CR
# endif
# endif
#endif /* CFG_INIT_DCACHE_CS */
#ifndef CFG_PLL_RECONFIG
#define CFG_PLL_RECONFIG 0
#endif
......@@ -353,24 +286,6 @@ int cpu_init_r (void)
uint pvr = get_pvr();
#endif
#ifdef CFG_INIT_DCACHE_CS
/*
* Flush and invalidate dcache, then disable CS for temporary stack.
* Afterwards, this CS can be used for other purposes
*/
dcache_disable(); /* flush and invalidate dcache */
mtebc(PBxAP, 0);
mtebc(PBxCR, 0); /* disable CS for temporary stack */
#if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
/*
* Write new value into CS register
*/
mtebc(PBxAP, PBxAP_VAL);
mtebc(PBxCR, PBxCR_VAL);
#endif
#endif /* CFG_INIT_DCACHE_CS */
/*
* Write Ethernetaddress into on-chip register
*/
......
cpu/ppc4xx/ecc.c 0 → 100644
浏览文件 @ 1730edf7
/*
* Copyright (c) 2008 Nuovation System Designs, LLC
* Grant Erickson <gerickson@nuovations.com>
*
* (C) Copyright 2005-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2002
* Jun Gu, Artesyn Technology, jung@artesyncp.com
*
* (C) Copyright 2001
* Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will abe useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Description:
* This file implements generic DRAM ECC initialization for
* PowerPC processors using a SDRAM DDR/DDR2 controller,
* including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
* 460EX/GT.
*/
#include <common.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/processor.h>
#include <asm/io.h>
#include "ecc.h"
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
/*
* void ecc_init()
*
* Description:
* This routine initializes a range of DRAM ECC memory with known
* data and enables ECC checking.
*
* TO DO:
* - Improve performance by utilizing cache.
* - Further generalize to make usable by other 4xx variants (e.g.
* 440EPx, et al).
*
* Input(s):
* start - A pointer to the start of memory covered by ECC requiring
* initialization.
* size - The size, in bytes, of the memory covered by ECC requiring
* initialization.
*
* Output(s):
* start - A pointer to the start of memory covered by ECC with
* CFG_ECC_PATTERN written to all locations and ECC data
* primed.
*
* Returns:
* N/A
*/
void ecc_init(unsigned long * const start, unsigned long size)
{
const unsigned long pattern = CFG_ECC_PATTERN;
unsigned long * const end = (unsigned long * const)((long)start + size);
unsigned long * current = start;
unsigned long mcopt1;
long increment;
if (start >= end)
return;
mfsdram(SDRAM_ECC_CFG, mcopt1);
/* Enable ECC generation without checking or reporting */
mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
SDRAM_ECC_CFG_MCHK_GEN));
increment = sizeof(u32);
#if defined(CONFIG_440)
/*
* Look at the geometry of SDRAM (data width) to determine whether we
* can skip words when writing.
*/
if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32)
increment = sizeof(u64);
#endif /* defined(CONFIG_440) */
while (current < end) {
*current = pattern;
current = (unsigned long *)((long)current + increment);
}
/* Wait until the writes are finished. */
sync();
/* Enable ECC generation with checking and no reporting */
mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
SDRAM_ECC_CFG_MCHK_CHK));
}
#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
cpu/ppc4xx/ecc.h 0 → 100644
浏览文件 @ 1730edf7
/*
* Copyright (c) 2008 Nuovation System Designs, LLC
* Grant Erickson <gerickson@nuovations.com>
*
* Copyright (c) 2007 DENX Software Engineering, GmbH
* Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will abe useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Description:
* This file implements ECC initialization for PowerPC processors
* using the SDRAM DDR2 controller, including the 405EX(r),
* 440SP(E), 460EX and 460GT.
*
*/
#ifndef _ECC_H_
#define _ECC_H_
#if !defined(CFG_ECC_PATTERN)
#define CFG_ECC_PATTERN 0x00000000
#endif /* !defined(CFG_ECC_PATTERN) */
/*
* Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
* compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
* we need to make some processor dependant defines used later on by the
* driver.
*/
/* For 440GP/GX/EP/GR */
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
#define SDRAM_ECC_CFG SDRAM_CFG0
#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK
#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN
#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK
#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK
#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32
#endif
/* For 405EX/440SP/SPe/460EX/GT */
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
#define SDRAM_ECC_CFG SDRAM_MCOPT1
#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK
#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN
#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK
#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK
#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32
#endif
extern void ecc_init(unsigned long * const start, unsigned long size);
#endif /* _ECC_H_ */
cpu/ppc4xx/sdram.c
浏览文件 @ 1730edf7
......@@ -31,6 +31,7 @@
#include <ppc4xx.h>
#include <asm/processor.h>
#include "sdram.h"
#include "ecc.h"
#ifdef CONFIG_SDRAM_BANK0
......@@ -163,7 +164,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
/*
* Autodetect onboard SDRAM on 405 platforms
*/
void sdram_init(void)
long int initdram(int board_type)
{
ulong speed;
ulong sdtr1;
......@@ -231,9 +232,15 @@ void sdram_init(void)
mtsdram(mem_mcopt1, 0);
}
#endif
return;
/*
* OK, size detected -> all done
*/
return mb0cf[i].size;
}
}
return 0;
}
#else /* CONFIG_440 */
......@@ -332,49 +339,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
*tr1_value = (first_good + last_bad) / 2;
}
#ifdef CONFIG_SDRAM_ECC
static void ecc_init(ulong start, ulong size)
{
ulong current_addr; /* current byte address */
ulong end_addr; /* end of memory region */
ulong addr_inc; /* address skip between writes */
ulong cfg0_reg; /* for restoring ECC state */
/*
* TODO: Enable dcache before running this test (speedup)
*/
mfsdram(mem_cfg0, cfg0_reg);
mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN);
/*
* look at geometry of SDRAM (data width) to determine whether we
* can skip words when writing
*/
if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32)
addr_inc = 4;
else
addr_inc = 8;
current_addr = start;
end_addr = start + size;
while (current_addr < end_addr) {
*((ulong *)current_addr) = 0x00000000;
current_addr += addr_inc;
}
/*
* TODO: Flush dcache and disable it again
*/
/*
* Enable ecc checking and parity errors
*/
mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK);
}
#endif
/*
* Autodetect onboard DDR SDRAM on 440 platforms
*
......
cpu/ppc4xx/start.S
浏览文件 @ 1730edf7
......@@ -3,6 +3,8 @@
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
* Copyright (c) 2008 Nuovation System Designs, LLC
* Grant Erickson <gerickson@nuovations.com>
*
* See file CREDITS for list of people who contributed to this
* project.
......@@ -79,34 +81,100 @@
# if (CFG_INIT_DCACHE_CS == 0)
# define PBxAP pb0ap
# define PBxCR pb0cr
# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
# define PBxAP_VAL CFG_EBC_PB0AP
# define PBxCR_VAL CFG_EBC_PB0CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 1)
# define PBxAP pb1ap
# define PBxCR pb1cr
# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
# define PBxAP_VAL CFG_EBC_PB1AP
# define PBxCR_VAL CFG_EBC_PB1CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 2)
# define PBxAP pb2ap
# define PBxCR pb2cr
# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
# define PBxAP_VAL CFG_EBC_PB2AP
# define PBxCR_VAL CFG_EBC_PB2CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 3)
# define PBxAP pb3ap
# define PBxCR pb3cr
# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
# define PBxAP_VAL CFG_EBC_PB3AP
# define PBxCR_VAL CFG_EBC_PB3CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 4)
# define PBxAP pb4ap
# define PBxCR pb4cr
# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
# define PBxAP_VAL CFG_EBC_PB4AP
# define PBxCR_VAL CFG_EBC_PB4CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 5)
# define PBxAP pb5ap
# define PBxCR pb5cr
# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
# define PBxAP_VAL CFG_EBC_PB5AP
# define PBxCR_VAL CFG_EBC_PB5CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 6)
# define PBxAP pb6ap
# define PBxCR pb6cr
# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
# define PBxAP_VAL CFG_EBC_PB6AP
# define PBxCR_VAL CFG_EBC_PB6CR
# endif
# endif
# if (CFG_INIT_DCACHE_CS == 7)
# define PBxAP pb7ap
# define PBxCR pb7cr
# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
# define PBxAP_VAL CFG_EBC_PB7AP
# define PBxCR_VAL CFG_EBC_PB7CR
# endif
# endif
# ifndef PBxAP_VAL
# define PBxAP_VAL 0
# endif
# ifndef PBxCR_VAL
# define PBxCR_VAL 0
# endif
/*
* Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB
* used as temporary stack pointer for the primordial stack
*/
# ifndef CFG_INIT_DCACHE_PBxAR
# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
EBC_BXAP_TWT_ENCODE(7) | \
EBC_BXAP_BCE_DISABLE | \
EBC_BXAP_BCT_2TRANS | \
EBC_BXAP_CSN_ENCODE(0) | \
EBC_BXAP_OEN_ENCODE(0) | \
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(2) | \
EBC_BXAP_RE_DISABLED | \
EBC_BXAP_SOR_NONDELAYED | \
EBC_BXAP_BEM_WRITEONLY | \
EBC_BXAP_PEN_DISABLED)
# endif /* CFG_INIT_DCACHE_PBxAR */
# ifndef CFG_INIT_DCACHE_PBxCR
# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \
EBC_BXCR_BS_64MB | \
EBC_BXCR_BU_RW | \
EBC_BXCR_BW_16BIT)
# endif /* CFG_INIT_DCACHE_PBxCR */
# ifndef CFG_INIT_RAM_PATTERN
# define CFG_INIT_RAM_PATTERN 0xDEADDEAD
# endif
#endif /* CFG_INIT_DCACHE_CS */
......@@ -114,6 +182,27 @@
#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
#endif
/*
* Unless otherwise overriden, enable two 128MB cachable instruction regions
* at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering
* NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions.
*/
#if !defined(CFG_FLASH_BASE)
/* If not already defined, set it to the "last" 128MByte region */
# define CFG_FLASH_BASE 0xf8000000
#endif
#if !defined(CFG_ICACHE_SACR_VALUE)
# define CFG_ICACHE_SACR_VALUE \
(PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \
PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \
PPC_128MB_SACR_VALUE(CFG_FLASH_BASE))
#endif /* !defined(CFG_ICACHE_SACR_VALUE) */
#if !defined(CFG_DCACHE_SACR_VALUE)
# define CFG_DCACHE_SACR_VALUE \
(0x00000000)
#endif /* !defined(CFG_DCACHE_SACR_VALUE) */
#define function_prolog(func_name) .text; \
.align 2; \
.globl func_name; \
......@@ -128,7 +217,6 @@
.extern ext_bus_cntlr_init
.extern sdram_init
#ifdef CONFIG_NAND_U_BOOT
.extern reconfig_tlb0
#endif
......@@ -401,97 +489,6 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
/* Continue from 'normal' start */
/*----------------------------------------------------------------*/
2:
#if defined(CONFIG_NAND_SPL)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
/*
* Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
*/
lis r2,0x7fff
ori r2,r2,0xffff
mfdcr r1,isram0_dpc
and r1,r1,r2 /* Disable parity check */
mtdcr isram0_dpc,r1
mfdcr r1,isram0_pmeg
and r1,r1,r2 /* Disable pwr mgmt */
mtdcr isram0_pmeg,r1
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
lis r1,0x4000 /* BAS = 8000_0000 */
ori r1,r1,0x4580 /* 16k */
mtdcr isram0_sb0cr,r1
#endif
#endif
#if defined(CONFIG_440EP)
/*
* On 440EP with no internal SRAM, we setup SDRAM very early
* and copy the NAND_SPL to SDRAM and jump to it
*/
/* Clear Dcache to use as RAM */
addis r3,r0,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
addis r4,r0,CFG_INIT_RAM_END@h
ori r4,r4,CFG_INIT_RAM_END@l
rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31
beq ..d_ran3
addi r5,r5,0x0001
..d_ran3:
mtctr r5
..d_ag3:
dcbz r0,r3
addi r3,r3,32
bdnz ..d_ag3
/*----------------------------------------------------------------*/
/* Setup the stack in internal SRAM */
/*----------------------------------------------------------------*/
lis r1,CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET@l
li r0,0
stwu r0,-4(r1)
stwu r0,-4(r1) /* Terminate call chain */
stwu r1,-8(r1) /* Save back chain and move SP */
lis r0,RESET_VECTOR@h /* Address of reset vector */
ori r0,r0, RESET_VECTOR@l
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
sync
bl early_sdram_init
sync
#endif /* CONFIG_440EP */
/*
* Copy SPL from cache into internal SRAM
*/
li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
mtctr r4
lis r2,CFG_NAND_BOOT_SPL_SRC@h
ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
lis r3,CFG_NAND_BOOT_SPL_DST@h
ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
spl_loop:
lwzu r4,4(r2)
stwu r4,4(r3)
bdnz spl_loop
/*
* Jump to code in RAM
*/
bl 00f
00: mflr r10
lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
sub r10,r10,r3
addi r10,r10,28
mtlr r10
blr
start_ram:
sync
isync
#endif /* CONFIG_NAND_SPL */
bl 3f
b _start
......@@ -746,7 +743,7 @@ _start:
stw r0,+12(r1) /* Save return addr (underflow vect) */
#ifdef CONFIG_NAND_SPL
bl nand_boot /* will not return */
bl nand_boot_common /* will not return */
#else
GET_GOT
......@@ -840,16 +837,16 @@ _start:
/* make sure above stores all comlete before going on */
sync
/*----------------------------------------------------------------------- */
/* Enable two 128MB cachable regions. */
/*----------------------------------------------------------------------- */
addis r1,r0,0xc000
addi r1,r1,0x0001
mticcr r1 /* instruction cache */
/* Set-up icache cacheability. */
lis r1, CFG_ICACHE_SACR_VALUE@h
ori r1, r1, CFG_ICACHE_SACR_VALUE@l
mticcr r1
isync
addis r1,r0,0x0000
addi r1,r1,0x0000
mtdccr r1 /* data cache */
/* Set-up dcache cacheability. */
lis r1, CFG_DCACHE_SACR_VALUE@h
ori r1, r1, CFG_DCACHE_SACR_VALUE@l
mtdccr r1
addis r1,r0,CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
......@@ -892,39 +889,33 @@ _start:
/* dbsr is cleared by setting bits to 1) */
mtdbsr r4 /* clear/reset the dbsr */
/*----------------------------------------------------------------------- */
/* Invalidate I and D caches. Enable I cache for defined memory regions */
/* to speed things up. Leave the D cache disabled for now. It will be */
/* enabled/left disabled later based on user selected menu options. */
/* Be aware that the I cache may be disabled later based on the menu */
/* options as well. See miscLib/main.c. */
/*----------------------------------------------------------------------- */
/* Invalidate the i- and d-caches. */
bl invalidate_icache
bl invalidate_dcache
/*----------------------------------------------------------------------- */
/* Enable two 128MB cachable regions. */
/*----------------------------------------------------------------------- */
lis r4,0xc000
ori r4,r4,0x0001
mticcr r4 /* instruction cache */
/* Set-up icache cacheability. */
lis r4, CFG_ICACHE_SACR_VALUE@h
ori r4, r4, CFG_ICACHE_SACR_VALUE@l
mticcr r4
isync
lis r4,0x0000
ori r4,r4,0x0000
mtdccr r4 /* data cache */
/* Set-up dcache cacheability. */
lis r4, CFG_DCACHE_SACR_VALUE@h
ori r4, r4, CFG_DCACHE_SACR_VALUE@l
mtdccr r4
#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX)
#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
/*----------------------------------------------------------------------- */
/* Tune the speed and size for flash CS0 */
/*----------------------------------------------------------------------- */
bl ext_bus_cntlr_init
#endif
#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
/*
* Boards like the Kilauea (405EX) don't have OCM and can't use
* DCache for init-ram. So setup stack here directly after the
* SDRAM is initialized.
* For boards that don't have OCM and can't use the data cache
* for their primordial stack, setup stack here directly after the
* SDRAM is initialized in ext_bus_cntlr_init.
*/
lis r1, CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
......@@ -1007,83 +998,90 @@ _start:
#endif /* CONFIG_405EZ */
#endif
#ifdef CONFIG_NAND_SPL
/*----------------------------------------------------------------------- */
/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
/*----------------------------------------------------------------------- */
#ifdef CFG_INIT_DCACHE_CS
li r4, PBxAP
mtdcr ebccfga, r4
lis r4, CFG_INIT_DCACHE_PBxAR@h
ori r4, r4, CFG_INIT_DCACHE_PBxAR@l
mtdcr ebccfgd, r4
addi r4, 0, PBxCR
mtdcr ebccfga, r4
lis r4, CFG_INIT_DCACHE_PBxCR@h
ori r4, r4, CFG_INIT_DCACHE_PBxCR@l
mtdcr ebccfgd, r4
/*
* Copy SPL from cache into internal SRAM
* Enable the data cache for the 128MB storage access control region
* at CFG_INIT_RAM_ADDR.
*/
li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
mtctr r4
lis r2,CFG_NAND_BOOT_SPL_SRC@h
ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
lis r3,CFG_NAND_BOOT_SPL_DST@h
ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
spl_loop:
lwzu r4,4(r2)
stwu r4,4(r3)
bdnz spl_loop
mfdccr r4
oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
mtdccr r4
/*
* Jump to code in RAM
* Preallocate data cache lines to be used to avoid a subsequent
* cache miss and an ensuing machine check exception when exceptions
* are enabled.
*/
bl 00f
00: mflr r10
lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
sub r10,r10,r3
addi r10,r10,28
mtlr r10
blr
li r0, 0
start_ram:
sync
isync
#endif /* CONFIG_NAND_SPL */
lis r3, CFG_INIT_RAM_ADDR@h
ori r3, r3, CFG_INIT_RAM_ADDR@l
/*----------------------------------------------------------------------- */
/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
/*----------------------------------------------------------------------- */
#ifdef CFG_INIT_DCACHE_CS
/*----------------------------------------------------------------------- */
/* Memory Bank x (nothingness) initialization 1GB+64MEG */
/* used as temporary stack pointer for stage0 */
/*----------------------------------------------------------------------- */
li r4,PBxAP
mtdcr ebccfga,r4
lis r4,0x0380
ori r4,r4,0x0480
mtdcr ebccfgd,r4
addi r4,0,PBxCR
mtdcr ebccfga,r4
lis r4,0x400D
ori r4,r4,0xa000
mtdcr ebccfgd,r4
/* turn on data cache for this region */
lis r4,0x0080
mtdccr r4
lis r4, CFG_INIT_RAM_END@h
ori r4, r4, CFG_INIT_RAM_END@l
/*
* Convert the size, in bytes, to the number of cache lines/blocks
* to preallocate.
*/
clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
srwi r5, r4, L1_CACHE_SHIFT
beq ..load_counter
addi r5, r5, 0x0001
..load_counter:
mtctr r5
/* set stack pointer and clear stack to known value */
/* Preallocate the computed number of cache blocks. */
..alloc_dcache_block:
dcba r0, r3
addi r3, r3, L1_CACHE_BYTES
bdnz ..alloc_dcache_block
sync
lis r1,CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET@l
/*
* Load the initial stack pointer and data area and convert the size,
* in bytes, to the number of words to initialize to a known value.
*/
lis r1, CFG_INIT_RAM_ADDR@h
ori r1, r1, CFG_INIT_SP_OFFSET@l
li r4,2048 /* we store 2048 words to stack */
lis r4, (CFG_INIT_RAM_END >> 2)@h
ori r4, r4, (CFG_INIT_RAM_END >> 2)@l
mtctr r4
lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
lis r2, CFG_INIT_RAM_ADDR@h
ori r2, r2, CFG_INIT_RAM_END@l
lis r4,0xdead /* we store 0xdeaddead in the stack */
ori r4,r4,0xdead
lis r4, CFG_INIT_RAM_PATTERN@h
ori r4, r4, CFG_INIT_RAM_PATTERN@l
..stackloop:
stwu r4,-4(r2)
stwu r4, -4(r2)
bdnz ..stackloop
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
/*
* Make room for stack frame header and clear final stack frame so
* that stack backtraces terminate cleanly.
*/
stwu r0, -4(r1)
stwu r0, -4(r1)
/*
* Set up a dummy frame to store reset vector as return address.
* this causes stack underflow to reset board.
......@@ -1120,13 +1118,8 @@ start_ram:
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* CFG_INIT_DCACHE_CS */
/*----------------------------------------------------------------------- */
/* Initialize SDRAM Controller */
/*----------------------------------------------------------------------- */
bl sdram_init
#ifdef CONFIG_NAND_SPL
bl nand_boot /* will not return */
bl nand_boot_common /* will not return */
#else
GET_GOT /* initialize GOT access */
......@@ -1328,33 +1321,72 @@ in32r:
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
* r3 = Relocated stack pointer
* r4 = Relocated global data pointer
* r5 = Relocated text pointer
*/
.globl relocate_code
relocate_code:
#ifdef CONFIG_4xx_DCACHE
#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS)
/*
* We need to flush the Init Data before the dcache will be
* invalidated
* We need to flush the initial global data (gd_t) before the dcache
* will be invalidated.
*/
/* save regs */
mr r9,r3
mr r10,r4
mr r11,r5
/* Save registers */
mr r9, r3
mr r10, r4
mr r11, r5
mr r3,r4
addi r4,r4,0x200 /* should be enough for init data */
/* Flush initial global data range */
mr r3, r4
addi r4, r4, CFG_GBL_DATA_SIZE@l
bl flush_dcache_range
/* restore regs */
mr r3,r9
mr r4,r10
mr r5,r11
#endif
#if defined(CFG_INIT_DCACHE_CS)
/*
* Undo the earlier data cache set-up for the primordial stack and
* data area. First, invalidate the data cache and then disable data
* cacheability for that area. Finally, restore the EBC values, if
* any.
*/
/* Invalidate the primordial stack and data area in cache */
lis r3, CFG_INIT_RAM_ADDR@h
ori r3, r3, CFG_INIT_RAM_ADDR@l
lis r4, CFG_INIT_RAM_END@h
ori r4, r4, CFG_INIT_RAM_END@l
add r4, r4, r3
bl invalidate_dcache_range
/* Disable cacheability for the region */
mfdccr r3
lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
and r3, r3, r4
mtdccr r3
/* Restore the EBC parameters */
li r3, PBxAP
mtdcr ebccfga, r3
lis r3, PBxAP_VAL@h
ori r3, r3, PBxAP_VAL@l
mtdcr ebccfgd, r3
li r3, PBxCR
mtdcr ebccfga, r3
lis r3, PBxCR_VAL@h
ori r3, r3, PBxCR_VAL@l
mtdcr ebccfgd, r3
#endif /* defined(CFG_INIT_DCACHE_CS) */
/* Restore registers */
mr r3, r9
mr r4, r10
mr r5, r11
#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */
#ifdef CFG_INIT_RAM_DCACHE
/*
......@@ -1396,13 +1428,13 @@ relocate_code:
addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
#else
addi r1,r0,0x0000 /* Default TLB entry is #0 */
#endif
#endif /* CFG_TLB_FOR_BOOT_FLASH */
tlbre r0,r1,0x0002 /* Read contents */
ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
tlbwe r0,r1,0x0002 /* Save it out */
sync
isync
#endif
#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Init Data pointer */
mr r10, r5 /* Save copy of Destination Address */
......@@ -1425,7 +1457,7 @@ relocate_code:
/* First our own GOT */
add r14, r14, r15
/* the the one used by the C code */
/* then the one used by the C code */
add r30, r30, r15
/*
......@@ -2024,3 +2056,75 @@ pll_wait:
blr
function_epilog(mftlb1)
#endif /* CONFIG_440 */
#if defined(CONFIG_NAND_SPL)
/*
* void nand_boot_relocate(dst, src, bytes)
*
* r3 = Destination address to copy code to (in SDRAM)
* r4 = Source address to copy code from
* r5 = size to copy in bytes
*/
nand_boot_relocate:
mr r6,r3
mr r7,r4
mflr r8
/*
* Copy SPL from icache into SDRAM
*/
subi r3,r3,4
subi r4,r4,4
srwi r5,r5,2
mtctr r5
..spl_loop:
lwzu r0,4(r4)
stwu r0,4(r3)
bdnz ..spl_loop
/*
* Calculate "corrected" link register, so that we "continue"
* in execution in destination range
*/
sub r3,r7,r6 /* r3 = src - dst */
sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
mtlr r8
blr
nand_boot_common:
/*
* First initialize SDRAM. It has to be available *before* calling
* nand_boot().
*/
lis r3,CFG_SDRAM_BASE@h
ori r3,r3,CFG_SDRAM_BASE@l
bl initdram
/*
* Now copy the 4k SPL code into SDRAM and continue execution
* from there.
*/
lis r3,CFG_NAND_BOOT_SPL_DST@h
ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
lis r4,CFG_NAND_BOOT_SPL_SRC@h
ori r4,r4,CFG_NAND_BOOT_SPL_SRC@l
lis r5,CFG_NAND_BOOT_SPL_SIZE@h
ori r5,r5,CFG_NAND_BOOT_SPL_SIZE@l
bl nand_boot_relocate
/*
* We're running from SDRAM now!!!
*
* It is necessary for 4xx systems to relocate from running at
* the original location (0xfffffxxx) to somewhere else (SDRAM
* preferably). This is because CS0 needs to be reconfigured for
* NAND access. And we can't reconfigure this CS when currently
* "running" from it.
*/
/*
* Finally call nand_boot() to load main NAND U-Boot image from
* NAND and jump to it.
*/
bl nand_boot /* will not return */
#endif /* CONFIG_NAND_SPL */
cpu/ppc4xx/traps.c
浏览文件 @ 1730edf7
......@@ -170,7 +170,7 @@ MachineCheckException(struct pt_regs *regs)
val = get_esr();
#if !defined(CONFIG_440)
#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
if (val& ESR_IMCP) {
printf("Instruction");
mtspr(ESR, val & ~ESR_IMCP);
......@@ -179,7 +179,7 @@ MachineCheckException(struct pt_regs *regs)
}
printf(" machine check.\n");
#elif defined(CONFIG_440)
#elif defined(CONFIG_440) || defined(CONFIG_405EX)
if (val& ESR_IMCP){
printf("Instruction Synchronous Machine Check exception\n");
mtspr(SPRN_ESR, val & ~ESR_IMCP);
......@@ -187,10 +187,15 @@ MachineCheckException(struct pt_regs *regs)
val = mfspr(MCSR);
if (val & MCSR_IB)
printf("Instruction Read PLB Error\n");
#if defined(CONFIG_440)
if (val & MCSR_DRB)
printf("Data Read PLB Error\n");
if (val & MCSR_DWB)
printf("Data Write PLB Error\n");
#else
if (val & MCSR_DB)
printf("Data PLB Error\n");
#endif
if (val & MCSR_TLBP)
printf("TLB Parity Error\n");
if (val & MCSR_ICP){
......
include/asm-ppc/ppc4xx-sdram.h 0 → 100644
浏览文件 @ 1730edf7
此差异已折叠。
include/asm-ppc/processor.h
浏览文件 @ 1730edf7
......@@ -460,17 +460,19 @@
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#define SPRN_MCAR 0x23d /* Machine Check Address register */
#ifdef CONFIG_440
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
#if defined(CONFIG_440)
#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
#else
#define MCSR_DB 0x20000000 /* Data PLB Error */
#endif /* defined(CONFIG_440) */
#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
#endif
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
......
include/configs/CPCI4052.h
浏览文件 @ 1730edf7
......@@ -88,32 +88,17 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#if 0 /* test-only */
#define CONFIG_NETCONSOLE
#define CONFIG_NET_MULTI
#ifdef CONFIG_NET_MULTI
#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */
#endif
#endif
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#if 0 /* test-only */
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
......@@ -256,29 +241,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/*
* JFFS2 partitions
*/
/* No command line, one static partition, use whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/* mtdparts command line support */
/* Use first bank for JFFS2, second bank contains U-Boot.
*
* Note: fake mtd_id's used, no linux mtd map file.
*/
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=cpci4052-0"
#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)"
*/
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
* NVRAM organization
......
include/configs/CPCI405AB.h
浏览文件 @ 1730edf7
......@@ -88,7 +88,6 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
......@@ -238,27 +237,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/*
* JFFS2 partitions
*/
/* No command line, one static partition */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/* mtdparts command line support */
/* Use first bank for JFFS2, second bank contains U-Boot.
*
* Note: fake mtd_id's used, no linux mtd map file.
*/
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=cpci405ab-0"
#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)"
*/
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC32) for environment
*/
......
include/configs/CPCI405DT.h
浏览文件 @ 1730edf7
......@@ -87,23 +87,12 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#if 0 /* test-only */
#define CONFIG_NETCONSOLE
#define CONFIG_NET_MULTI
#ifdef CONFIG_NET_MULTI
#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */
#endif
#endif
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
......@@ -260,27 +249,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/*
* JFFS2 partitions
*/
/* No command line, one static partition */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/* mtdparts command line support */
/* Use first bank for JFFS2, second bank contains U-Boot.
*
* Note: fake mtd_id's used, no linux mtd map file.
*/
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=cpci405dt-0"
#define MTDPARTS_DEFAULT "mtdparts=cpci405dt-0:-(jffs2)"
*/
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
* NVRAM organization
......@@ -416,7 +384,6 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
* Internal Definitions
*
......
include/configs/acadia.h
浏览文件 @ 1730edf7
......@@ -34,6 +34,13 @@
#define CONFIG_ACADIA 1 /* Board is Acadia */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME acadia
#include "amcc-common.h"
/* Detect Acadia PLL input clock automatically via CPLD bit */
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
66666666 : 33333000)
......@@ -59,16 +66,11 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xfe000000
#define CFG_CPLD_BASE 0x80000000
#define CFG_NAND_ADDR 0xd0000000
#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1)
#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
......@@ -89,12 +91,6 @@
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#define CFG_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/*-----------------------------------------------------------------------
* Environment
......@@ -202,10 +198,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
......@@ -222,77 +215,24 @@
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
#if 0 /* test-only... */
/*-----------------------------------------------------------------------
* SPI stuff - Define to include SPI control
*-----------------------------------------------------------------------
*/
#define CONFIG_SPI
#endif
/*-----------------------------------------------------------------------
* Ethernet
*----------------------------------------------------------------------*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/
#define CONFIG_HAS_ETH0 1
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define xstr(s) str(s)
#define str(s) #s
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=acadia\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=acadia/uImage\0" \
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_PPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff10000\0" \
"ramdisk_addr=fff20000\0" \
"initrd_high=30000000\0" \
"load=tftp 200000 acadia/u-boot.bin\0" \
"update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
"era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
"cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
"nload=tftp 200000 acadia/u-boot-nand.bin\0" \
"nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
"setenv filesize;saveenv\0" \
"nupd=run nload nupdate\0" \
"kozio=bootm ffc60000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
......@@ -305,35 +245,10 @@
#define CONFIG_SUPPORT_VFAT
/*
* BOOTP options
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB
/*
......@@ -344,43 +259,6 @@
#undef CONFIG_CMD_IMLS
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
......@@ -493,21 +371,4 @@
#define CFG_GPIO1_TSRL 0x00000000
#define CFG_GPIO1_TSRH 0x00000000
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#endif /* __CONFIG_H */
include/configs/alpr.h
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......@@ -33,7 +33,6 @@
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
......
include/configs/amcc-common.h 0 → 100644
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include/configs/bamboo.h
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......@@ -36,6 +36,12 @@
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME bamboo
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/*
......@@ -49,10 +55,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
......@@ -84,14 +86,9 @@
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* NVRAM/RTC
*
......@@ -223,15 +220,11 @@
#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
#define CONFIG_PROG_SDRAM_TLB
#undef CFG_DRAM_TEST
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
......@@ -245,54 +238,20 @@
#define CFG_ENV_OFFSET 0x0
#endif /* CFG_ENV_IS_IN_EEPROM */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=bamboo\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/bamboo/uImage\0" \
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
"initrd_high=30000000\0" \
"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
"cp.b 100000 fffa0000 60000;" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_HAS_ETH0
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 1
......@@ -300,16 +259,6 @@
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#endif /* CONFIG_BAMBOO_NAND */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
......@@ -319,77 +268,27 @@
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/
/*
* BOOTP options
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#ifdef CONFIG_BAMBOO_NAND
#define CONFIG_CMD_NAND
#endif
#define CONFIG_SUPPORT_VFAT
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
/*-----------------------------------------------------------------------
* PCI stuff
......@@ -408,28 +307,4 @@
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#endif /* __CONFIG_H */
include/configs/bubinga.h
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include/configs/canyonlands.h
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include/configs/ebony.h
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include/configs/katmai.h
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include/configs/kilauea.h
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include/configs/luan.h
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include/configs/makalu.h
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include/configs/ocotea.h
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include/configs/sequoia.h
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include/configs/taihu.h
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include/configs/taishan.h
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include/configs/walnut.h
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include/configs/yosemite.h
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include/configs/yucca.h
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include/ppc405.h
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include/ppc440.h
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include/ppc4xx.h
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nand_spl/board/amcc/acadia/Makefile
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......@@ -51,7 +51,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS)
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
......
nand_spl/board/amcc/bamboo/Makefile
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nand_spl/board/amcc/bamboo/sdram.c
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nand_spl/nand_boot.c
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post/cpu/ppc4xx/uart.c
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