Merge branch '2020-01-02-master-imports'

- Assorted test.py fixes
- Other minor changes

.gitignore

@@ -7,6 +7,7 @@
 #
 .*
 *.a
+*.asn1.[ch]
 *.bin
 *.cfgout
 *.dtb

.mailmap

@@ -29,6 +29,7 @@ Jagan Teki <jaganna@gmail.com>
 Jagan Teki <jaganna@xilinx.com>
 Jagan Teki <jagannadh.teki@gmail.com>
 Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
+Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
 Markus Klotzbuecher <mk@denx.de>
 Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
 Prabhakar Kushwaha <prabhakar@freescale.com>

arch/arm/Kconfig

@@ -17,7 +17,7 @@ config POSITION_INDEPENDENT
 	  be loaded to and run from that address. This option lifts that
 	  restriction, thus allowing the code to be loaded to and executed
 	  from almost any address. This logic relies on the relocation
-	  information that is embedded into the binary to support U-Boot
+	  information that is embedded in the binary to support U-Boot
 	  relocating itself to the top-of-RAM later during execution.
 
 config INIT_SP_RELATIVE
@@ -26,7 +26,7 @@ config INIT_SP_RELATIVE
 	  U-Boot typically uses a hard-coded value for the stack pointer
 	  before relocation. Enable this option to instead calculate the
 	  initial SP at run-time. This is useful to avoid hard-coding addresses
-	  into U-Boot, so that can be loaded and executed at arbitrary
+	  into U-Boot, so that it can be loaded and executed at arbitrary
 	  addresses and thus avoid using arbitrary addresses at runtime.
 
 	  If this option is enabled, the early stack pointer is set to
@@ -57,7 +57,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 	hex
 	help
 	  The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
-	  TEXT_OFFSET value written in to the Linux kernel image header.
+	  TEXT_OFFSET value written to the Linux kernel image header.
 endif
 endif
 
@@ -121,7 +121,7 @@ config SYS_ARM_MMU
 	select SYS_ARM_CACHE_CP15
 	help
 	  Select if you want MMU-based virtualised addressing space
-	  support by paged memory management.
+	  support via paged memory management.
 
 config SYS_ARM_MPU
 	bool 'Use the ARM v7 PMSA Compliant MPU'
@@ -136,8 +136,8 @@ config SYS_ARM_MPU
 # startup. Note that in general these options force the workarounds to be
 # applied; no CPU-type/version detection exists, unlike the similar options in
 # the Linux kernel. Do not set these options unless they apply!  Also note that
-# the following can be machine specific errata. These do have ability to
-# provide rudimentary version and machine specific checks, but expect no
+# the following can be machine-specific errata. These do have ability to
+# provide rudimentary version and machine-specific checks, but expect no
 # product checks:
 # CONFIG_ARM_ERRATA_430973
 # CONFIG_ARM_ERRATA_454179
@@ -332,7 +332,7 @@ config SYS_CACHELINE_SIZE
 config ARCH_CPU_INIT
 	bool "Enable ARCH_CPU_INIT"
 	help
-	  Some architectures require a call to arch_cpu_init()
+	  Some architectures require a call to arch_cpu_init().
 	  Say Y here to enable it
 
 config SYS_ARCH_TIMER
@@ -342,7 +342,7 @@ config SYS_ARCH_TIMER
 	help
 	  The ARM Generic Timer (aka arch-timer) provides an architected
 	  interface to a timer source on an SoC.
-	  It is mandantory for ARMv8 implementation and widely available
+	  It is mandatory for ARMv8 implementation and widely available
 	  on ARMv7 systems.
 
 config ARM_SMCCC
@@ -385,7 +385,7 @@ config TPL_SYS_THUMB_BUILD
 	default y if SYS_THUMB_BUILD
 	depends on TPL && !ARM64
 	help
-	   Use this flag to build SPL using the Thumb instruction set for
+	   Use this flag to build TPL using the Thumb instruction set for
 	   ARM architectures. Thumb instruction set provides better code
 	   density. For ARM architectures that support Thumb2 this flag will
 	   result in Thumb2 code generated by GCC.
@@ -394,7 +394,7 @@ config TPL_SYS_THUMB_BUILD
 config SYS_L2CACHE_OFF
 	bool "L2cache off"
 	help
-	  If SoC does not support L2CACHE or one do not want to enable
+	  If SoC does not support L2CACHE or one does not want to enable
 	  L2CACHE, choose this option.
 
 config ENABLE_ARM_SOC_BOOT0_HOOK
@@ -414,7 +414,7 @@ config USE_ARCH_MEMCPY
 	depends on !ARM64
 	help
 	  Enable the generation of an optimized version of memcpy.
-	  Such implementation may be faster under some conditions
+	  Such an implementation may be faster under some conditions
 	  but may increase the binary size.
 
 config SPL_USE_ARCH_MEMCPY
@@ -423,7 +423,7 @@ config SPL_USE_ARCH_MEMCPY
 	depends on !ARM64 && SPL
 	help
 	  Enable the generation of an optimized version of memcpy.
-	  Such implementation may be faster under some conditions
+	  Such an implementation may be faster under some conditions
 	  but may increase the binary size.
 
 config TPL_USE_ARCH_MEMCPY
@@ -432,7 +432,7 @@ config TPL_USE_ARCH_MEMCPY
 	depends on !ARM64 && TPL
 	help
 	  Enable the generation of an optimized version of memcpy.
-	  Such implementation may be faster under some conditions
+	  Such an implementation may be faster under some conditions
 	  but may increase the binary size.
 
 config USE_ARCH_MEMSET
@@ -441,7 +441,7 @@ config USE_ARCH_MEMSET
 	depends on !ARM64
 	help
 	  Enable the generation of an optimized version of memset.
-	  Such implementation may be faster under some conditions
+	  Such an implementation may be faster under some conditions
 	  but may increase the binary size.
 
 config SPL_USE_ARCH_MEMSET
@@ -450,7 +450,7 @@ config SPL_USE_ARCH_MEMSET
 	depends on !ARM64 && SPL
 	help
 	  Enable the generation of an optimized version of memset.
-	  Such implementation may be faster under some conditions
+	  Such an implementation may be faster under some conditions
 	  but may increase the binary size.
 
 config TPL_USE_ARCH_MEMSET
@@ -459,7 +459,7 @@ config TPL_USE_ARCH_MEMSET
 	depends on !ARM64 && TPL
 	help
 	  Enable the generation of an optimized version of memset.
-	  Such implementation may be faster under some conditions
+	  Such an implementation may be faster under some conditions
 	  but may increase the binary size.
 
 config SET_STACK_SIZE
@@ -467,14 +467,14 @@ config SET_STACK_SIZE
 	default y if ARCH_VERSAL || ARCH_ZYNQMP
 	help
 	  This will enable an option to set max stack size that can be
-	  used by u-boot.
+	  used by U-Boot.
 
 config STACK_SIZE
-	hex "Define max stack size that can be used by u-boot"
+	hex "Define max stack size that can be used by U-Boot"
 	depends on SET_STACK_SIZE
 	default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
 	help
-	  Defines Max stack size that can be used by u-boot so that the
+	  Define Max stack size that can be used by U-Boot so that the
 	  initrd_high will be calculated as base stack pointer minus this
 	  stack size.
 
@@ -689,7 +689,7 @@ config TARGET_BCMNS2
 	help
 	  Support for Broadcom Northstar 2 SoCs.  NS2 is a quad-core 64-bit
 	  ARMv8 Cortex-A57 processors targeting a broad range of networking
-	  applications
+	  applications.
 
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
@@ -1101,8 +1101,8 @@ config TARGET_LS2080A_EMU
 	select ARMV8_MULTIENTRY
 	select FSL_DDR_SYNC_REFRESH
 	help
-	  Support for Freescale LS2080A_EMU platform
-	  The LS2080A Development System (EMULATOR) is a pre silicon
+	  Support for Freescale LS2080A_EMU platform.
+	  The LS2080A Development System (EMULATOR) is a pre-silicon
 	  development platform that supports the QorIQ LS2080A
 	  Layerscape Architecture processor.
 
@@ -1114,7 +1114,7 @@ config TARGET_LS2080A_SIMU
 	select ARMV8_MULTIENTRY
 	select BOARD_LATE_INIT
 	help
-	  Support for Freescale LS2080A_SIMU platform
+	  Support for Freescale LS2080A_SIMU platform.
 	  The LS2080A Development System (QDS) is a pre silicon
 	  development platform that supports the QorIQ LS2080A
 	  Layerscape Architecture processor.
@@ -1130,7 +1130,7 @@ config TARGET_LS1088AQDS
 	select SUPPORT_SPL
 	select FSL_DDR_INTERACTIVE if !SD_BOOT
 	help
-	  Support for NXP LS1088AQDS platform
+	  Support for NXP LS1088AQDS platform.
 	  The LS1088A Development System (QDS) is a high-performance
 	  development platform that supports the QorIQ LS1088A
 	  Layerscape Architecture processor.
@@ -1149,7 +1149,7 @@ config TARGET_LS2080AQDS
 	select FSL_DDR_BIST
 	select FSL_DDR_INTERACTIVE if !SPL
 	help
-	  Support for Freescale LS2080AQDS platform
+	  Support for Freescale LS2080AQDS platform.
 	  The LS2080A Development System (QDS) is a high-performance
 	  development platform that supports the QorIQ LS2080A
 	  Layerscape Architecture processor.
@@ -1649,7 +1649,7 @@ config TFABOOT
 	default n
 	help
 	  Enabling this will make a U-Boot binary that is capable of being
-	  booted via TF-A.
+	  booted via TF-A (Trusted Firmware for Cortex-A).
 
 config TI_SECURE_DEVICE
 	bool "HS Device Type Support"

test/py/tests/test_env.py

@@ -49,7 +49,7 @@ class StateTestEnv(object):
         for l in response.splitlines():
             if not '=' in l:
                 continue
-            (var, value) = l.strip().split('=', 1)
+            (var, value) = l.split('=', 1)
             self.env[var] = value
 
     def get_existent_var(self):

test/py/tests/test_handoff.py

@@ -6,7 +6,7 @@ import pytest
 # Magic number to check that SPL handoff is working
 TEST_HANDOFF_MAGIC = 0x14f93c7b
 
-@pytest.mark.boardspec('sandbox')
+@pytest.mark.boardspec('sandbox_spl')
 @pytest.mark.buildconfigspec('spl')
 def test_handoff(u_boot_console):
     """Test that of-platdata can be generated and used in sandbox"""

tools/.gitignore

+/asn1_compiler
 /atmel_pmecc_params
 /bin2header
 /bmp_logo