colibri-imx6: use dynamic DDR calibration

Enable dynamic DDR calibration to have a reliable behavior on edge
temperatures conditions.
Signed-off-by: NMax Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: NFrancesco Dolcini <francesco.dolcini@toradex.com>

board/toradex/colibri_imx6/colibri_imx6.c

@@ -997,9 +997,28 @@ static void ddr_init(int *table, int size)
 		writel(table[2 * i + 1], table[2 * i]);
 }
 
+/* Perform DDR DRAM calibration */
+static void spl_dram_perform_cal(u8 dsize)
+{
+#ifdef CONFIG_MX6_DDRCAL
+	int err;
+	struct mx6_ddr_sysinfo ddr_sysinfo = {
+		.dsize = dsize,
+	};
+
+	err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+	if (err)
+		printf("error %d from write level calibration\n", err);
+	err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+	if (err)
+		printf("error %d from dqs calibration\n", err);
+#endif
+}
+
 static void spl_dram_init(void)
 {
 	int minc, maxc;
+	u8 dsize = 2;
 
 	switch (get_cpu_temp_grade(&minc, &maxc)) {
 	case TEMP_COMMERCIAL:
@@ -1009,6 +1028,7 @@ static void spl_dram_init(void)
 			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
 		} else {
 			puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
+			dsize = 1;
 			ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
 		}
 		break;
@@ -1020,11 +1040,13 @@ static void spl_dram_init(void)
 			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
 		} else {
 			puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
+			dsize = 1;
 			ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
 		}
 		break;
 	};
 	udelay(100);
+	spl_dram_perform_cal(dsize);
 }
 
 static iomux_v3_cfg_t const gpio_reset_pad[] = {

configs/colibri_imx6_defconfig

@@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x10010000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_MX6DL=y
+CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_COLIBRI_IMX6=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y