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体验新版 GitCode,发现更多精彩内容 >>
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10fda487
编写于
11月 04, 2013
作者:
E
Eric Nelson
提交者:
Stefano Babic
11月 13, 2013
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
i.MX6DQ/DLS: replace pad names with their Linux kernel equivalents
Signed-off-by:
N
Eric Nelson
<
eric.nelson@boundarydevices.com
>
上级
c2cde27d
变更
10
展开全部
隐藏空白更改
内联
并排
Showing
10 changed file
with
2064 addition
and
2064 deletion
+2064
-2064
arch/arm/include/asm/arch-mx6/mx6dl_pins.h
arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+912
-912
arch/arm/include/asm/arch-mx6/mx6q_pins.h
arch/arm/include/asm/arch-mx6/mx6q_pins.h
+849
-849
board/barco/titanium/titanium.c
board/barco/titanium/titanium.c
+53
-53
board/boundary/nitrogen6x/nitrogen6x.c
board/boundary/nitrogen6x/nitrogen6x.c
+85
-85
board/congatec/cgtqmx6eval/cgtqmx6eval.c
board/congatec/cgtqmx6eval/cgtqmx6eval.c
+20
-20
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6qarm2/mx6qarm2.c
+33
-33
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6qsabreauto/mx6qsabreauto.c
+30
-30
board/freescale/mx6sabresd/mx6sabresd.c
board/freescale/mx6sabresd/mx6sabresd.c
+45
-45
board/udoo/udoo.c
board/udoo/udoo.c
+10
-10
board/wandboard/wandboard.c
board/wandboard/wandboard.c
+27
-27
未找到文件。
arch/arm/include/asm/arch-mx6/mx6dl_pins.h
浏览文件 @
10fda487
此差异已折叠。
点击以展开。
arch/arm/include/asm/arch-mx6/mx6q_pins.h
浏览文件 @
10fda487
此差异已折叠。
点击以展开。
board/barco/titanium/titanium.c
浏览文件 @
10fda487
...
...
@@ -45,18 +45,18 @@ int dram_init(void)
}
iomux_v3_cfg_t
const
uart1_pads
[]
=
{
MX6_PAD_SD3_DAT6__UART1_RX
D
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_SD3_DAT7__UART1_TX
D
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_SD3_DAT6__UART1_RX
_DATA
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_SD3_DAT7__UART1_TX
_DATA
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
};
iomux_v3_cfg_t
const
uart2_pads
[]
=
{
MX6_PAD_EIM_D26__UART2_TX
D
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_EIM_D27__UART2_RX
D
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_EIM_D26__UART2_TX
_DATA
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_EIM_D27__UART2_RX
_DATA
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
};
iomux_v3_cfg_t
const
uart4_pads
[]
=
{
MX6_PAD_CSI0_DAT12__UART4_TX
D
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_CSI0_DAT13__UART4_RX
D
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_CSI0_DAT12__UART4_TX
_DATA
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_CSI0_DAT13__UART4_RX
_DATA
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
...
...
@@ -64,12 +64,12 @@ iomux_v3_cfg_t const uart4_pads[] = {
struct
i2c_pads_info
i2c_pad_info0
=
{
.
scl
=
{
.
i2c_mode
=
MX6_PAD_CSI0_DAT9__I2C1_SCL
|
PC
,
.
gpio_mode
=
MX6_PAD_CSI0_DAT9__GPIO
_5_
27
|
PC
,
.
gpio_mode
=
MX6_PAD_CSI0_DAT9__GPIO
5_IO
27
|
PC
,
.
gp
=
IMX_GPIO_NR
(
5
,
27
)
},
.
sda
=
{
.
i2c_mode
=
MX6_PAD_CSI0_DAT8__I2C1_SDA
|
PC
,
.
gpio_mode
=
MX6_PAD_CSI0_DAT8__GPIO
_5_
26
|
PC
,
.
gpio_mode
=
MX6_PAD_CSI0_DAT8__GPIO
5_IO
26
|
PC
,
.
gp
=
IMX_GPIO_NR
(
5
,
26
)
}
};
...
...
@@ -77,81 +77,81 @@ struct i2c_pads_info i2c_pad_info0 = {
struct
i2c_pads_info
i2c_pad_info2
=
{
.
scl
=
{
.
i2c_mode
=
MX6_PAD_GPIO_3__I2C3_SCL
|
PC
,
.
gpio_mode
=
MX6_PAD_GPIO_3__GPIO
_1_
3
|
PC
,
.
gpio_mode
=
MX6_PAD_GPIO_3__GPIO
1_IO0
3
|
PC
,
.
gp
=
IMX_GPIO_NR
(
1
,
3
)
},
.
sda
=
{
.
i2c_mode
=
MX6_PAD_GPIO_16__I2C3_SDA
|
PC
,
.
gpio_mode
=
MX6_PAD_GPIO_16__GPIO
_7_
11
|
PC
,
.
gpio_mode
=
MX6_PAD_GPIO_16__GPIO
7_IO
11
|
PC
,
.
gp
=
IMX_GPIO_NR
(
7
,
11
)
}
};
iomux_v3_cfg_t
const
usdhc3_pads
[]
=
{
MX6_PAD_SD3_CLK__
USDHC
3_CLK
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_CMD__
USDHC
3_CMD
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT0__
USDHC3_DAT
0
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT1__
USDHC3_DAT
1
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT2__
USDHC3_DAT
2
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT3__
USDHC3_DAT
3
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT5__GPIO
_7_
0
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
/* CD */
MX6_PAD_SD3_CLK__
SD
3_CLK
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_CMD__
SD
3_CMD
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT0__
SD3_DATA
0
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT1__
SD3_DATA
1
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT2__
SD3_DATA
2
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT3__
SD3_DATA
3
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT5__GPIO
7_IO0
0
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
/* CD */
};
iomux_v3_cfg_t
const
enet_pads1
[]
=
{
MX6_PAD_ENET_MDIO__ENET_MDIO
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_ENET_MDC__ENET_MDC
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TXC__
ENET_
RGMII_TXC
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TD0__
ENET_
RGMII_TD0
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TD1__
ENET_
RGMII_TD1
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TD2__
ENET_
RGMII_TD2
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TD3__
ENET_
RGMII_TD3
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TXC__RGMII_TXC
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TD0__RGMII_TD0
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TD1__RGMII_TD1
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TD2__RGMII_TD2
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TD3__RGMII_TD3
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
/* pin 35 - 1 (PHY_AD2) on reset */
MX6_PAD_RGMII_RXC__GPIO
_6_
30
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_RGMII_RXC__GPIO
6_IO
30
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO
_6_
25
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_RGMII_RD0__GPIO
6_IO
25
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO
_6_
27
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_RGMII_RD1__GPIO
6_IO
27
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO
_6_
28
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_RGMII_RD2__GPIO
6_IO
28
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO
_6_
29
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_RGMII_RD3__GPIO
6_IO
29
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO
_6_
24
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_RGMII_RX_CTL__GPIO
6_IO
24
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
/* pin 42 PHY nRST */
MX6_PAD_EIM_D23__GPIO
_3_
23
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_EIM_D23__GPIO
3_IO
23
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
};
iomux_v3_cfg_t
const
enet_pads2
[]
=
{
MX6_PAD_RGMII_RXC__
ENET_
RGMII_RXC
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RD0__
ENET_
RGMII_RD0
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RD1__
ENET_
RGMII_RD1
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RD2__
ENET_
RGMII_RD2
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RD3__
ENET_
RGMII_RD3
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RXC__RGMII_RXC
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RD0__RGMII_RD0
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RD1__RGMII_RD1
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RD2__RGMII_RD2
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RD3__RGMII_RD3
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL
|
MUX_PAD_CTRL
(
ENET_PAD_CTRL
),
};
iomux_v3_cfg_t
nfc_pads
[]
=
{
MX6_PAD_NANDF_CLE__
RAW
NAND_CLE
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_ALE__
RAW
NAND_ALE
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_WP_B__
RAWNAND_RESETN
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_RB0__
RAWNAND_READY0
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_CS0__
RAWNAND_CE0N
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_CS1__
RAWNAND_CE1N
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_CS2__
RAWNAND_CE2N
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_CS3__
RAWNAND_CE3N
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_SD4_CMD__
RAWNAND_RDN
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_SD4_CLK__
RAWNAND_WRN
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D0__
RAWNAND_D
0
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D1__
RAWNAND_D
1
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D2__
RAWNAND_D
2
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D3__
RAWNAND_D
3
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D4__
RAWNAND_D
4
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D5__
RAWNAND_D
5
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D6__
RAWNAND_D
6
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D7__
RAWNAND_D
7
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_SD4_DAT0__
RAW
NAND_DQS
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_CLE__NAND_CLE
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_ALE__NAND_ALE
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_WP_B__
NAND_WP_B
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_RB0__
NAND_READY_B
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_CS0__
NAND_CE0_B
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_CS1__
NAND_CE1_B
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_CS2__
NAND_CE2_B
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_CS3__
NAND_CE3_B
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_SD4_CMD__
NAND_RE_B
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_SD4_CLK__
NAND_WE_B
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D0__
NAND_DATA0
0
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D1__
NAND_DATA0
1
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D2__
NAND_DATA0
2
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D3__
NAND_DATA0
3
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D4__
NAND_DATA0
4
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D5__
NAND_DATA0
5
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D6__
NAND_DATA0
6
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_NANDF_D7__
NAND_DATA0
7
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_SD4_DAT0__NAND_DQS
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
};
static
void
setup_gpmi_nand
(
void
)
...
...
board/boundary/nitrogen6x/nitrogen6x.c
浏览文件 @
10fda487
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点击以展开。
board/congatec/cgtqmx6eval/cgtqmx6eval.c
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10fda487
此差异已折叠。
点击以展开。
board/freescale/mx6qarm2/mx6qarm2.c
浏览文件 @
10fda487
此差异已折叠。
点击以展开。
board/freescale/mx6qsabreauto/mx6qsabreauto.c
浏览文件 @
10fda487
此差异已折叠。
点击以展开。
board/freescale/mx6sabresd/mx6sabresd.c
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点击以展开。
board/udoo/udoo.c
浏览文件 @
10fda487
...
...
@@ -40,22 +40,22 @@ int dram_init(void)
}
static
iomux_v3_cfg_t
const
uart2_pads
[]
=
{
MX6_PAD_EIM_D26__UART2_TX
D
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_EIM_D27__UART2_RX
D
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_EIM_D26__UART2_TX
_DATA
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
MX6_PAD_EIM_D27__UART2_RX
_DATA
|
MUX_PAD_CTRL
(
UART_PAD_CTRL
),
};
static
iomux_v3_cfg_t
const
usdhc3_pads
[]
=
{
MX6_PAD_SD3_CLK__
USDHC3_CLK
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_CMD__
USDHC3_CMD
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT0__
USDHC3_DAT
0
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT1__
USDHC3_DAT
1
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT2__
USDHC3_DAT
2
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT3__
USDHC3_DAT
3
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_CLK__
SD3_CLK
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_CMD__
SD3_CMD
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT0__
SD3_DATA
0
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT1__
SD3_DATA
1
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT2__
SD3_DATA
2
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
MX6_PAD_SD3_DAT3__
SD3_DATA
3
|
MUX_PAD_CTRL
(
USDHC_PAD_CTRL
),
};
static
iomux_v3_cfg_t
const
wdog_pads
[]
=
{
MX6_PAD_EIM_A24__GPIO
_5_
4
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_EIM_D19__GPIO
_3_
19
,
MX6_PAD_EIM_A24__GPIO
5_IO0
4
|
MUX_PAD_CTRL
(
NO_PAD_CTRL
),
MX6_PAD_EIM_D19__GPIO
3_IO
19
,
};
static
void
setup_iomux_uart
(
void
)
...
...
board/wandboard/wandboard.c
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