Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OS
U-Boot.Mirror
提交
10af8781
U
U-Boot.Mirror
项目概览
OS
/
U-Boot.Mirror
通知
1
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
U
U-Boot.Mirror
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
10af8781
编写于
3月 26, 2015
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-x86
上级
f643d929
6f1eba49
变更
23
展开全部
隐藏空白更改
内联
并排
Showing
23 changed file
with
1852 addition
and
1076 deletion
+1852
-1076
arch/x86/cpu/quark/hte.c
arch/x86/cpu/quark/hte.c
+37
-37
arch/x86/cpu/quark/hte.h
arch/x86/cpu/quark/hte.h
+2
-2
arch/x86/cpu/quark/mrc.c
arch/x86/cpu/quark/mrc.c
+8
-7
arch/x86/cpu/quark/mrc_util.c
arch/x86/cpu/quark/mrc_util.c
+161
-165
arch/x86/cpu/quark/mrc_util.h
arch/x86/cpu/quark/mrc_util.h
+0
-34
arch/x86/cpu/quark/quark.c
arch/x86/cpu/quark/quark.c
+19
-0
arch/x86/cpu/quark/smc.c
arch/x86/cpu/quark/smc.c
+531
-674
arch/x86/cpu/quark/smc.h
arch/x86/cpu/quark/smc.h
+218
-131
doc/README.drivers.eth
doc/README.drivers.eth
+35
-16
doc/README.x86
doc/README.x86
+7
-0
drivers/net/Makefile
drivers/net/Makefile
+1
-0
drivers/net/e1000.h
drivers/net/e1000.h
+3
-4
drivers/net/pch_gbe.c
drivers/net/pch_gbe.c
+466
-0
drivers/net/pch_gbe.h
drivers/net/pch_gbe.h
+300
-0
drivers/usb/gadget/ether.c
drivers/usb/gadget/ether.c
+0
-1
drivers/usb/gadget/rndis.c
drivers/usb/gadget/rndis.c
+0
-1
include/configs/crownbay.h
include/configs/crownbay.h
+12
-0
include/configs/galileo.h
include/configs/galileo.h
+13
-0
include/configs/x86-common.h
include/configs/x86-common.h
+29
-2
include/fdtdec.h
include/fdtdec.h
+4
-1
include/net.h
include/net.h
+2
-0
include/netdev.h
include/netdev.h
+4
-0
include/usb_ether.h
include/usb_ether.h
+0
-1
未找到文件。
arch/x86/cpu/quark/hte.c
浏览文件 @
10af8781
...
...
@@ -20,9 +20,9 @@
*/
static
void
hte_enable_all_errors
(
void
)
{
msg_port_write
(
HTE
,
0x000200
A2
,
0xFFFFFFFF
);
msg_port_write
(
HTE
,
0x000200
A3
,
0x000000FF
);
msg_port_write
(
HTE
,
0x000200
A
4
,
0x00000000
);
msg_port_write
(
HTE
,
0x000200
a2
,
0xffffffff
);
msg_port_write
(
HTE
,
0x000200
a3
,
0x000000ff
);
msg_port_write
(
HTE
,
0x000200
a
4
,
0x00000000
);
}
/**
...
...
@@ -32,7 +32,7 @@ static void hte_enable_all_errors(void)
*/
static
u32
hte_check_errors
(
void
)
{
return
msg_port_read
(
HTE
,
0x000200
A
7
);
return
msg_port_read
(
HTE
,
0x000200
a
7
);
}
/**
...
...
@@ -44,11 +44,11 @@ static void hte_wait_for_complete(void)
ENTERFN
();
do
{}
while
((
msg_port_read
(
HTE
,
0x00020012
)
&
BIT30
)
!=
0
);
do
{}
while
((
msg_port_read
(
HTE
,
0x00020012
)
&
(
1
<<
30
)
)
!=
0
);
tmp
=
msg_port_read
(
HTE
,
0x00020011
);
tmp
|=
BIT9
;
tmp
&=
~
(
BIT12
|
BIT13
);
tmp
|=
(
1
<<
9
)
;
tmp
&=
~
(
(
1
<<
12
)
|
(
1
<<
13
)
);
msg_port_write
(
HTE
,
0x00020011
,
tmp
);
LEAVEFN
();
...
...
@@ -65,9 +65,9 @@ static void hte_clear_error_regs(void)
* Clear all HTE errors and enable error checking
* for burst and chunk.
*/
tmp
=
msg_port_read
(
HTE
,
0x000200
A
1
);
tmp
|=
BIT8
;
msg_port_write
(
HTE
,
0x000200
A
1
,
tmp
);
tmp
=
msg_port_read
(
HTE
,
0x000200
a
1
);
tmp
|=
(
1
<<
8
)
;
msg_port_write
(
HTE
,
0x000200
a
1
,
tmp
);
}
/**
...
...
@@ -91,25 +91,25 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
u32
offset
;
if
(
first_run
)
{
msg_port_write
(
HTE
,
0x00020020
,
0x01
B
10021
);
msg_port_write
(
HTE
,
0x00020020
,
0x01
b
10021
);
msg_port_write
(
HTE
,
0x00020021
,
0x06000000
);
msg_port_write
(
HTE
,
0x00020022
,
addr
>>
6
);
msg_port_write
(
HTE
,
0x00020062
,
0x00800015
);
msg_port_write
(
HTE
,
0x00020063
,
0x
AAAAAAAA
);
msg_port_write
(
HTE
,
0x00020064
,
0x
CCCCCCCC
);
msg_port_write
(
HTE
,
0x00020065
,
0x
F0F0F0F
0
);
msg_port_write
(
HTE
,
0x00020063
,
0x
aaaaaaaa
);
msg_port_write
(
HTE
,
0x00020064
,
0x
cccccccc
);
msg_port_write
(
HTE
,
0x00020065
,
0x
f0f0f0f
0
);
msg_port_write
(
HTE
,
0x00020061
,
0x00030008
);
if
(
mode
==
WRITE_TRAIN
)
pattern
=
0x
C33C
0000
;
pattern
=
0x
c33c
0000
;
else
/* READ_TRAIN */
pattern
=
0x
AA5555AA
;
pattern
=
0x
aa5555aa
;
for
(
offset
=
0x80
;
offset
<=
0x8
F
;
offset
++
)
for
(
offset
=
0x80
;
offset
<=
0x8
f
;
offset
++
)
msg_port_write
(
HTE
,
offset
,
pattern
);
}
msg_port_write
(
HTE
,
0x000200
A1
,
0xFFFF
1000
);
msg_port_write
(
HTE
,
0x000200
a1
,
0xffff
1000
);
msg_port_write
(
HTE
,
0x00020011
,
0x00011000
);
msg_port_write
(
HTE
,
0x00020011
,
0x00011100
);
...
...
@@ -119,7 +119,7 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
* any bytelane errors.
*/
return
(
hte_check_errors
()
>>
8
)
&
0x
FF
;
return
(
hte_check_errors
()
>>
8
)
&
0x
ff
;
}
/**
...
...
@@ -153,7 +153,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
msg_port_write
(
HTE
,
0x00020024
,
0x06070000
);
msg_port_write
(
HTE
,
0x00020022
,
addr
>>
6
);
msg_port_write
(
HTE
,
0x00020025
,
addr
>>
6
);
msg_port_write
(
HTE
,
0x00020062
,
0x0000002
A
);
msg_port_write
(
HTE
,
0x00020062
,
0x0000002
a
);
msg_port_write
(
HTE
,
0x00020063
,
seed_victim
);
msg_port_write
(
HTE
,
0x00020064
,
seed_aggressor
);
msg_port_write
(
HTE
,
0x00020065
,
seed_victim
);
...
...
@@ -163,21 +163,21 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
*
* Start with bit0
*/
for
(
offset
=
0x80
;
offset
<=
0x8
F
;
offset
++
)
{
for
(
offset
=
0x80
;
offset
<=
0x8
f
;
offset
++
)
{
if
((
offset
%
8
)
==
victim_bit
)
msg_port_write
(
HTE
,
offset
,
0x55555555
);
else
msg_port_write
(
HTE
,
offset
,
0x
CCCCCCCC
);
msg_port_write
(
HTE
,
offset
,
0x
cccccccc
);
}
msg_port_write
(
HTE
,
0x00020061
,
0x00000000
);
msg_port_write
(
HTE
,
0x00020066
,
0x03440000
);
msg_port_write
(
HTE
,
0x000200
A1
,
0xFFFF
1000
);
msg_port_write
(
HTE
,
0x000200
a1
,
0xffff
1000
);
}
tmp
=
0x10001000
|
(
loop_cnt
<<
16
);
msg_port_write
(
HTE
,
0x00020011
,
tmp
);
msg_port_write
(
HTE
,
0x00020011
,
tmp
|
BIT8
);
msg_port_write
(
HTE
,
0x00020011
,
tmp
|
(
1
<<
8
)
);
hte_wait_for_complete
();
...
...
@@ -185,7 +185,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
* any bytelane errors.
*/
return
(
hte_check_errors
()
>>
8
)
&
0x
FF
;
return
(
hte_check_errors
()
>>
8
)
&
0x
ff
;
}
/**
...
...
@@ -219,14 +219,14 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
msg_port_write
(
HTE
,
0x00020062
,
0x00000015
);
for
(
offset
=
0x80
;
offset
<=
0x8
F
;
offset
++
)
msg_port_write
(
HTE
,
offset
,
((
offset
&
1
)
?
0x
A55A
:
0x5AA
5
));
for
(
offset
=
0x80
;
offset
<=
0x8
f
;
offset
++
)
msg_port_write
(
HTE
,
offset
,
((
offset
&
1
)
?
0x
a55a
:
0x5aa
5
));
msg_port_write
(
HTE
,
0x00020021
,
0x00000000
);
msg_port_write
(
HTE
,
0x00020022
,
(
mrc_params
->
mem_size
>>
6
)
-
1
);
msg_port_write
(
HTE
,
0x00020063
,
0x
AAAAAAAA
);
msg_port_write
(
HTE
,
0x00020064
,
0x
CCCCCCCC
);
msg_port_write
(
HTE
,
0x00020065
,
0x
F0F0F0F
0
);
msg_port_write
(
HTE
,
0x00020063
,
0x
aaaaaaaa
);
msg_port_write
(
HTE
,
0x00020064
,
0x
cccccccc
);
msg_port_write
(
HTE
,
0x00020065
,
0x
f0f0f0f
0
);
msg_port_write
(
HTE
,
0x00020066
,
0x03000000
);
switch
(
flag
)
{
...
...
@@ -243,7 +243,7 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
break
;
default:
DPF
(
D_INFO
,
"Unknown parameter for flag: %d
\n
"
,
flag
);
return
0x
FFFFFFFF
;
return
0x
ffffffff
;
}
DPF
(
D_INFO
,
"hte_mem_init"
);
...
...
@@ -379,16 +379,16 @@ void hte_mem_op(u32 addr, u8 first_run, u8 is_write)
msg_port_write
(
HTE
,
0x00020021
,
0x06000000
);
msg_port_write
(
HTE
,
0x00020022
,
addr
>>
6
);
msg_port_write
(
HTE
,
0x00020062
,
0x00800015
);
msg_port_write
(
HTE
,
0x00020063
,
0x
AAAAAAAA
);
msg_port_write
(
HTE
,
0x00020064
,
0x
CCCCCCCC
);
msg_port_write
(
HTE
,
0x00020065
,
0x
F0F0F0F
0
);
msg_port_write
(
HTE
,
0x00020063
,
0x
aaaaaaaa
);
msg_port_write
(
HTE
,
0x00020064
,
0x
cccccccc
);
msg_port_write
(
HTE
,
0x00020065
,
0x
f0f0f0f
0
);
msg_port_write
(
HTE
,
0x00020061
,
0x00030008
);
for
(
offset
=
0x80
;
offset
<=
0x8
F
;
offset
++
)
msg_port_write
(
HTE
,
offset
,
0x
C33C
0000
);
for
(
offset
=
0x80
;
offset
<=
0x8
f
;
offset
++
)
msg_port_write
(
HTE
,
offset
,
0x
c33c
0000
);
}
msg_port_write
(
HTE
,
0x000200
A1
,
0xFFFF
1000
);
msg_port_write
(
HTE
,
0x000200
a1
,
0xffff
1000
);
msg_port_write
(
HTE
,
0x00020011
,
0x00011000
);
msg_port_write
(
HTE
,
0x00020011
,
0x00011100
);
...
...
arch/x86/cpu/quark/hte.h
浏览文件 @
10af8781
...
...
@@ -29,10 +29,10 @@ enum {
#define HTE_LOOP_CNT 5
/* random seed for victim */
#define HTE_LFSR_VICTIM_SEED 0x
F294BA
21
#define HTE_LFSR_VICTIM_SEED 0x
f294ba
21
/* random seed for aggressor */
#define HTE_LFSR_AGRESSOR_SEED 0x
EBA7492D
#define HTE_LFSR_AGRESSOR_SEED 0x
eba7492d
u32
hte_mem_init
(
struct
mrc_params
*
mrc_params
,
u8
flag
);
u16
hte_basic_write_read
(
struct
mrc_params
*
mrc_params
,
u32
addr
,
...
...
arch/x86/cpu/quark/mrc.c
浏览文件 @
10af8781
...
...
@@ -34,6 +34,7 @@
*/
#include <common.h>
#include <version.h>
#include <asm/arch/mrc.h>
#include <asm/arch/msg_port.h>
#include "mrc_util.h"
...
...
@@ -105,8 +106,8 @@ static void mrc_adjust_params(struct mrc_params *mrc_params)
* Column: 11 for 8Gbx8, else 10
*/
mrc_params
->
column_bits
[
0
]
=
(
(
dram_params
[
0
].
density
==
4
)
&&
(
dram_width
==
X8
)
)
?
(
11
)
:
(
10
)
;
(
dram_params
[
0
].
density
==
4
)
&&
(
dram_width
==
X8
)
?
11
:
10
;
/*
* Determine row bits:
...
...
@@ -117,9 +118,9 @@ static void mrc_adjust_params(struct mrc_params *mrc_params)
* 4Gbx16=15 4Gbx8=16
* 8Gbx16=16 8Gbx8=16
*/
mrc_params
->
row_bits
[
0
]
=
12
+
(
dram_params
[
0
].
density
)
+
(
((
dram_params
[
0
].
density
<
4
)
&&
(
dram_width
==
X8
)
)
?
(
1
)
:
(
0
))
;
mrc_params
->
row_bits
[
0
]
=
12
+
dram_params
[
0
].
density
+
(
dram_params
[
0
].
density
<
4
)
&&
(
dram_width
==
X8
)
?
1
:
0
;
/*
* Determine per-channel memory size:
...
...
@@ -137,7 +138,7 @@ static void mrc_adjust_params(struct mrc_params *mrc_params)
* 4Gb x16 0x040000000 (1024MB)
* 4Gb x8 0x080000000 (2048MB)
*/
mrc_params
->
channel_size
[
0
]
=
(
1
<<
dram_params
[
0
].
density
)
;
mrc_params
->
channel_size
[
0
]
=
1
<<
dram_params
[
0
].
density
;
mrc_params
->
channel_size
[
0
]
*=
(
dram_width
==
X8
)
?
2
:
1
;
mrc_params
->
channel_size
[
0
]
*=
(
rank_enables
==
0x3
)
?
2
:
1
;
mrc_params
->
channel_size
[
0
]
*=
(
channel_width
==
X16
)
?
1
:
2
;
...
...
@@ -192,7 +193,7 @@ void mrc_init(struct mrc_params *mrc_params)
ENTERFN
();
DPF
(
D_INFO
,
"MRC Version %04x %s %s
\n
"
,
MRC_VERSION
,
__DATE__
,
__TIME__
);
U_BOOT_DATE
,
U_BOOT_TIME
);
/* Set up the data structures used by mrc_mem_init() */
mrc_adjust_params
(
mrc_params
);
...
...
arch/x86/cpu/quark/mrc_util.c
浏览文件 @
10af8781
此差异已折叠。
点击以展开。
arch/x86/cpu/quark/mrc_util.h
浏览文件 @
10af8781
...
...
@@ -41,40 +41,6 @@
#define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__)
#define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__)
/* Generic Register Bits */
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
/* Message Bus Port */
#define MEM_CTLR 0x01
#define HOST_BRIDGE 0x03
...
...
arch/x86/cpu/quark/quark.c
浏览文件 @
10af8781
...
...
@@ -6,6 +6,8 @@
#include <common.h>
#include <mmc.h>
#include <netdev.h>
#include <phy.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/post.h>
...
...
@@ -116,3 +118,20 @@ int cpu_mmc_init(bd_t *bis)
return
pci_mmc_init
(
"Quark SDHCI"
,
mmc_supported
,
ARRAY_SIZE
(
mmc_supported
));
}
int
cpu_eth_init
(
bd_t
*
bis
)
{
u32
base
;
int
ret0
,
ret1
;
pci_read_config_dword
(
QUARK_EMAC0
,
PCI_BASE_ADDRESS_0
,
&
base
);
ret0
=
designware_initialize
(
base
,
PHY_INTERFACE_MODE_RMII
);
pci_read_config_dword
(
QUARK_EMAC1
,
PCI_BASE_ADDRESS_0
,
&
base
);
ret1
=
designware_initialize
(
base
,
PHY_INTERFACE_MODE_RMII
);
if
(
ret0
<
0
&&
ret1
<
0
)
return
-
1
;
else
return
0
;
}
arch/x86/cpu/quark/smc.c
浏览文件 @
10af8781
此差异已折叠。
点击以展开。
arch/x86/cpu/quark/smc.h
浏览文件 @
10af8781
...
...
@@ -24,46 +24,133 @@
#define DPMC1 0x07
#define DRFC 0x08
#define DSCH 0x09
#define DCAL 0x0
A
#define DRMC 0x0
B
#define PMSTS 0x0
C
#define DCO 0x0
F
#define DCAL 0x0
a
#define DRMC 0x0
b
#define PMSTS 0x0
c
#define DCO 0x0
f
#define DSTAT 0x20
#define SSKPD0 0x4
A
#define SSKPD1 0x4
B
#define SSKPD0 0x4
a
#define SSKPD1 0x4
b
#define DECCCTRL 0x60
#define DECCSTAT 0x61
#define DECCSBECNT 0x62
#define DECCSBECA 0x68
#define DECCSBECS 0x69
#define DECCDBECA 0x6
A
#define DECCDBECS 0x6
B
#define DECCDBECA 0x6
a
#define DECCDBECS 0x6
b
#define DFUSESTAT 0x70
#define SCRMSEED 0x80
#define SCRMLO 0x81
#define SCRMHI 0x82
/* DRP register defines */
#define DRP_RKEN0 (1 << 0)
#define DRP_RKEN1 (1 << 1)
#define DRP_PRI64BSPLITEN (1 << 13)
#define DRP_ADDRMAP_MAP0 (1 << 14)
#define DRP_ADDRMAP_MAP1 (1 << 15)
#define DRP_ADDRMAP_MASK 0x0000c000
/* DTR0 register defines */
#define DTR0_DFREQ_MASK 0x00000003
#define DTR0_TRP_MASK 0x000000f0
#define DTR0_TRCD_MASK 0x00000f00
#define DTR0_TCL_MASK 0x00007000
/* DTR1 register defines */
#define DTR1_TWCL_MASK 0x00000007
#define DTR1_TCMD_MASK 0x00000030
#define DTR1_TWTP_MASK 0x00000f00
#define DTR1_TCCD_12CLK (1 << 12)
#define DTR1_TCCD_18CLK (1 << 13)
#define DTR1_TCCD_MASK 0x00003000
#define DTR1_TFAW_MASK 0x000f0000
#define DTR1_TRAS_MASK 0x00f00000
#define DTR1_TRRD_MASK 0x03000000
#define DTR1_TRTP_MASK 0x70000000
/* DTR2 register defines */
#define DTR2_TRRDR_MASK 0x00000007
#define DTR2_TWWDR_MASK 0x00000700
#define DTR2_TRWDR_MASK 0x000f0000
/* DTR3 register defines */
#define DTR3_TWRDR_MASK 0x00000007
#define DTR3_TXXXX_MASK 0x00000070
#define DTR3_TRWSR_MASK 0x00000f00
#define DTR3_TWRSR_MASK 0x0001e000
#define DTR3_TXP_MASK 0x00c00000
/* DTR4 register defines */
#define DTR4_WRODTSTRT_MASK 0x00000003
#define DTR4_WRODTSTOP_MASK 0x00000070
#define DTR4_XXXX1_MASK 0x00000700
#define DTR4_XXXX2_MASK 0x00007000
#define DTR4_ODTDIS (1 << 15)
#define DTR4_TRGSTRDIS (1 << 16)
/* DPMC0 register defines */
#define DPMC0_PCLSTO_MASK 0x00070000
#define DPMC0_PREAPWDEN (1 << 21)
#define DPMC0_DYNSREN (1 << 23)
#define DPMC0_CLKGTDIS (1 << 24)
#define DPMC0_DISPWRDN (1 << 25)
#define DPMC0_ENPHYCLKGATE (1 << 29)
/* DRFC register defines */
#define DRFC_TREFI_MASK 0x00007000
#define DRFC_REFDBTCLR (1 << 21)
/* DSCH register defines */
#define DSCH_OOODIS (1 << 8)
#define DSCH_OOOST3DIS (1 << 9)
#define DSCH_NEWBYPDIS (1 << 12)
/* DCAL register defines */
#define DCAL_ZQCINT_MASK 0x00000700
#define DCAL_SRXZQCL_MASK 0x00003000
/* DRMC register defines */
#define DRMC_CKEMODE (1 << 4)
#define DRMC_ODTMODE (1 << 12)
#define DRMC_COLDWAKE (1 << 16)
/* PMSTS register defines */
#define PMSTS_DISR (1 << 0)
/* DCO register defines */
#define DCO_DRPLOCK (1 << 0)
#define DCO_CPGCLOCK (1 << 8)
#define DCO_PMICTL (1 << 28)
#define DCO_PMIDIS (1 << 29)
#define DCO_IC (1 << 31)
/* DECCCTRL register defines */
#define DECCCTRL_SBEEN (1 << 0)
#define DECCCTRL_DBEEN (1 << 1)
#define DECCCTRL_ENCBGEN (1 << 17)
/* DRAM init command */
#define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6))
#define DCMD_REF(rnk) (1 | ((rnk) << 22))
#define DCMD_PRE(rnk) (2 | ((rnk) << 22))
#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (
BIT1
0 << 6))
#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (
0x40
0 << 6))
#define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6))
#define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6))
#define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6))
#define DCMD_ZQCS(rnk) (6 | ((rnk) << 22))
#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (
BIT1
0 << 6))
#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (
0x40
0 << 6))
#define DCMD_NOP(rnk) (7 | ((rnk) << 22))
#define DDR3_EMRS1_DIC_40
(0)
#define DDR3_EMRS1_DIC_34
(1)
#define DDR3_EMRS1_DIC_40
0
#define DDR3_EMRS1_DIC_34
1
#define DDR3_EMRS1_RTTNOM_0
(0)
#define DDR3_EMRS1_RTTNOM_60
(0x04)
#define DDR3_EMRS1_RTTNOM_120
(0x40)
#define DDR3_EMRS1_RTTNOM_40
(0x44)
#define DDR3_EMRS1_RTTNOM_20
(0x200)
#define DDR3_EMRS1_RTTNOM_30
(0x204)
#define DDR3_EMRS1_RTTNOM_0
0
#define DDR3_EMRS1_RTTNOM_60
0x04
#define DDR3_EMRS1_RTTNOM_120
0x40
#define DDR3_EMRS1_RTTNOM_40
0x44
#define DDR3_EMRS1_RTTNOM_20
0x200
#define DDR3_EMRS1_RTTNOM_30
0x204
#define DDR3_EMRS2_RTTWR_60 (1 << 9)
#define DDR3_EMRS2_RTTWR_120 (1 << 10)
...
...
@@ -80,87 +167,87 @@
#define DQOBSCKEBBCTL 0x0000
#define DQDLLTXCTL 0x0004
#define DQDLLRXCTL 0x0008
#define DQMDLLCTL 0x000
C
#define DQMDLLCTL 0x000
c
#define B0RXIOBUFCTL 0x0010
#define B0VREFCTL 0x0014
#define B0RXOFFSET1 0x0018
#define B0RXOFFSET0 0x001
C
#define B0RXOFFSET0 0x001
c
#define B1RXIOBUFCTL 0x0020
#define B1VREFCTL 0x0024
#define B1RXOFFSET1 0x0028
#define B1RXOFFSET0 0x002
C
#define B1RXOFFSET0 0x002
c
#define DQDFTCTL 0x0030
#define DQTRAINSTS 0x0034
#define B1DLLPICODER0 0x0038
#define B0DLLPICODER0 0x003
C
#define B0DLLPICODER0 0x003
c
#define B1DLLPICODER1 0x0040
#define B0DLLPICODER1 0x0044
#define B1DLLPICODER2 0x0048
#define B0DLLPICODER2 0x004
C
#define B0DLLPICODER2 0x004
c
#define B1DLLPICODER3 0x0050
#define B0DLLPICODER3 0x0054
#define B1RXDQSPICODE 0x0058
#define B0RXDQSPICODE 0x005
C
#define B0RXDQSPICODE 0x005
c
#define B1RXDQPICODER32 0x0060
#define B1RXDQPICODER10 0x0064
#define B0RXDQPICODER32 0x0068
#define B0RXDQPICODER10 0x006
C
#define B0RXDQPICODER10 0x006
c
#define B01PTRCTL0 0x0070
#define B01PTRCTL1 0x0074
#define B01DBCTL0 0x0078
#define B01DBCTL1 0x007
C
#define B01DBCTL1 0x007
c
#define B0LATCTL0 0x0080
#define B1LATCTL0 0x0084
#define B01LATCTL1 0x0088
#define B0ONDURCTL 0x008
C
#define B0ONDURCTL 0x008
c
#define B1ONDURCTL 0x0090
#define B0OVRCTL 0x0094
#define B1OVRCTL 0x0098
#define DQCTL 0x009
C
#define B0RK2RKCHGPTRCTRL 0x00
A
0
#define B1RK2RKCHGPTRCTRL 0x00
A
4
#define DQRK2RKCTL 0x00
A
8
#define DQRK2RKPTRCTL 0x00
AC
#define B0RK2RKLAT 0x00
B
0
#define B1RK2RKLAT 0x00
B
4
#define DQCLKALIGNREG0 0x00
B
8
#define DQCLKALIGNREG1 0x00
BC
#define DQCLKALIGNREG2 0x00
C
0
#define DQCLKALIGNSTS0 0x00
C
4
#define DQCLKALIGNSTS1 0x00
C
8
#define DQCLKGATE 0x00
CC
#define B0COMPSLV1 0x00
D
0
#define B1COMPSLV1 0x00
D
4
#define B0COMPSLV2 0x00
D
8
#define B1COMPSLV2 0x00
DC
#define B0COMPSLV3 0x00
E
0
#define B1COMPSLV3 0x00
E
4
#define DQVISALANECR0TOP 0x00
E
8
#define DQVISALANECR1TOP 0x00
EC
#define DQVISACONTROLCRTOP 0x00
F
0
#define DQVISALANECR0BL 0x00
F
4
#define DQVISALANECR1BL 0x00
F
8
#define DQVISACONTROLCRBL 0x00
FC
#define DQTIMINGCTRL 0x010
C
#define DQCTL 0x009
c
#define B0RK2RKCHGPTRCTRL 0x00
a
0
#define B1RK2RKCHGPTRCTRL 0x00
a
4
#define DQRK2RKCTL 0x00
a
8
#define DQRK2RKPTRCTL 0x00
ac
#define B0RK2RKLAT 0x00
b
0
#define B1RK2RKLAT 0x00
b
4
#define DQCLKALIGNREG0 0x00
b
8
#define DQCLKALIGNREG1 0x00
bc
#define DQCLKALIGNREG2 0x00
c
0
#define DQCLKALIGNSTS0 0x00
c
4
#define DQCLKALIGNSTS1 0x00
c
8
#define DQCLKGATE 0x00
cc
#define B0COMPSLV1 0x00
d
0
#define B1COMPSLV1 0x00
d
4
#define B0COMPSLV2 0x00
d
8
#define B1COMPSLV2 0x00
dc
#define B0COMPSLV3 0x00
e
0
#define B1COMPSLV3 0x00
e
4
#define DQVISALANECR0TOP 0x00
e
8
#define DQVISALANECR1TOP 0x00
ec
#define DQVISACONTROLCRTOP 0x00
f
0
#define DQVISALANECR0BL 0x00
f
4
#define DQVISALANECR1BL 0x00
f
8
#define DQVISACONTROLCRBL 0x00
fc
#define DQTIMINGCTRL 0x010
c
/* CH0-ECC */
#define ECCDLLTXCTL 0x2004
#define ECCDLLRXCTL 0x2008
#define ECCMDLLCTL 0x200
C
#define ECCMDLLCTL 0x200
c
#define ECCB1DLLPICODER0 0x2038
#define ECCB1DLLPICODER1 0x2040
#define ECCB1DLLPICODER2 0x2048
#define ECCB1DLLPICODER3 0x2050
#define ECCB01DBCTL0 0x2078
#define ECCB01DBCTL1 0x207
C
#define ECCCLKALIGNREG0 0x20
B
8
#define ECCCLKALIGNREG1 0x20
BC
#define ECCCLKALIGNREG2 0x20
C
0
#define ECCB01DBCTL1 0x207
c
#define ECCCLKALIGNREG0 0x20
b
8
#define ECCCLKALIGNREG1 0x20
bc
#define ECCCLKALIGNREG2 0x20
c
0
/* CH0-CMD */
#define CMDOBSCKEBBCTL 0x4800
#define CMDDLLTXCTL 0x4808
#define CMDDLLRXCTL 0x480
C
#define CMDDLLRXCTL 0x480
c
#define CMDMDLLCTL 0x4810
#define CMDRCOMPODT 0x4814
#define CMDDLLPICODER0 0x4820
...
...
@@ -170,30 +257,30 @@
#define CMDCLKALIGNREG0 0x4850
#define CMDCLKALIGNREG1 0x4854
#define CMDCLKALIGNREG2 0x4858
#define CMDPMCONFIG0 0x485
C
#define CMDPMCONFIG0 0x485
c
#define CMDPMDLYREG0 0x4860
#define CMDPMDLYREG1 0x4864
#define CMDPMDLYREG2 0x4868
#define CMDPMDLYREG3 0x486
C
#define CMDPMDLYREG3 0x486
c
#define CMDPMDLYREG4 0x4870
#define CMDCLKALIGNSTS0 0x4874
#define CMDCLKALIGNSTS1 0x4878
#define CMDPMSTS0 0x487
C
#define CMDPMSTS0 0x487
c
#define CMDPMSTS1 0x4880
#define CMDCOMPSLV 0x4884
#define CMDBONUS0 0x488
C
#define CMDBONUS0 0x488
c
#define CMDBONUS1 0x4890
#define CMDVISALANECR0 0x4894
#define CMDVISALANECR1 0x4898
#define CMDVISACONTROLCR 0x489
C
#define CMDCLKGATE 0x48
A
0
#define CMDTIMINGCTRL 0x48
A
4
#define CMDVISACONTROLCR 0x489
c
#define CMDCLKGATE 0x48
a
0
#define CMDTIMINGCTRL 0x48
a
4
/* CH0-CLK-CTL */
#define CCOBSCKEBBCTL 0x5800
#define CCRCOMPIO 0x5804
#define CCDLLTXCTL 0x5808
#define CCDLLRXCTL 0x580
C
#define CCDLLRXCTL 0x580
c
#define CCMDLLCTL 0x5810
#define CCRCOMPODT 0x5814
#define CCDLLPICODER0 0x5820
...
...
@@ -205,123 +292,123 @@
#define CCCLKALIGNREG0 0x5850
#define CCCLKALIGNREG1 0x5854
#define CCCLKALIGNREG2 0x5858
#define CCPMCONFIG0 0x585
C
#define CCPMCONFIG0 0x585
c
#define CCPMDLYREG0 0x5860
#define CCPMDLYREG1 0x5864
#define CCPMDLYREG2 0x5868
#define CCPMDLYREG3 0x586
C
#define CCPMDLYREG3 0x586
c
#define CCPMDLYREG4 0x5870
#define CCCLKALIGNSTS0 0x5874
#define CCCLKALIGNSTS1 0x5878
#define CCPMSTS0 0x587
C
#define CCPMSTS0 0x587
c
#define CCPMSTS1 0x5880
#define CCCOMPSLV1 0x5884
#define CCCOMPSLV2 0x5888
#define CCCOMPSLV3 0x588
C
#define CCCOMPSLV3 0x588
c
#define CCBONUS0 0x5894
#define CCBONUS1 0x5898
#define CCVISALANECR0 0x589
C
#define CCVISALANECR1 0x58
A
0
#define CCVISACONTROLCR 0x58
A
4
#define CCCLKGATE 0x58
A
8
#define CCTIMINGCTL 0x58
AC
#define CCVISALANECR0 0x589
c
#define CCVISALANECR1 0x58
a
0
#define CCVISACONTROLCR 0x58
a
4
#define CCCLKGATE 0x58
a
8
#define CCTIMINGCTL 0x58
ac
/* COMP */
#define CMPCTRL 0x6800
#define SOFTRSTCNTL 0x6804
#define MSCNTR 0x6808
#define NMSCNTRL 0x680
C
#define NMSCNTRL 0x680
c
#define LATCH1CTL 0x6814
#define COMPVISALANECR0 0x681
C
#define COMPVISALANECR0 0x681
c
#define COMPVISALANECR1 0x6820
#define COMPVISACONTROLCR 0x6824
#define COMPBONUS0 0x6830
#define TCOCNTCTRL 0x683
C
#define TCOCNTCTRL 0x683
c
#define DQANAODTPUCTL 0x6840
#define DQANAODTPDCTL 0x6844
#define DQANADRVPUCTL 0x6848
#define DQANADRVPDCTL 0x684
C
#define DQANADRVPDCTL 0x684
c
#define DQANADLYPUCTL 0x6850
#define DQANADLYPDCTL 0x6854
#define DQANATCOPUCTL 0x6858
#define DQANATCOPDCTL 0x685
C
#define DQANATCOPDCTL 0x685
c
#define CMDANADRVPUCTL 0x6868
#define CMDANADRVPDCTL 0x686
C
#define CMDANADRVPDCTL 0x686
c
#define CMDANADLYPUCTL 0x6870
#define CMDANADLYPDCTL 0x6874
#define CLKANAODTPUCTL 0x6880
#define CLKANAODTPDCTL 0x6884
#define CLKANADRVPUCTL 0x6888
#define CLKANADRVPDCTL 0x688
C
#define CLKANADRVPDCTL 0x688
c
#define CLKANADLYPUCTL 0x6890
#define CLKANADLYPDCTL 0x6894
#define CLKANATCOPUCTL 0x6898
#define CLKANATCOPDCTL 0x689
C
#define DQSANAODTPUCTL 0x68
A
0
#define DQSANAODTPDCTL 0x68
A
4
#define DQSANADRVPUCTL 0x68
A
8
#define DQSANADRVPDCTL 0x68
AC
#define DQSANADLYPUCTL 0x68
B
0
#define DQSANADLYPDCTL 0x68
B
4
#define DQSANATCOPUCTL 0x68
B
8
#define DQSANATCOPDCTL 0x68
BC
#define CTLANADRVPUCTL 0x68
C
8
#define CTLANADRVPDCTL 0x68
CC
#define CTLANADLYPUCTL 0x68
D
0
#define CTLANADLYPDCTL 0x68
D
4
#define CHNLBUFSTATIC 0x68
F
0
#define COMPOBSCNTRL 0x68
F
4
#define COMPBUFFDBG0 0x68
F
8
#define COMPBUFFDBG1 0x68
FC
#define CLKANATCOPDCTL 0x689
c
#define DQSANAODTPUCTL 0x68
a
0
#define DQSANAODTPDCTL 0x68
a
4
#define DQSANADRVPUCTL 0x68
a
8
#define DQSANADRVPDCTL 0x68
ac
#define DQSANADLYPUCTL 0x68
b
0
#define DQSANADLYPDCTL 0x68
b
4
#define DQSANATCOPUCTL 0x68
b
8
#define DQSANATCOPDCTL 0x68
bc
#define CTLANADRVPUCTL 0x68
c
8
#define CTLANADRVPDCTL 0x68
cc
#define CTLANADLYPUCTL 0x68
d
0
#define CTLANADLYPDCTL 0x68
d
4
#define CHNLBUFSTATIC 0x68
f
0
#define COMPOBSCNTRL 0x68
f
4
#define COMPBUFFDBG0 0x68
f
8
#define COMPBUFFDBG1 0x68
fc
#define CFGMISCCH0 0x6900
#define COMPEN0CH0 0x6904
#define COMPEN1CH0 0x6908
#define COMPEN2CH0 0x690
C
#define COMPEN2CH0 0x690
c
#define STATLEGEN0CH0 0x6910
#define STATLEGEN1CH0 0x6914
#define DQVREFCH0 0x6918
#define CMDVREFCH0 0x691
C
#define CMDVREFCH0 0x691
c
#define CLKVREFCH0 0x6920
#define DQSVREFCH0 0x6924
#define CTLVREFCH0 0x6928
#define TCOVREFCH0 0x692
C
#define TCOVREFCH0 0x692
c
#define DLYSELCH0 0x6930
#define TCODRAMBUFODTCH0 0x6934
#define CCBUFODTCH0 0x6938
#define RXOFFSETCH0 0x693
C
#define RXOFFSETCH0 0x693
c
#define DQODTPUCTLCH0 0x6940
#define DQODTPDCTLCH0 0x6944
#define DQDRVPUCTLCH0 0x6948
#define DQDRVPDCTLCH0 0x694
C
#define DQDRVPDCTLCH0 0x694
c
#define DQDLYPUCTLCH0 0x6950
#define DQDLYPDCTLCH0 0x6954
#define DQTCOPUCTLCH0 0x6958
#define DQTCOPDCTLCH0 0x695
C
#define DQTCOPDCTLCH0 0x695
c
#define CMDDRVPUCTLCH0 0x6968
#define CMDDRVPDCTLCH0 0x696
C
#define CMDDRVPDCTLCH0 0x696
c
#define CMDDLYPUCTLCH0 0x6970
#define CMDDLYPDCTLCH0 0x6974
#define CLKODTPUCTLCH0 0x6980
#define CLKODTPDCTLCH0 0x6984
#define CLKDRVPUCTLCH0 0x6988
#define CLKDRVPDCTLCH0 0x698
C
#define CLKDRVPDCTLCH0 0x698
c
#define CLKDLYPUCTLCH0 0x6990
#define CLKDLYPDCTLCH0 0x6994
#define CLKTCOPUCTLCH0 0x6998
#define CLKTCOPDCTLCH0 0x699
C
#define DQSODTPUCTLCH0 0x69
A
0
#define DQSODTPDCTLCH0 0x69
A
4
#define DQSDRVPUCTLCH0 0x69
A
8
#define DQSDRVPDCTLCH0 0x69
AC
#define DQSDLYPUCTLCH0 0x69
B
0
#define DQSDLYPDCTLCH0 0x69
B
4
#define DQSTCOPUCTLCH0 0x69
B
8
#define DQSTCOPDCTLCH0 0x69
BC
#define CTLDRVPUCTLCH0 0x69
C
8
#define CTLDRVPDCTLCH0 0x69
CC
#define CTLDLYPUCTLCH0 0x69
D
0
#define CTLDLYPDCTLCH0 0x69
D
4
#define FNLUPDTCTLCH0 0x69
F
0
#define CLKTCOPDCTLCH0 0x699
c
#define DQSODTPUCTLCH0 0x69
a
0
#define DQSODTPDCTLCH0 0x69
a
4
#define DQSDRVPUCTLCH0 0x69
a
8
#define DQSDRVPDCTLCH0 0x69
ac
#define DQSDLYPUCTLCH0 0x69
b
0
#define DQSDLYPDCTLCH0 0x69
b
4
#define DQSTCOPUCTLCH0 0x69
b
8
#define DQSTCOPDCTLCH0 0x69
bc
#define CTLDRVPUCTLCH0 0x69
c
8
#define CTLDRVPDCTLCH0 0x69
cc
#define CTLDLYPUCTLCH0 0x69
d
0
#define CTLDLYPDCTLCH0 0x69
d
4
#define FNLUPDTCTLCH0 0x69
f
0
/* PLL */
#define MPLLCTRL0 0x7800
...
...
@@ -332,17 +419,17 @@
#define MPLLDFT 0x7828
#define MPLLMON0CTL 0x7830
#define MPLLMON1CTL 0x7838
#define MPLLMON2CTL 0x783
C
#define MPLLMON2CTL 0x783
c
#define SFRTRIM 0x7850
#define MPLLDFTOUT0 0x7858
#define MPLLDFTOUT1 0x785
C
#define MPLLDFTOUT1 0x785
c
#define MASTERRSTN 0x7880
#define PLLLOCKDEL 0x7884
#define SFRDEL 0x7888
#define CRUVISALANECR0 0x78
F
0
#define CRUVISALANECR1 0x78
F
4
#define CRUVISACONTROLCR 0x78
F
8
#define IOSFVISALANECR0 0x78
FC
#define CRUVISALANECR0 0x78
f
0
#define CRUVISALANECR1 0x78
f
4
#define CRUVISACONTROLCR 0x78
f
8
#define IOSFVISALANECR0 0x78
fc
#define IOSFVISALANECR1 0x7900
#define IOSFVISACONTROLCR 0x7904
...
...
@@ -350,7 +437,7 @@
/* DRAM Specific Message Bus OpCodes */
#define MSG_OP_DRAM_INIT 0x68
#define MSG_OP_DRAM_WAKE 0x
CA
#define MSG_OP_DRAM_WAKE 0x
ca
#define SAMPLE_SIZE 6
...
...
@@ -377,9 +464,9 @@
/* offset into "vref_codes[]" for minimum allowed VREF setting */
#define VREF_MIN 0x00
/* offset into "vref_codes[]" for maximum allowed VREF setting */
#define VREF_MAX 0x3
F
#define VREF_MAX 0x3
f
#define RDQS_MIN 0x00
/* minimum RDQS delay value */
#define RDQS_MAX 0x3
F
/* maximum RDQS delay value */
#define RDQS_MAX 0x3
f
/* maximum RDQS delay value */
/* how many WDQ codes to jump while margining */
#define WDQ_STEP 1
...
...
doc/README.drivers.eth
浏览文件 @
10af8781
...
...
@@ -43,15 +43,16 @@ int ape_register(bd_t *bis, int iobase)
{
struct ape_priv *priv;
struct eth_device *dev;
struct mii_dev *bus;
priv = malloc(sizeof(*priv));
if (priv == NULL)
return
1
;
return
-ENOMEM
;
dev = malloc(sizeof(*dev));
if (dev == NULL) {
free(priv);
return
1
;
return
-ENOMEM
;
}
/* setup whatever private state you need */
...
...
@@ -59,7 +60,8 @@ int ape_register(bd_t *bis, int iobase)
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "APE");
/* if your device has dedicated hardware storage for the
/*
* if your device has dedicated hardware storage for the
* MAC, read it and initialize dev->enetaddr with it
*/
ape_mac_read(dev->enetaddr);
...
...
@@ -74,8 +76,17 @@ int ape_register(bd_t *bis, int iobase)
eth_register(dev);
#ifdef CONFIG_CMD_MII)
miiphy_register(dev->name, ape_mii_read, ape_mii_write);
#ifdef CONFIG_PHYLIB
bus = mdio_alloc();
if (!bus) {
free(priv);
free(dev);
return -ENOMEM;
}
bus->read = ape_mii_read;
bus->write = ape_mii_write;
mdio_register(bus);
#endif
return 1;
...
...
@@ -166,25 +177,33 @@ some net operation (ping / tftp / whatever...)
eth_halt()
dev->halt()
-----------------------------
CONFIG_
MII
/ CONFIG_CMD_MII
-----------------------------
-----------------------------
---
CONFIG_
PHYLIB
/ CONFIG_CMD_MII
-----------------------------
---
If your device supports banging arbitrary values on the MII bus (pretty much
every device does), you should add support for the mii command. Doing so is
fairly trivial and makes debugging mii issues a lot easier at runtime.
After you have called eth_register() in your driver's register function, add
a call to miiphy_register() like so:
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, mii_read, mii_write);
#endif
a call to mdio_alloc() and mdio_register() like so:
bus = mdio_alloc();
if (!bus) {
free(priv);
free(dev);
return -ENOMEM;
}
bus->read = ape_mii_read;
bus->write = ape_mii_write;
mdio_register(bus);
And then define the mii_read and mii_write functions if you haven't already.
Their syntax is straightforward:
int mii_read(char *devname, uchar addr, uchar reg, ushort *val);
int mii_write(char *devname, uchar addr, uchar reg, ushort val);
int mii_read(struct mii_dev *bus, int addr, int devad, int reg);
int mii_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 val);
The read function should read the register 'reg' from the phy at address 'addr'
and
store the result in the pointer 'val'. The implementation for the write
function
should logically follow.
and
return the result to its caller. The implementation for the write function
should logically follow.
doc/README.x86
浏览文件 @
10af8781
...
...
@@ -105,6 +105,13 @@ in this FSP package too.
Rename the first one to fsp.bin and second one to cmc.bin and put them in the
board directory.
Note the FSP release version 001 has a bug which could cause random endless
loop during the FspInit call. This bug was published by Intel although Intel
did not describe any details. We need manually apply the patch to the FSP
binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
binary, change the following five bytes values from orginally E8 42 FF FF FF
to B8 00 80 0B 00.
Now you can build U-Boot and obtain u-boot.rom
$ make crownbay_defconfig
...
...
drivers/net/Makefile
浏览文件 @
10af8781
...
...
@@ -46,6 +46,7 @@ obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
obj-$(CONFIG_DRIVER_AX88796L)
+=
ax88796.o ne2000_base.o
obj-$(CONFIG_NETCONSOLE)
+=
netconsole.o
obj-$(CONFIG_NS8382X)
+=
ns8382x.o
obj-$(CONFIG_PCH_GBE)
+=
pch_gbe.o
obj-$(CONFIG_PCNET)
+=
pcnet.o
obj-$(CONFIG_RTL8139)
+=
rtl8139.o
obj-$(CONFIG_RTL8169)
+=
rtl8169.o
...
...
drivers/net/e1000.h
浏览文件 @
10af8781
...
...
@@ -430,12 +430,11 @@ struct e1000_phy_stats {
#define ENET_HEADER_SIZE 14
#define MAXIMUM_ETHERNET_FRAME_SIZE 1518
/* With FCS */
#define MINIMUM_ETHERNET_FRAME_SIZE 64
/* With FCS */
#define ETHERNET_FCS_SIZE 4
#define MAXIMUM_ETHERNET_PACKET_SIZE \
(MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE
)
(MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN
)
#define MINIMUM_ETHERNET_PACKET_SIZE \
(MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE
)
#define CRC_LENGTH ETH
ERNET_FCS_SIZE
(MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN
)
#define CRC_LENGTH ETH
_FCS_LEN
#define MAX_JUMBO_FRAME_SIZE 0x3F00
/* 802.1q VLAN Packet Sizes */
...
...
drivers/net/pch_gbe.c
0 → 100644
浏览文件 @
10af8781
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <pci.h>
#include <malloc.h>
#include <miiphy.h>
#include "pch_gbe.h"
#if !defined(CONFIG_PHYLIB)
# error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
#endif
static
struct
pci_device_id
supported
[]
=
{
{
PCI_VENDOR_ID_INTEL
,
PCI_DEVICE_ID_INTEL_TCF_GBE
},
{
}
};
static
void
pch_gbe_mac_read
(
struct
pch_gbe_regs
*
mac_regs
,
u8
*
addr
)
{
u32
macid_hi
,
macid_lo
;
macid_hi
=
readl
(
&
mac_regs
->
mac_adr
[
0
].
high
);
macid_lo
=
readl
(
&
mac_regs
->
mac_adr
[
0
].
low
)
&
0xffff
;
debug
(
"pch_gbe: macid_hi %#x macid_lo %#x
\n
"
,
macid_hi
,
macid_lo
);
addr
[
0
]
=
(
u8
)(
macid_hi
&
0xff
);
addr
[
1
]
=
(
u8
)((
macid_hi
>>
8
)
&
0xff
);
addr
[
2
]
=
(
u8
)((
macid_hi
>>
16
)
&
0xff
);
addr
[
3
]
=
(
u8
)((
macid_hi
>>
24
)
&
0xff
);
addr
[
4
]
=
(
u8
)(
macid_lo
&
0xff
);
addr
[
5
]
=
(
u8
)((
macid_lo
>>
8
)
&
0xff
);
}
static
int
pch_gbe_mac_write
(
struct
pch_gbe_regs
*
mac_regs
,
u8
*
addr
)
{
u32
macid_hi
,
macid_lo
;
ulong
start
;
macid_hi
=
addr
[
0
]
+
(
addr
[
1
]
<<
8
)
+
(
addr
[
2
]
<<
16
)
+
(
addr
[
3
]
<<
24
);
macid_lo
=
addr
[
4
]
+
(
addr
[
5
]
<<
8
);
writel
(
macid_hi
,
&
mac_regs
->
mac_adr
[
0
].
high
);
writel
(
macid_lo
,
&
mac_regs
->
mac_adr
[
0
].
low
);
writel
(
0xfffe
,
&
mac_regs
->
addr_mask
);
start
=
get_timer
(
0
);
while
(
get_timer
(
start
)
<
PCH_GBE_TIMEOUT
)
{
if
(
!
(
readl
(
&
mac_regs
->
addr_mask
)
&
PCH_GBE_BUSY
))
return
0
;
udelay
(
10
);
}
return
-
ETIME
;
}
static
int
pch_gbe_reset
(
struct
eth_device
*
dev
)
{
struct
pch_gbe_priv
*
priv
=
dev
->
priv
;
struct
pch_gbe_regs
*
mac_regs
=
priv
->
mac_regs
;
ulong
start
;
priv
->
rx_idx
=
0
;
priv
->
tx_idx
=
0
;
writel
(
PCH_GBE_ALL_RST
,
&
mac_regs
->
reset
);
/*
* Configure the MAC to RGMII mode after reset
*
* For some unknown reason, we must do the configuration here right
* after resetting the whole MAC, otherwise the reset bit in the RESET
* register will never be cleared by the hardware. And there is another
* way of having the same magic, that is to configure the MODE register
* to have the MAC work in MII/GMII mode, which is how current Linux
* pch_gbe driver does. Since anyway we need program the MAC to RGMII
* mode in the driver, we just do it here.
*
* Note: this behavior is not documented in the hardware manual.
*/
writel
(
PCH_GBE_RGMII_MODE_RGMII
|
PCH_GBE_CHIP_TYPE_INTERNAL
,
&
mac_regs
->
rgmii_ctrl
);
start
=
get_timer
(
0
);
while
(
get_timer
(
start
)
<
PCH_GBE_TIMEOUT
)
{
if
(
!
(
readl
(
&
mac_regs
->
reset
)
&
PCH_GBE_ALL_RST
))
{
/*
* Soft reset clears hardware MAC address registers,
* so we have to reload MAC address here in order to
* make linux pch_gbe driver happy.
*/
return
pch_gbe_mac_write
(
mac_regs
,
dev
->
enetaddr
);
}
udelay
(
10
);
}
debug
(
"pch_gbe: reset timeout
\n
"
);
return
-
ETIME
;
}
static
void
pch_gbe_rx_descs_init
(
struct
eth_device
*
dev
)
{
struct
pch_gbe_priv
*
priv
=
dev
->
priv
;
struct
pch_gbe_regs
*
mac_regs
=
priv
->
mac_regs
;
struct
pch_gbe_rx_desc
*
rx_desc
=
&
priv
->
rx_desc
[
0
];
int
i
;
memset
(
rx_desc
,
0
,
sizeof
(
struct
pch_gbe_rx_desc
)
*
PCH_GBE_DESC_NUM
);
for
(
i
=
0
;
i
<
PCH_GBE_DESC_NUM
;
i
++
)
rx_desc
->
buffer_addr
=
pci_phys_to_mem
(
priv
->
bdf
,
(
u32
)(
priv
->
rx_buff
[
i
]));
writel
(
pci_phys_to_mem
(
priv
->
bdf
,
(
u32
)
rx_desc
),
&
mac_regs
->
rx_dsc_base
);
writel
(
sizeof
(
struct
pch_gbe_rx_desc
)
*
(
PCH_GBE_DESC_NUM
-
1
),
&
mac_regs
->
rx_dsc_size
);
writel
(
pci_phys_to_mem
(
priv
->
bdf
,
(
u32
)(
rx_desc
+
1
)),
&
mac_regs
->
rx_dsc_sw_p
);
}
static
void
pch_gbe_tx_descs_init
(
struct
eth_device
*
dev
)
{
struct
pch_gbe_priv
*
priv
=
dev
->
priv
;
struct
pch_gbe_regs
*
mac_regs
=
priv
->
mac_regs
;
struct
pch_gbe_tx_desc
*
tx_desc
=
&
priv
->
tx_desc
[
0
];
memset
(
tx_desc
,
0
,
sizeof
(
struct
pch_gbe_tx_desc
)
*
PCH_GBE_DESC_NUM
);
writel
(
pci_phys_to_mem
(
priv
->
bdf
,
(
u32
)
tx_desc
),
&
mac_regs
->
tx_dsc_base
);
writel
(
sizeof
(
struct
pch_gbe_tx_desc
)
*
(
PCH_GBE_DESC_NUM
-
1
),
&
mac_regs
->
tx_dsc_size
);
writel
(
pci_phys_to_mem
(
priv
->
bdf
,
(
u32
)(
tx_desc
+
1
)),
&
mac_regs
->
tx_dsc_sw_p
);
}
static
void
pch_gbe_adjust_link
(
struct
pch_gbe_regs
*
mac_regs
,
struct
phy_device
*
phydev
)
{
if
(
!
phydev
->
link
)
{
printf
(
"%s: No link.
\n
"
,
phydev
->
dev
->
name
);
return
;
}
clrbits_le32
(
&
mac_regs
->
rgmii_ctrl
,
PCH_GBE_RGMII_RATE_2_5M
|
PCH_GBE_CRS_SEL
);
clrbits_le32
(
&
mac_regs
->
mode
,
PCH_GBE_MODE_GMII_ETHER
|
PCH_GBE_MODE_FULL_DUPLEX
);
switch
(
phydev
->
speed
)
{
case
1000
:
setbits_le32
(
&
mac_regs
->
rgmii_ctrl
,
PCH_GBE_RGMII_RATE_125M
);
setbits_le32
(
&
mac_regs
->
mode
,
PCH_GBE_MODE_GMII_ETHER
);
break
;
case
100
:
setbits_le32
(
&
mac_regs
->
rgmii_ctrl
,
PCH_GBE_RGMII_RATE_25M
);
setbits_le32
(
&
mac_regs
->
mode
,
PCH_GBE_MODE_MII_ETHER
);
break
;
case
10
:
setbits_le32
(
&
mac_regs
->
rgmii_ctrl
,
PCH_GBE_RGMII_RATE_2_5M
);
setbits_le32
(
&
mac_regs
->
mode
,
PCH_GBE_MODE_MII_ETHER
);
break
;
}
if
(
phydev
->
duplex
)
{
setbits_le32
(
&
mac_regs
->
rgmii_ctrl
,
PCH_GBE_CRS_SEL
);
setbits_le32
(
&
mac_regs
->
mode
,
PCH_GBE_MODE_FULL_DUPLEX
);
}
printf
(
"Speed: %d, %s duplex
\n
"
,
phydev
->
speed
,
(
phydev
->
duplex
)
?
"full"
:
"half"
);
return
;
}
static
int
pch_gbe_init
(
struct
eth_device
*
dev
,
bd_t
*
bis
)
{
struct
pch_gbe_priv
*
priv
=
dev
->
priv
;
struct
pch_gbe_regs
*
mac_regs
=
priv
->
mac_regs
;
if
(
pch_gbe_reset
(
dev
))
return
-
1
;
pch_gbe_rx_descs_init
(
dev
);
pch_gbe_tx_descs_init
(
dev
);
/* Enable frame bursting */
writel
(
PCH_GBE_MODE_FR_BST
,
&
mac_regs
->
mode
);
/* Disable TCP/IP accelerator */
writel
(
PCH_GBE_RX_TCPIPACC_OFF
,
&
mac_regs
->
tcpip_acc
);
/* Disable RX flow control */
writel
(
0
,
&
mac_regs
->
rx_fctrl
);
/* Configure RX/TX mode */
writel
(
PCH_GBE_RH_ALM_EMP_16
|
PCH_GBE_RH_ALM_FULL_16
|
PCH_GBE_RH_RD_TRG_32
,
&
mac_regs
->
rx_mode
);
writel
(
PCH_GBE_TM_TH_TX_STRT_32
|
PCH_GBE_TM_TH_ALM_EMP_16
|
PCH_GBE_TM_TH_ALM_FULL_32
|
PCH_GBE_TM_ST_AND_FD
|
PCH_GBE_TM_SHORT_PKT
,
&
mac_regs
->
tx_mode
);
/* Start up the PHY */
if
(
phy_startup
(
priv
->
phydev
))
{
printf
(
"Could not initialize PHY %s
\n
"
,
priv
->
phydev
->
dev
->
name
);
return
-
1
;
}
pch_gbe_adjust_link
(
mac_regs
,
priv
->
phydev
);
if
(
!
priv
->
phydev
->
link
)
return
-
1
;
/* Enable TX & RX */
writel
(
PCH_GBE_RX_DMA_EN
|
PCH_GBE_TX_DMA_EN
,
&
mac_regs
->
dma_ctrl
);
writel
(
PCH_GBE_MRE_MAC_RX_EN
,
&
mac_regs
->
mac_rx_en
);
return
0
;
}
static
void
pch_gbe_halt
(
struct
eth_device
*
dev
)
{
struct
pch_gbe_priv
*
priv
=
dev
->
priv
;
pch_gbe_reset
(
dev
);
phy_shutdown
(
priv
->
phydev
);
}
static
int
pch_gbe_send
(
struct
eth_device
*
dev
,
void
*
packet
,
int
length
)
{
struct
pch_gbe_priv
*
priv
=
dev
->
priv
;
struct
pch_gbe_regs
*
mac_regs
=
priv
->
mac_regs
;
struct
pch_gbe_tx_desc
*
tx_head
,
*
tx_desc
;
u16
frame_ctrl
=
0
;
u32
int_st
;
ulong
start
;
tx_head
=
&
priv
->
tx_desc
[
0
];
tx_desc
=
&
priv
->
tx_desc
[
priv
->
tx_idx
];
if
(
length
<
64
)
frame_ctrl
|=
PCH_GBE_TXD_CTRL_APAD
;
tx_desc
->
buffer_addr
=
pci_phys_to_mem
(
priv
->
bdf
,
(
u32
)
packet
);
tx_desc
->
length
=
length
;
tx_desc
->
tx_words_eob
=
length
+
3
;
tx_desc
->
tx_frame_ctrl
=
frame_ctrl
;
tx_desc
->
dma_status
=
0
;
tx_desc
->
gbec_status
=
0
;
/* Test the wrap-around condition */
if
(
++
priv
->
tx_idx
>=
PCH_GBE_DESC_NUM
)
priv
->
tx_idx
=
0
;
writel
(
pci_phys_to_mem
(
priv
->
bdf
,
(
u32
)(
tx_head
+
priv
->
tx_idx
)),
&
mac_regs
->
tx_dsc_sw_p
);
start
=
get_timer
(
0
);
while
(
get_timer
(
start
)
<
PCH_GBE_TIMEOUT
)
{
int_st
=
readl
(
&
mac_regs
->
int_st
);
if
(
int_st
&
PCH_GBE_INT_TX_CMPLT
)
return
0
;
udelay
(
10
);
}
debug
(
"pch_gbe: sent failed
\n
"
);
return
-
ETIME
;
}
static
int
pch_gbe_recv
(
struct
eth_device
*
dev
)
{
struct
pch_gbe_priv
*
priv
=
dev
->
priv
;
struct
pch_gbe_regs
*
mac_regs
=
priv
->
mac_regs
;
struct
pch_gbe_rx_desc
*
rx_head
,
*
rx_desc
;
u32
hw_desc
,
buffer_addr
,
length
;
int
rx_swp
;
rx_head
=
&
priv
->
rx_desc
[
0
];
rx_desc
=
&
priv
->
rx_desc
[
priv
->
rx_idx
];
readl
(
&
mac_regs
->
int_st
);
hw_desc
=
readl
(
&
mac_regs
->
rx_dsc_hw_p_hld
);
/* Just return if not receiving any packet */
if
((
u32
)
rx_desc
==
hw_desc
)
return
0
;
buffer_addr
=
pci_mem_to_phys
(
priv
->
bdf
,
rx_desc
->
buffer_addr
);
length
=
rx_desc
->
rx_words_eob
-
3
-
ETH_FCS_LEN
;
NetReceive
((
uchar
*
)
buffer_addr
,
length
);
/* Test the wrap-around condition */
if
(
++
priv
->
rx_idx
>=
PCH_GBE_DESC_NUM
)
priv
->
rx_idx
=
0
;
rx_swp
=
priv
->
rx_idx
;
if
(
++
rx_swp
>=
PCH_GBE_DESC_NUM
)
rx_swp
=
0
;
writel
(
pci_phys_to_mem
(
priv
->
bdf
,
(
u32
)(
rx_head
+
rx_swp
)),
&
mac_regs
->
rx_dsc_sw_p
);
return
length
;
}
static
int
pch_gbe_mdio_ready
(
struct
pch_gbe_regs
*
mac_regs
)
{
ulong
start
=
get_timer
(
0
);
while
(
get_timer
(
start
)
<
PCH_GBE_TIMEOUT
)
{
if
(
readl
(
&
mac_regs
->
miim
)
&
PCH_GBE_MIIM_OPER_READY
)
return
0
;
udelay
(
10
);
}
return
-
ETIME
;
}
static
int
pch_gbe_mdio_read
(
struct
mii_dev
*
bus
,
int
addr
,
int
devad
,
int
reg
)
{
struct
pch_gbe_regs
*
mac_regs
=
bus
->
priv
;
u32
miim
;
if
(
pch_gbe_mdio_ready
(
mac_regs
))
return
-
ETIME
;
miim
=
(
addr
<<
PCH_GBE_MIIM_PHY_ADDR_SHIFT
)
|
(
reg
<<
PCH_GBE_MIIM_REG_ADDR_SHIFT
)
|
PCH_GBE_MIIM_OPER_READ
;
writel
(
miim
,
&
mac_regs
->
miim
);
if
(
pch_gbe_mdio_ready
(
mac_regs
))
return
-
ETIME
;
return
readl
(
&
mac_regs
->
miim
)
&
0xffff
;
}
static
int
pch_gbe_mdio_write
(
struct
mii_dev
*
bus
,
int
addr
,
int
devad
,
int
reg
,
u16
val
)
{
struct
pch_gbe_regs
*
mac_regs
=
bus
->
priv
;
u32
miim
;
if
(
pch_gbe_mdio_ready
(
mac_regs
))
return
-
ETIME
;
miim
=
(
addr
<<
PCH_GBE_MIIM_PHY_ADDR_SHIFT
)
|
(
reg
<<
PCH_GBE_MIIM_REG_ADDR_SHIFT
)
|
PCH_GBE_MIIM_OPER_WRITE
|
val
;
writel
(
miim
,
&
mac_regs
->
miim
);
if
(
pch_gbe_mdio_ready
(
mac_regs
))
return
-
ETIME
;
else
return
0
;
}
static
int
pch_gbe_mdio_init
(
char
*
name
,
struct
pch_gbe_regs
*
mac_regs
)
{
struct
mii_dev
*
bus
;
bus
=
mdio_alloc
();
if
(
!
bus
)
{
debug
(
"pch_gbe: failed to allocate MDIO bus
\n
"
);
return
-
ENOMEM
;
}
bus
->
read
=
pch_gbe_mdio_read
;
bus
->
write
=
pch_gbe_mdio_write
;
sprintf
(
bus
->
name
,
name
);
bus
->
priv
=
(
void
*
)
mac_regs
;
return
mdio_register
(
bus
);
}
static
int
pch_gbe_phy_init
(
struct
eth_device
*
dev
)
{
struct
pch_gbe_priv
*
priv
=
dev
->
priv
;
struct
phy_device
*
phydev
;
int
mask
=
0xffffffff
;
phydev
=
phy_find_by_mask
(
priv
->
bus
,
mask
,
priv
->
interface
);
if
(
!
phydev
)
{
printf
(
"pch_gbe: cannot find the phy
\n
"
);
return
-
1
;
}
phy_connect_dev
(
phydev
,
dev
);
phydev
->
supported
&=
PHY_GBIT_FEATURES
;
phydev
->
advertising
=
phydev
->
supported
;
priv
->
phydev
=
phydev
;
phy_config
(
phydev
);
return
1
;
}
int
pch_gbe_register
(
bd_t
*
bis
)
{
struct
eth_device
*
dev
;
struct
pch_gbe_priv
*
priv
;
pci_dev_t
devno
;
u32
iobase
;
devno
=
pci_find_devices
(
supported
,
0
);
if
(
devno
==
-
1
)
return
-
ENODEV
;
dev
=
(
struct
eth_device
*
)
malloc
(
sizeof
(
*
dev
));
if
(
!
dev
)
return
-
ENOMEM
;
memset
(
dev
,
0
,
sizeof
(
*
dev
));
/*
* The priv structure contains the descriptors and frame buffers which
* need a strict buswidth alignment (64 bytes)
*/
priv
=
(
struct
pch_gbe_priv
*
)
memalign
(
PCH_GBE_ALIGN_SIZE
,
sizeof
(
*
priv
));
if
(
!
priv
)
{
free
(
dev
);
return
-
ENOMEM
;
}
memset
(
priv
,
0
,
sizeof
(
*
priv
));
dev
->
priv
=
priv
;
priv
->
dev
=
dev
;
priv
->
bdf
=
devno
;
pci_read_config_dword
(
devno
,
PCI_BASE_ADDRESS_1
,
&
iobase
);
iobase
&=
PCI_BASE_ADDRESS_MEM_MASK
;
iobase
=
pci_mem_to_phys
(
devno
,
iobase
);
dev
->
iobase
=
iobase
;
priv
->
mac_regs
=
(
struct
pch_gbe_regs
*
)
iobase
;
sprintf
(
dev
->
name
,
"pch_gbe.%x"
,
iobase
);
/* Read MAC address from SROM and initialize dev->enetaddr with it */
pch_gbe_mac_read
(
priv
->
mac_regs
,
dev
->
enetaddr
);
dev
->
init
=
pch_gbe_init
;
dev
->
halt
=
pch_gbe_halt
;
dev
->
send
=
pch_gbe_send
;
dev
->
recv
=
pch_gbe_recv
;
eth_register
(
dev
);
priv
->
interface
=
PHY_INTERFACE_MODE_RGMII
;
pch_gbe_mdio_init
(
dev
->
name
,
priv
->
mac_regs
);
priv
->
bus
=
miiphy_get_dev_by_name
(
dev
->
name
);
return
pch_gbe_phy_init
(
dev
);
}
drivers/net/pch_gbe.h
0 → 100644
浏览文件 @
10af8781
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
* Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PCH_GBE_H_
#define _PCH_GBE_H_
#define PCH_GBE_TIMEOUT (3 * CONFIG_SYS_HZ)
#define PCH_GBE_DESC_NUM 4
#define PCH_GBE_ALIGN_SIZE 64
/*
* Topcliff GBE MAC supports receiving ethernet frames with normal frame size
* (64-1518 bytes) as well as up to 10318 bytes, however it does not have a
* register bit to turn off receiving 'jumbo frame', so we have to allocate
* our own buffer to store the received frames instead of using U-Boot's own.
*/
#define PCH_GBE_RX_FRAME_LEN ROUND(10318, PCH_GBE_ALIGN_SIZE)
/* Interrupt Status */
/* Interrupt Status Hold */
/* Interrupt Enable */
#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001
#define PCH_GBE_INT_RX_VALID 0x00000002
#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004
#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008
#define PCH_GBE_INT_RX_DMA_ERR 0x00000010
#define PCH_GBE_INT_RX_DSC_EMP 0x00000020
#define PCH_GBE_INT_TX_CMPLT 0x00000100
#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200
#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400
#define PCH_GBE_INT_TX_DMA_ERR 0x00000800
#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000
#define PCH_GBE_INT_MIIM_CMPLT 0x00010000
#define PCH_GBE_INT_PHY_INT 0x00100000
#define PCH_GBE_INT_WOL_DET 0x01000000
#define PCH_GBE_INT_TCPIP_ERR 0x10000000
/* Mode */
#define PCH_GBE_MODE_MII_ETHER 0x00000000
#define PCH_GBE_MODE_GMII_ETHER 0x80000000
#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000
#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000
#define PCH_GBE_MODE_FR_BST 0x04000000
/* Reset */
#define PCH_GBE_ALL_RST 0x80000000
#define PCH_GBE_TX_RST 0x00008000
#define PCH_GBE_RX_RST 0x00004000
/* TCP/IP Accelerator Control */
#define PCH_GBE_EX_LIST_EN 0x00000008
#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004
#define PCH_GBE_TX_TCPIPACC_EN 0x00000002
#define PCH_GBE_RX_TCPIPACC_EN 0x00000001
/* MAC RX Enable */
#define PCH_GBE_MRE_MAC_RX_EN 0x00000001
/* RX Flow Control */
#define PCH_GBE_FL_CTRL_EN 0x80000000
/* RX Mode */
#define PCH_GBE_ADD_FIL_EN 0x80000000
#define PCH_GBE_MLT_FIL_EN 0x40000000
#define PCH_GBE_RH_ALM_EMP_4 0x00000000
#define PCH_GBE_RH_ALM_EMP_8 0x00004000
#define PCH_GBE_RH_ALM_EMP_16 0x00008000
#define PCH_GBE_RH_ALM_EMP_32 0x0000c000
#define PCH_GBE_RH_ALM_FULL_4 0x00000000
#define PCH_GBE_RH_ALM_FULL_8 0x00001000
#define PCH_GBE_RH_ALM_FULL_16 0x00002000
#define PCH_GBE_RH_ALM_FULL_32 0x00003000
#define PCH_GBE_RH_RD_TRG_4 0x00000000
#define PCH_GBE_RH_RD_TRG_8 0x00000200
#define PCH_GBE_RH_RD_TRG_16 0x00000400
#define PCH_GBE_RH_RD_TRG_32 0x00000600
#define PCH_GBE_RH_RD_TRG_64 0x00000800
#define PCH_GBE_RH_RD_TRG_128 0x00000a00
#define PCH_GBE_RH_RD_TRG_256 0x00000c00
#define PCH_GBE_RH_RD_TRG_512 0x00000e00
/* TX Mode */
#define PCH_GBE_TM_NO_RTRY 0x80000000
#define PCH_GBE_TM_LONG_PKT 0x40000000
#define PCH_GBE_TM_ST_AND_FD 0x20000000
#define PCH_GBE_TM_SHORT_PKT 0x10000000
#define PCH_GBE_TM_LTCOL_RETX 0x08000000
#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000
#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000
#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000
#define PCH_GBE_TM_TH_TX_STRT_32 0x0000c000
#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000
#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800
#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000
#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800
#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000
#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800
#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000
#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800
#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000
#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200
#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400
#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600
/* MAC Address Mask */
#define PCH_GBE_BUSY 0x80000000
/* MIIM */
#define PCH_GBE_MIIM_OPER_WRITE 0x04000000
#define PCH_GBE_MIIM_OPER_READ 0x00000000
#define PCH_GBE_MIIM_OPER_READY 0x04000000
#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
/* RGMII Control */
#define PCH_GBE_CRS_SEL 0x00000010
#define PCH_GBE_RGMII_RATE_125M 0x00000000
#define PCH_GBE_RGMII_RATE_25M 0x00000008
#define PCH_GBE_RGMII_RATE_2_5M 0x0000000c
#define PCH_GBE_RGMII_MODE_GMII 0x00000000
#define PCH_GBE_RGMII_MODE_RGMII 0x00000002
#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000
#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001
/* DMA Control */
#define PCH_GBE_RX_DMA_EN 0x00000002
#define PCH_GBE_TX_DMA_EN 0x00000001
/* Receive Descriptor bit definitions */
#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400
#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200
#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100
#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000c0
#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080
#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040
#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020
#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010
#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008
#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004
#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002
#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001
#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200
#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100
#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080
#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040
#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020
#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010
#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008
#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004
#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002
#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001
/* Transmit Descriptor bit definitions */
#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008
#define PCH_GBE_TXD_CTRL_ITAG 0x0004
#define PCH_GBE_TXD_CTRL_ICRC 0x0002
#define PCH_GBE_TXD_CTRL_APAD 0x0001
#define PCH_GBE_TXD_WORDS_SHIFT 2
#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000
#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000
#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800
#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400
#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200
#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100
#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080
#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040
#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020
#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010
/**
* struct pch_gbe_rx_desc - Receive Descriptor
* @buffer_addr: RX Frame Buffer Address
* @tcp_ip_status: TCP/IP Accelerator Status
* @rx_words_eob: RX word count and Byte position
* @gbec_status: GMAC Status
* @dma_status: DMA Status
* @reserved1: Reserved
* @reserved2: Reserved
*/
struct
pch_gbe_rx_desc
{
u32
buffer_addr
;
u32
tcp_ip_status
;
u16
rx_words_eob
;
u16
gbec_status
;
u8
dma_status
;
u8
reserved1
;
u16
reserved2
;
};
/**
* struct pch_gbe_tx_desc - Transmit Descriptor
* @buffer_addr: TX Frame Buffer Address
* @length: Data buffer length
* @reserved1: Reserved
* @tx_words_eob: TX word count and Byte position
* @tx_frame_ctrl: TX Frame Control
* @dma_status: DMA Status
* @reserved2: Reserved
* @gbec_status: GMAC Status
*/
struct
pch_gbe_tx_desc
{
u32
buffer_addr
;
u16
length
;
u16
reserved1
;
u16
tx_words_eob
;
u16
tx_frame_ctrl
;
u8
dma_status
;
u8
reserved2
;
u16
gbec_status
;
};
/**
* pch_gbe_regs_mac_adr - structure holding values of mac address registers
*
* @high Denotes the 1st to 4th byte from the initial of MAC address
* @low Denotes the 5th to 6th byte from the initial of MAC address
*/
struct
pch_gbe_regs_mac_adr
{
u32
high
;
u32
low
;
};
/**
* pch_gbe_regs - structure holding values of MAC registers
*/
struct
pch_gbe_regs
{
u32
int_st
;
u32
int_en
;
u32
mode
;
u32
reset
;
u32
tcpip_acc
;
u32
ex_list
;
u32
int_st_hold
;
u32
phy_int_ctrl
;
u32
mac_rx_en
;
u32
rx_fctrl
;
u32
pause_req
;
u32
rx_mode
;
u32
tx_mode
;
u32
rx_fifo_st
;
u32
tx_fifo_st
;
u32
tx_fid
;
u32
tx_result
;
u32
pause_pkt1
;
u32
pause_pkt2
;
u32
pause_pkt3
;
u32
pause_pkt4
;
u32
pause_pkt5
;
u32
reserve
[
2
];
struct
pch_gbe_regs_mac_adr
mac_adr
[
16
];
u32
addr_mask
;
u32
miim
;
u32
mac_addr_load
;
u32
rgmii_st
;
u32
rgmii_ctrl
;
u32
reserve3
[
3
];
u32
dma_ctrl
;
u32
reserve4
[
3
];
u32
rx_dsc_base
;
u32
rx_dsc_size
;
u32
rx_dsc_hw_p
;
u32
rx_dsc_hw_p_hld
;
u32
rx_dsc_sw_p
;
u32
reserve5
[
3
];
u32
tx_dsc_base
;
u32
tx_dsc_size
;
u32
tx_dsc_hw_p
;
u32
tx_dsc_hw_p_hld
;
u32
tx_dsc_sw_p
;
u32
reserve6
[
3
];
u32
rx_dma_st
;
u32
tx_dma_st
;
u32
reserve7
[
2
];
u32
wol_st
;
u32
wol_ctrl
;
u32
wol_addr_mask
;
};
struct
pch_gbe_priv
{
struct
pch_gbe_rx_desc
rx_desc
[
PCH_GBE_DESC_NUM
];
struct
pch_gbe_tx_desc
tx_desc
[
PCH_GBE_DESC_NUM
];
char
rx_buff
[
PCH_GBE_DESC_NUM
][
PCH_GBE_RX_FRAME_LEN
];
struct
eth_device
*
dev
;
struct
phy_device
*
phydev
;
struct
mii_dev
*
bus
;
struct
pch_gbe_regs
*
mac_regs
;
pci_dev_t
bdf
;
u32
interface
;
int
rx_idx
;
int
tx_idx
;
};
#endif
/* _PCH_GBE_H_ */
drivers/usb/gadget/ether.c
浏览文件 @
10af8781
...
...
@@ -68,7 +68,6 @@ unsigned packet_received, packet_sent;
#define ETH_ZLEN 60
/* Min. octets in frame sans FCS */
#define ETH_DATA_LEN 1500
/* Max. octets in payload */
#define ETH_FRAME_LEN PKTSIZE_ALIGN
/* Max. octets in frame sans FCS */
#define ETH_FCS_LEN 4
/* Octets in the FCS */
#define DRIVER_DESC "Ethernet Gadget"
/* Based on linux 2.6.27 version */
...
...
drivers/usb/gadget/rndis.c
浏览文件 @
10af8781
...
...
@@ -43,7 +43,6 @@
#define ETH_ZLEN 60
/* Min. octets in frame sans FCS */
#define ETH_DATA_LEN 1500
/* Max. octets in payload */
#define ETH_FRAME_LEN PKTSIZE_ALIGN
/* Max. octets in frame sans FCS */
#define ETH_FCS_LEN 4
/* Octets in the FCS */
#define ENOTSUPP 524
/* Operation is not supported */
...
...
include/configs/crownbay.h
浏览文件 @
10af8781
...
...
@@ -52,8 +52,20 @@
#define CONFIG_MMC_SDMA
#define CONFIG_CMD_MMC
/* Topcliff Gigabit Ethernet */
#define CONFIG_PCH_GBE
#define CONFIG_PHYLIB
/* Video is not supported */
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
/* Environment configuration */
#undef CONFIG_ENV_IS_NOWHERE
#undef CONFIG_ENV_SIZE
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0
#endif
/* __CONFIG_H */
include/configs/galileo.h
浏览文件 @
10af8781
...
...
@@ -57,4 +57,17 @@
#define CONFIG_MMC_SDMA
#define CONFIG_CMD_MMC
/* 10/100M Ethernet support */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_PHYLIB
/* Environment configuration */
#undef CONFIG_ENV_IS_NOWHERE
#undef CONFIG_ENV_SIZE
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0
#endif
/* __CONFIG_H */
include/configs/x86-common.h
浏览文件 @
10af8781
...
...
@@ -243,7 +243,34 @@
#define CONFIG_CMD_USB
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_STD_DEVICES_SETTINGS
/* Default environment */
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_HOSTNAME "x86"
#define CONFIG_BOOTFILE "bzImage"
#define CONFIG_LOADADDR 0x1000000
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_STD_DEVICES_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"othbootargs=acpi=off\0" \
"ramdiskaddr=0x2000000\0" \
"ramdiskfile=initramfs.gz\0"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftpboot $loadaddr $bootfile;" \
"tftpboot $ramdiskaddr $ramdiskfile;" \
"zboot $loadaddr 0 $ramdiskaddr $filesize"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftpboot $loadaddr $bootfile;" \
"zboot $loadaddr"
#endif
/* __CONFIG_H */
include/fdtdec.h
浏览文件 @
10af8781
...
...
@@ -347,7 +347,10 @@ int fdtdec_get_pci_vendev(const void *blob, int node,
/**
* Look at the pci address of a device node that represents a PCI device
* and parse the bus, device and function number from it.
* and parse the bus, device and function number from it. For some cases
* like the bus number encoded in reg property is not correct after pci
* enumeration, this function looks through the node's compatible strings
* to get these numbers extracted instead.
*
* @param blob FDT blob
* @param node node to examine
...
...
include/net.h
浏览文件 @
10af8781
...
...
@@ -191,6 +191,8 @@ struct ethernet_hdr {
/* Ethernet header size */
#define ETHER_HDR_SIZE (sizeof(struct ethernet_hdr))
#define ETH_FCS_LEN 4
/* Octets in the FCS */
struct
e802_hdr
{
uchar
et_dest
[
6
];
/* Destination node */
uchar
et_src
[
6
];
/* Source node */
...
...
include/netdev.h
浏览文件 @
10af8781
...
...
@@ -69,6 +69,7 @@ int natsemi_initialize(bd_t *bis);
int
ne2k_register
(
void
);
int
npe_initialize
(
bd_t
*
bis
);
int
ns8382x_initialize
(
bd_t
*
bis
);
int
pch_gbe_register
(
bd_t
*
bis
);
int
pcnet_initialize
(
bd_t
*
bis
);
int
ppc_4xx_eth_initialize
(
bd_t
*
bis
);
int
rtl8139_initialize
(
bd_t
*
bis
);
...
...
@@ -123,6 +124,9 @@ static inline int pci_eth_init(bd_t *bis)
#ifdef CONFIG_E1000
num
+=
e1000_initialize
(
bis
);
#endif
#ifdef CONFIG_PCH_GBE
num
+=
pch_gbe_register
(
bis
);
#endif
#ifdef CONFIG_PCNET
num
+=
pcnet_initialize
(
bis
);
#endif
...
...
include/usb_ether.h
浏览文件 @
10af8781
...
...
@@ -18,7 +18,6 @@
#define ETH_ZLEN 60
/* Min. octets in frame sans FCS */
#define ETH_DATA_LEN 1500
/* Max. octets in payload */
#define ETH_FRAME_LEN PKTSIZE_ALIGN
/* Max. octets in frame sans FCS */
#define ETH_FCS_LEN 4
/* Octets in the FCS */
struct
ueth_data
{
/* eth info */
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录