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0b203350
编写于
11月 18, 2007
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://www.denx.de/git/u-boot-mips
上级
7e14fc65
7e1d884b
变更
14
隐藏空白更改
内联
并排
Showing
14 changed file
with
132 addition
and
134 deletion
+132
-134
MAKEALL
MAKEALL
+1
-0
board/dbau1x00/u-boot.lds
board/dbau1x00/u-boot.lds
+5
-4
board/gth2/u-boot.lds
board/gth2/u-boot.lds
+5
-3
board/incaip/u-boot.lds
board/incaip/u-boot.lds
+5
-4
board/pb1x00/Makefile
board/pb1x00/Makefile
+1
-1
board/pb1x00/lowlevel_init.S
board/pb1x00/lowlevel_init.S
+2
-2
board/pb1x00/u-boot.lds
board/pb1x00/u-boot.lds
+5
-3
board/purple/u-boot.lds
board/purple/u-boot.lds
+5
-4
board/tb0229/u-boot.lds
board/tb0229/u-boot.lds
+5
-4
cpu/mips/au1x00_eth.c
cpu/mips/au1x00_eth.c
+59
-59
cpu/mips/cache.S
cpu/mips/cache.S
+13
-17
cpu/mips/config.mk
cpu/mips/config.mk
+1
-2
cpu/mips/cpu.c
cpu/mips/cpu.c
+3
-3
cpu/mips/start.S
cpu/mips/start.S
+22
-28
未找到文件。
MAKEALL
浏览文件 @
0b203350
...
...
@@ -554,6 +554,7 @@ LIST_mips5kc_el=""
LIST_au1xx0_el
=
"
\
dbau1550_el
\
pb1000
\
"
LIST_mips_el
=
"
\
...
...
board/dbau1x00/u-boot.lds
浏览文件 @
0b203350
...
...
@@ -54,10 +54,11 @@ SECTIONS
.sdata : { *(.sdata) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
...
...
board/gth2/u-boot.lds
浏览文件 @
0b203350
...
...
@@ -54,9 +54,11 @@ SECTIONS
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
...
...
board/incaip/u-boot.lds
浏览文件 @
0b203350
...
...
@@ -54,10 +54,11 @@ SECTIONS
.sdata : { *(.sdata) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
...
...
board/pb1x00/Makefile
浏览文件 @
0b203350
...
...
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
=
$(BOARD)
.o flash.o
SOBJS
=
memsetup
.o
SOBJS
=
lowlevel_init
.o
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
...
...
board/pb1x00/
memsetup
.S
→
board/pb1x00/
lowlevel_init
.S
浏览文件 @
0b203350
...
...
@@ -15,8 +15,8 @@
.
set
noreorder
.
set
mips32
.
globl
memsetup
memsetup
:
.
globl
lowlevel_init
lowlevel_init
:
/
*
*
Step
1
)
Establish
CPU
endian
mode
.
*
NOTE
:
A
fair
amount
of
code
is
necessary
on
the
Pb1000
to
...
...
board/pb1x00/u-boot.lds
浏览文件 @
0b203350
...
...
@@ -54,9 +54,11 @@ SECTIONS
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
...
...
board/purple/u-boot.lds
浏览文件 @
0b203350
...
...
@@ -64,10 +64,11 @@ SECTIONS
.sdata : { *(.sdata) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
...
...
board/tb0229/u-boot.lds
浏览文件 @
0b203350
...
...
@@ -54,10 +54,11 @@ SECTIONS
.sdata : { *(.sdata) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
...
...
cpu/mips/au1x00_eth.c
浏览文件 @
0b203350
...
...
@@ -90,6 +90,65 @@ mac_fifo_t mac_fifo[NO_OF_FIFOS];
#define MAX_WAIT 1000
#if defined(CONFIG_CMD_MII)
int
au1x00_miiphy_read
(
char
*
devname
,
unsigned
char
addr
,
unsigned
char
reg
,
unsigned
short
*
value
)
{
volatile
u32
*
mii_control_reg
=
(
volatile
u32
*
)(
ETH0_BASE
+
MAC_MII_CNTRL
);
volatile
u32
*
mii_data_reg
=
(
volatile
u32
*
)(
ETH0_BASE
+
MAC_MII_DATA
);
u32
mii_control
;
unsigned
int
timedout
=
20
;
while
(
*
mii_control_reg
&
MAC_MII_BUSY
)
{
udelay
(
1000
);
if
(
--
timedout
==
0
)
{
printf
(
"au1x00_eth: miiphy_read busy timeout!!
\n
"
);
return
-
1
;
}
}
mii_control
=
MAC_SET_MII_SELECT_REG
(
reg
)
|
MAC_SET_MII_SELECT_PHY
(
addr
)
|
MAC_MII_READ
;
*
mii_control_reg
=
mii_control
;
timedout
=
20
;
while
(
*
mii_control_reg
&
MAC_MII_BUSY
)
{
udelay
(
1000
);
if
(
--
timedout
==
0
)
{
printf
(
"au1x00_eth: miiphy_read busy timeout!!
\n
"
);
return
-
1
;
}
}
*
value
=
*
mii_data_reg
;
return
0
;
}
int
au1x00_miiphy_write
(
char
*
devname
,
unsigned
char
addr
,
unsigned
char
reg
,
unsigned
short
value
)
{
volatile
u32
*
mii_control_reg
=
(
volatile
u32
*
)(
ETH0_BASE
+
MAC_MII_CNTRL
);
volatile
u32
*
mii_data_reg
=
(
volatile
u32
*
)(
ETH0_BASE
+
MAC_MII_DATA
);
u32
mii_control
;
unsigned
int
timedout
=
20
;
while
(
*
mii_control_reg
&
MAC_MII_BUSY
)
{
udelay
(
1000
);
if
(
--
timedout
==
0
)
{
printf
(
"au1x00_eth: miiphy_write busy timeout!!
\n
"
);
return
-
1
;
}
}
mii_control
=
MAC_SET_MII_SELECT_REG
(
reg
)
|
MAC_SET_MII_SELECT_PHY
(
addr
)
|
MAC_MII_WRITE
;
*
mii_data_reg
=
value
;
*
mii_control_reg
=
mii_control
;
return
0
;
}
#endif
static
int
au1x00_send
(
struct
eth_device
*
dev
,
volatile
void
*
packet
,
int
length
){
volatile
mac_fifo_t
*
fifo_tx
=
(
volatile
mac_fifo_t
*
)(
MAC0_TX_DMA_ADDR
+
MAC_TX_BUFF0_STATUS
);
...
...
@@ -249,63 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){
return
1
;
}
#if defined(CONFIG_CMD_MII)
int
au1x00_miiphy_read
(
char
*
devname
,
unsigned
char
addr
,
unsigned
char
reg
,
unsigned
short
*
value
)
{
volatile
u32
*
mii_control_reg
=
(
volatile
u32
*
)(
ETH0_BASE
+
MAC_MII_CNTRL
);
volatile
u32
*
mii_data_reg
=
(
volatile
u32
*
)(
ETH0_BASE
+
MAC_MII_DATA
);
u32
mii_control
;
unsigned
int
timedout
=
20
;
while
(
*
mii_control_reg
&
MAC_MII_BUSY
)
{
udelay
(
1000
);
if
(
--
timedout
==
0
)
{
printf
(
"au1x00_eth: miiphy_read busy timeout!!
\n
"
);
return
-
1
;
}
}
mii_control
=
MAC_SET_MII_SELECT_REG
(
reg
)
|
MAC_SET_MII_SELECT_PHY
(
addr
)
|
MAC_MII_READ
;
*
mii_control_reg
=
mii_control
;
timedout
=
20
;
while
(
*
mii_control_reg
&
MAC_MII_BUSY
)
{
udelay
(
1000
);
if
(
--
timedout
==
0
)
{
printf
(
"au1x00_eth: miiphy_read busy timeout!!
\n
"
);
return
-
1
;
}
}
*
value
=
*
mii_data_reg
;
return
0
;
}
int
au1x00_miiphy_write
(
char
*
devname
,
unsigned
char
addr
,
unsigned
char
reg
,
unsigned
short
value
)
{
volatile
u32
*
mii_control_reg
=
(
volatile
u32
*
)(
ETH0_BASE
+
MAC_MII_CNTRL
);
volatile
u32
*
mii_data_reg
=
(
volatile
u32
*
)(
ETH0_BASE
+
MAC_MII_DATA
);
u32
mii_control
;
unsigned
int
timedout
=
20
;
while
(
*
mii_control_reg
&
MAC_MII_BUSY
)
{
udelay
(
1000
);
if
(
--
timedout
==
0
)
{
printf
(
"au1x00_eth: miiphy_write busy timeout!!
\n
"
);
return
;
}
}
mii_control
=
MAC_SET_MII_SELECT_REG
(
reg
)
|
MAC_SET_MII_SELECT_PHY
(
addr
)
|
MAC_MII_WRITE
;
*
mii_data_reg
=
value
;
*
mii_control_reg
=
mii_control
;
return
0
;
}
#endif
#endif
/* CONFIG_AU1X00 */
cpu/mips/cache.S
浏览文件 @
0b203350
...
...
@@ -22,7 +22,6 @@
*
MA
02111
-
1307
USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
...
...
@@ -30,13 +29,11 @@
#include <asm/addrspace.h>
#include <asm/cacheops.h>
/
*
16
KB
is
the
maximum
size
of
instruction
and
data
caches
on
*
MIPS
4
K
.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
/*
*
cacheop
macro
to
automate
cache
operations
*
first
some
helpers
...
...
...
@@ -131,7 +128,6 @@ mips_cache_reset:
li
t4
,
CFG_CACHELINE_SIZE
move
t5
,
t4
li
v0
,
MIPS_MAX_CACHE_SIZE
/
*
Now
clear
that
much
memory
starting
from
zero
.
...
...
@@ -139,8 +135,8 @@ mips_cache_reset:
li
a0
,
KSEG1
addu
a1
,
a0
,
v0
2
:
sw
zero
,
0
(
a0
)
2
:
sw
zero
,
0
(
a0
)
sw
zero
,
4
(
a0
)
sw
zero
,
8
(
a0
)
sw
zero
,
12
(
a0
)
...
...
@@ -156,11 +152,11 @@ mips_cache_reset:
mtc0
zero
,
CP0_TAGLO
/
*
*
The
caches
are
probably
in
an
indeterminate
state
,
*
so
we
force
good
parity
into
them
by
doing
an
*
invalidate
,
load
/
fill
,
invalidate
for
each
line
.
*/
/
*
*
The
caches
are
probably
in
an
indeterminate
state
,
*
so
we
force
good
parity
into
them
by
doing
an
*
invalidate
,
load
/
fill
,
invalidate
for
each
line
.
*/
/
*
Assume
bottom
of
RAM
will
generate
good
parity
for
the
cache
.
*/
...
...
@@ -201,9 +197,9 @@ mips_cache_reset:
move
a1
,
a2
icacheop
(
a0
,
a1
,
a2
,
a3
,
Index_Store_Tag_D
)
j
ra
.
end
mips_cache_reset
j
ra
.
end
mips_cache_reset
/*******************************************************************************
*
...
...
@@ -220,7 +216,7 @@ dcache_status:
andi
v0
,
v0
,
1
j
ra
.
end
dcache_status
.
end
dcache_status
/*******************************************************************************
*
...
...
@@ -237,11 +233,10 @@ dcache_disable:
li
t1
,
-
8
and
t0
,
t0
,
t1
ori
t0
,
t0
,
CONF_CM_UNCACHED
mtc0
t0
,
CP0_CONFIG
mtc0
t0
,
CP0_CONFIG
j
ra
.
end
dcache_disable
.
end
dcache_disable
/*******************************************************************************
*
...
...
@@ -266,4 +261,5 @@ mips_cache_lock:
icacheop
(
a0
,
a1
,
a2
,
a3
,0
x1d
)
j
ra
.
end
mips_cache_lock
cpu/mips/config.mk
浏览文件 @
0b203350
...
...
@@ -20,8 +20,7 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
v
=
$(
shell
\
$(CROSS_COMPILE)
as
--version
|grep
"GNU assembler"
|awk
'{print $$3
}
'
|awk
-F
.
'{print $$2}'
)
v
=
$(
shell
$(AS)
--version
|grep
"GNU assembler"
|cut
-d
.
-f2
)
MIPSFLAGS
=
$(
shell
\
if
[
"
$v
"
-lt
"14"
]
;
then
\
echo
"-mcpu=4kc"
;
\
...
...
cpu/mips/cpu.c
浏览文件 @
0b203350
...
...
@@ -39,12 +39,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return
0
;
}
void
flush_cache
(
ulong
start_addr
,
ulong
size
)
void
flush_cache
(
ulong
start_addr
,
ulong
size
)
{
}
void
write_one_tlb
(
int
index
,
u32
pagemask
,
u32
hi
,
u32
low0
,
u32
low1
){
void
write_one_tlb
(
int
index
,
u32
pagemask
,
u32
hi
,
u32
low0
,
u32
low1
)
{
write_32bit_cp0_register
(
CP0_ENTRYLO0
,
low0
);
write_32bit_cp0_register
(
CP0_PAGEMASK
,
pagemask
);
write_32bit_cp0_register
(
CP0_ENTRYLO1
,
low1
);
...
...
cpu/mips/start.S
浏览文件 @
0b203350
...
...
@@ -22,13 +22,11 @@
*
MA
02111
-
1307
USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#define RVECENT(f,n) \
b
f
; nop
#define XVECENT(f,bev) \
...
...
@@ -192,7 +190,7 @@ _start:
.
word
0x00000000
.
word
0x03e00008
.
word
0x00000000
.
word
0x00000000
.
word
0x00000000
/*
0
xbfc00428
*/
.
word
0xdc870000
.
word
0xfca70000
...
...
@@ -203,7 +201,7 @@ _start:
.
word
0x00000000
.
word
0x03e00008
.
word
0x00000000
.
word
0x00000000
.
word
0x00000000
#endif /* CONFIG_PURPLE */
.
align
4
reset
:
...
...
@@ -235,33 +233,31 @@ reset:
mtc0
t0
,
CP0_CONFIG
/
*
Initialize
$gp.
*/
bal
1
f
*/
bal
1
f
nop
.
word
_gp
1:
move
gp
,
ra
lw
t1
,
0
(
ra
)
move
gp
,
t1
1
:
lw
gp
,
0
(
ra
)
#ifdef CONFIG_INCA_IP
/
*
Disable
INCA
-
IP
Watchdog
.
*/
la
t9
,
disable_incaip_wdt
jalr
t9
la
t9
,
disable_incaip_wdt
jalr
t9
nop
#endif
/
*
Initialize
any
external
memory
.
*/
la
t9
,
lowlevel_init
jalr
t9
la
t9
,
lowlevel_init
jalr
t9
nop
/
*
Initialize
caches
...
*/
la
t9
,
mips_cache_reset
jalr
t9
la
t9
,
mips_cache_reset
jalr
t9
nop
/
*
...
and
enable
them
.
...
...
@@ -269,12 +265,11 @@ reset:
li
t0
,
CONF_CM_CACHABLE_NONCOHERENT
mtc0
t0
,
CP0_CONFIG
/
*
Set
up
temporary
stack
.
*/
li
a0
,
CFG_INIT_SP_OFFSET
la
t9
,
mips_cache_lock
jalr
t9
la
t9
,
mips_cache_lock
jalr
t9
nop
li
t0
,
CFG_SDRAM_BASE
+
CFG_INIT_SP_OFFSET
...
...
@@ -284,7 +279,6 @@ reset:
j
t9
nop
/*
*
void
relocate_code
(
addr_sp
,
gd
,
addr_moni
)
*
...
...
@@ -298,7 +292,7 @@ reset:
.
globl
relocate_code
.
ent
relocate_code
relocate_code
:
move
sp
,
a0
/*
Set
new
stack
pointer
*/
move
sp
,
a0
/*
Set
new
stack
pointer
*/
li
t0
,
CFG_MONITOR_BASE
la
t3
,
in_ram
...
...
@@ -312,8 +306,8 @@ relocate_code:
*/
move
t6
,
gp
sub
gp
,
CFG_MONITOR_BASE
add
gp
,
a2
/*
gp
now
adjusted
*/
sub
t6
,
gp
,
t6
/*
t6
<--
relocation
offset
*/
add
gp
,
a2
/*
gp
now
adjusted
*/
sub
t6
,
gp
,
t6
/*
t6
<--
relocation
offset
*/
/
*
*
t0
=
source
address
...
...
@@ -329,7 +323,7 @@ relocate_code:
sw
t3
,
0
(
t1
)
addu
t0
,
4
ble
t0
,
t2
,
1
b
addu
t1
,
4
/*
delay
slot
*/
addu
t1
,
4
/*
delay
slot
*/
#endif
/
*
If
caches
were
enabled
,
we
would
have
to
flush
them
here
.
...
...
@@ -376,7 +370,8 @@ in_ram:
add
t2
,
t6
sub
t1
,
4
1
:
addi
t1
,
4
1
:
addi
t1
,
4
bltl
t1
,
t2
,
1
b
sw
zero
,
0
(
t1
)
/*
delay
slot
*/
...
...
@@ -387,11 +382,10 @@ in_ram:
.
end
relocate_code
/
*
Exception
handlers
.
*/
romReserved
:
b
romReserved
b
romReserved
romExcHandle
:
b
romExcHandle
b
romExcHandle
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