powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: NAnton Staaf <robotboy@chromium.org>
Acked-by: NStefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>

arch/powerpc/include/asm/cache.h

@@ -20,6 +20,12 @@
 
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+
 /*
  * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
  */