Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OS
U-Boot.Mirror
提交
095b8a37
U
U-Boot.Mirror
项目概览
OS
/
U-Boot.Mirror
通知
1
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
U
U-Boot.Mirror
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
095b8a37
编写于
8月 02, 2005
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
Coding style cleanup
上级
797638f9
变更
13
隐藏空白更改
内联
并排
Showing
13 changed file
with
237 addition
and
243 deletion
+237
-243
board/funkwerk/vovpn-gw/vovpn-gw.c
board/funkwerk/vovpn-gw/vovpn-gw.c
+16
-16
board/pm520/flash.c
board/pm520/flash.c
+1
-3
common/cmd_flash.c
common/cmd_flash.c
+1
-1
common/cmd_usb.c
common/cmd_usb.c
+1
-2
common/usb.c
common/usb.c
+9
-10
common/usb_storage.c
common/usb_storage.c
+5
-5
cpu/arm920t/s3c24x0/usb_ohci.c
cpu/arm920t/s3c24x0/usb_ohci.c
+2
-4
cpu/mpc5xxx/usb_ohci.c
cpu/mpc5xxx/usb_ohci.c
+3
-3
include/440_i2c.h
include/440_i2c.h
+1
-1
include/configs/bamboo.h
include/configs/bamboo.h
+77
-77
include/configs/walnut.h
include/configs/walnut.h
+56
-56
include/configs/yellowstone.h
include/configs/yellowstone.h
+31
-31
include/configs/yosemite.h
include/configs/yosemite.h
+34
-34
未找到文件。
board/funkwerk/vovpn-gw/vovpn-gw.c
浏览文件 @
095b8a37
...
...
@@ -208,22 +208,22 @@ void reset_phy (void)
}
static
unsigned
long
UPMATable
[]
=
{
0x8fffec00
,
0x0ffcfc00
,
0x0ffcfc00
,
0x0ffcfc00
,
/
/Words 0 to 3
0x0ffcfc04
,
0x3ffdfc00
,
0xfffffc01
,
0xfffffc01
,
/
/Words 4 to 7
0xfffffc00
,
0xfffffc04
,
0xfffffc01
,
0xfffffc00
,
/
/Words 8 to 11
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
/Words 12 to 15
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
/Words 16 to 19
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc01
,
/
/Words 20 to 23
0x8fffec00
,
0x00fffc00
,
0x00fffc00
,
0x00fffc00
,
/
/Words 24 to 27
0x0ffffc04
,
0xfffffc01
,
0xfffffc01
,
0xfffffc01
,
/
/Words 28 to 31
0xfffffc00
,
0xfffffc01
,
0xfffffc01
,
0xfffffc00
,
/
/Words 32 to 35
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
/Words 36 to 39
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
/Words 40 to 43
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc01
,
/
/Words 44 to 47
0xfffffc00
,
0xfffffc04
,
0xfffffc01
,
0xfffffc00
,
/
/Words 48 to 51
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
/Words 52 to 55
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc01
,
/
/Words 56 to 59
0xffffec00
,
0xffffec04
,
0xffffec00
,
0xfffffc01
/
/Words 60 to 63
0x8fffec00
,
0x0ffcfc00
,
0x0ffcfc00
,
0x0ffcfc00
,
/
* Words 0 to 3 */
0x0ffcfc04
,
0x3ffdfc00
,
0xfffffc01
,
0xfffffc01
,
/
* Words 4 to 7 */
0xfffffc00
,
0xfffffc04
,
0xfffffc01
,
0xfffffc00
,
/
* Words 8 to 11 */
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
* Words 12 to 15 */
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
* Words 16 to 19 */
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc01
,
/
* Words 20 to 23 */
0x8fffec00
,
0x00fffc00
,
0x00fffc00
,
0x00fffc00
,
/
* Words 24 to 27 */
0x0ffffc04
,
0xfffffc01
,
0xfffffc01
,
0xfffffc01
,
/
* Words 28 to 31 */
0xfffffc00
,
0xfffffc01
,
0xfffffc01
,
0xfffffc00
,
/
* Words 32 to 35 */
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
* Words 36 to 39 */
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
* Words 40 to 43 */
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc01
,
/
* Words 44 to 47 */
0xfffffc00
,
0xfffffc04
,
0xfffffc01
,
0xfffffc00
,
/
* Words 48 to 51 */
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
/
* Words 52 to 55 */
0xfffffc00
,
0xfffffc00
,
0xfffffc00
,
0xfffffc01
,
/
* Words 56 to 59 */
0xffffec00
,
0xffffec04
,
0xffffec00
,
0xfffffc01
/
* Words 60 to 63 */
};
int
board_early_init_f
(
void
)
...
...
board/pm520/flash.c
浏览文件 @
095b8a37
...
...
@@ -334,7 +334,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
return
1
;
}
}
/* issue the Read Identifier Codes command */
*
addr
=
(
FPW
)
INTEL_READID
;
...
...
@@ -351,8 +351,6 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
return
ret
;
}
/*-----------------------------------------------------------------------
*/
...
...
common/cmd_flash.c
浏览文件 @
095b8a37
...
...
@@ -101,7 +101,7 @@ abbrev_spec (char *str, flash_info_t ** pinfo, int *psf, int *psl)
* erase and protect commands. The range of the addresses on which
* either of the commands is to operate can be given in two forms:
* 1. <cmd> start end - operate on <'start', 'end')
* 2. <cmd> start +length - operate on <'start', start + length)
* 2. <cmd> start +length - operate on <'start', start + length)
* If the second form is used and the end address doesn't fall on the
* sector boundary, than it will be adjusted to the next sector boundary.
* If it isn't in the flash, the function will fail (return -1).
...
...
common/cmd_usb.c
浏览文件 @
095b8a37
...
...
@@ -455,9 +455,8 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
i
=
usb_init
();
#ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */
if
(
i
>=
0
)
if
(
i
>=
0
)
usb_stor_curr_dev
=
usb_stor_scan
(
1
);
#endif
return
0
;
}
...
...
common/usb.c
浏览文件 @
095b8a37
...
...
@@ -46,8 +46,7 @@
#include <405gp_pci.h>
#endif
#undef USB_DEBUG
#undef USB_DEBUG
#ifdef USB_DEBUG
#define USB_PRINTF(fmt,args...) printf (fmt ,##args)
...
...
@@ -342,7 +341,7 @@ int usb_clear_halt(struct usb_device *dev, int pipe)
if
(
result
<
0
)
return
result
;
/*
/*
* NOTE: we do not get status and verify reset was successful
* as some devices are reported to lock up upon this check..
*/
...
...
@@ -517,13 +516,13 @@ int usb_get_string(struct usb_device *dev, unsigned short langid, unsigned char
/* some devices are flaky */
result
=
usb_control_msg
(
dev
,
usb_rcvctrlpipe
(
dev
,
0
),
USB_REQ_GET_DESCRIPTOR
,
USB_DIR_IN
,
(
USB_DT_STRING
<<
8
)
+
index
,
langid
,
buf
,
size
,
(
USB_DT_STRING
<<
8
)
+
index
,
langid
,
buf
,
size
,
USB_CNTL_TIMEOUT
);
if
(
result
>
0
)
break
;
}
}
return
result
;
}
...
...
@@ -572,7 +571,7 @@ static int usb_string_sub(struct usb_device *dev, unsigned int langid,
}
if
(
rc
<
2
)
rc
=
-
1
;
rc
=
-
1
;
return
rc
;
}
...
...
@@ -721,10 +720,10 @@ int usb_new_device(struct usb_device *dev)
}
}
dev
->
descriptor
.
bMaxPacketSize0
=
desc
->
bMaxPacketSize0
;
/* find the port number we're at */
if
(
parent
)
{
for
(
j
=
0
;
j
<
parent
->
maxchild
;
j
++
)
{
if
(
parent
->
children
[
j
]
==
dev
)
{
port
=
j
;
...
...
@@ -958,7 +957,7 @@ static int hub_port_reset(struct usb_device *dev, int port,
return
-
1
;
if
(
portstatus
&
USB_PORT_STAT_ENABLE
)
{
break
;
}
...
...
common/usb_storage.c
浏览文件 @
095b8a37
...
...
@@ -229,7 +229,7 @@ int usb_stor_scan(int mode)
}
if
(
usb_storage_probe
(
dev
,
0
,
&
usb_stor
[
usb_max_devs
]))
{
/* ok, it is a storage devices */
/* get info and fill it in */
if
(
usb_stor_get_info
(
dev
,
&
usb_stor
[
usb_max_devs
],
&
usb_dev_desc
[
usb_max_devs
]))
if
(
usb_stor_get_info
(
dev
,
&
usb_stor
[
usb_max_devs
],
&
usb_dev_desc
[
usb_max_devs
]))
usb_max_devs
++
;
}
/* if storage device */
if
(
usb_max_devs
==
USB_MAX_STOR_DEV
)
{
...
...
@@ -237,7 +237,7 @@ int usb_stor_scan(int mode)
break
;
}
}
/* for */
usb_disable_asynch
(
0
);
/* asynch transfer allowed */
printf
(
"%d Storage Device(s) found
\n
"
,
usb_max_devs
);
if
(
usb_max_devs
>
0
)
...
...
@@ -656,7 +656,7 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
retry
=
0
;
again:
USB_STOR_PRINTF
(
"STATUS phase
\n
"
);
result
=
usb_bulk_msg
(
us
->
pusb_dev
,
pipein
,
&
csw
,
UMASS_BBB_CSW_SIZE
,
result
=
usb_bulk_msg
(
us
->
pusb_dev
,
pipein
,
&
csw
,
UMASS_BBB_CSW_SIZE
,
&
actlen
,
USB_CNTL_TIMEOUT
*
5
);
/* special handling of STALL in STATUS phase */
...
...
@@ -1134,7 +1134,7 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
dev
->
descriptor
.
idProduct
==
0x2010
)
)
USB_STOR_PRINTF
(
"usb_stor_get_info: skipping RESET..
\n
"
);
else
else
ss
->
transport_reset
(
ss
);
pccb
->
pdata
=
usb_stor_buf
;
...
...
@@ -1145,7 +1145,7 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
if
(
usb_inquiry
(
pccb
,
ss
))
return
-
1
;
perq
=
usb_stor_buf
[
0
];
modi
=
usb_stor_buf
[
1
];
if
((
perq
&
0x1f
)
==
0x1f
)
{
...
...
cpu/arm920t/s3c24x0/usb_ohci.c
浏览文件 @
095b8a37
...
...
@@ -1220,8 +1220,6 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
return
stat
;
}
/*-------------------------------------------------------------------------*/
/* common code for handling submit messages - used for all but root hub */
...
...
@@ -1294,7 +1292,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
wait_ms
(
1
);
if
(
!
urb_finished
)
dbg
(
"\%"
);
}
else
{
err
(
"CTL:TIMEOUT "
);
dbg
(
"submit_common_msg: TO status %x
\n
"
,
stat
);
...
...
@@ -1511,7 +1509,7 @@ hc_interrupt (void)
ohci
->
disabled
++
;
err
(
"%s device removed!"
,
ohci
->
slot_name
);
return
-
1
;
}
else
if
((
ints
&=
readl
(
&
regs
->
intrenable
))
==
0
)
{
dbg
(
"hc_interrupt: returning..
\n
"
);
return
0xff
;
...
...
cpu/mpc5xxx/usb_ohci.c
浏览文件 @
095b8a37
...
...
@@ -1261,7 +1261,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
stat
=
USB_ST_CRC_ERR
;
break
;
}
/* NOTE: since we are not interrupt driven in U-Boot and always
* handle only one URB at a time, we cannot assume the
* transaction finished on the first successful return from
...
...
@@ -1483,7 +1483,7 @@ hc_interrupt (void)
struct
ohci_regs
*
regs
=
ohci
->
regs
;
int
ints
;
int
stat
=
-
1
;
if
((
ohci
->
hcca
->
done_head
!=
0
)
&&
!
(
ohci_cpu_to_le32
(
ohci
->
hcca
->
done_head
)
&
0x01
))
{
...
...
@@ -1493,7 +1493,7 @@ hc_interrupt (void)
ohci
->
disabled
++
;
err
(
"%s device removed!"
,
ohci
->
slot_name
);
return
-
1
;
}
else
if
((
ints
&=
readl
(
&
regs
->
intrenable
))
==
0
)
{
dbg
(
"hc_interrupt: returning..
\n
"
);
return
0xff
;
...
...
include/440_i2c.h
浏览文件 @
095b8a37
#ifndef _440_i2c_h_
#define _440_i2c_h_
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
#else
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
...
...
include/configs/bamboo.h
浏览文件 @
095b8a37
...
...
@@ -30,13 +30,13 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_BAMBOO
1
/* Board is BAMBOO
*/
#define CONFIG_440_EP
1
/* Specific PPC440EP support */
#define CONFIG_BAMBOO
1
/* Board is BAMBOO
*/
#define CONFIG_440_EP 1
/* Specific PPC440EP support */
#define CONFIG_4xx
1
/* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F
1
/* Call board_early_init_f */
#undef CFG_DRAM_TEST
/* disable - takes long time! */
/
/#define CONFIG_SYS_CLK_FREQ 66666666 /
* external freq to pll */
#define CONFIG_4xx 1
/* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1
/* Call board_early_init_f */
#undef CFG_DRAM_TEST
/* disable - takes long time! */
/
*#define CONFIG_SYS_CLK_FREQ 66666666 /X
* external freq to pll */
#define CONFIG_SYS_CLK_FREQ 33333333
/* external freq to pll */
/*-----------------------------------------------------------------------
...
...
@@ -64,24 +64,24 @@
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR
0xf0000000
/* DCache */
#define CFG_INIT_RAM_ADDR 0xf0000000
/* DCache */
#define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256
/* num bytes initial data */
#define CFG_GBL_DATA_SIZE 256
/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN
(256 * 1024)
/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN
(128 * 1024)
/* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024)
/* 128MB
*/
/
/#define CFG_SDRAM_BANKS (2)
#define CFG_SDRAM_BANKS
(1)
#define CFG_MONITOR_LEN
(256 * 1024)
/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN
(128 * 1024)
/* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024)
/* 128MB
*/
/
*#define CFG_SDRAM_BANKS (2) */
#define CFG_SDRAM_BANKS
(1)
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200
/* use external 11.059MHz clk */
#define CONFIG_BAUDRATE
115200
#define CONFIG_SERIAL_MULTI
1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI
1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
...
...
@@ -95,8 +95,8 @@
* The DS1558 code assumes this condition
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE
(0x2000 - 0x10)
/* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1
/* DS1556 RTC */
#define CFG_NVRAM_SIZE
(0x2000 - 0x10)
/* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1
/* DS1556 RTC */
/*-----------------------------------------------------------------------
* FLASH related
...
...
@@ -109,9 +109,9 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
#else
#define CFG_FLASH_CFI
/* The flash is CFI compatible
*/
#define CFG_FLASH_CFI_DRIVER
/* Use common CFI driver
*/
#define CFG_FLASH_CFI_AMD_RESET
1
/* AMD RESET for STM 29W320DB!
*/
#define CFG_FLASH_CFI
/* The flash is CFI compatible
*/
#define CFG_FLASH_CFI_DRIVER
/* Use common CFI driver
*/
#define CFG_FLASH_CFI_AMD_RESET
1
/* AMD RESET for STM 29W320DB!
*/
#define CFG_MAX_FLASH_BANKS 1
/* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256
/* max number of sectors on one chip */
...
...
@@ -125,7 +125,7 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM
/* Don't use SPD EEPROM for setup */
#undef CONFIG_SPD_EEPROM
/* Don't use SPD EEPROM for setup */
/*-----------------------------------------------------------------------
* I2C
...
...
@@ -139,9 +139,9 @@
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef
CFG_ENV_IS_IN_NVRAM
/*No NVRAM on board*/
#undef
CFG_ENV_IS_IN_NVRAM
/*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH
/* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM
1
#define CFG_ENV_IS_IN_EEPROM
1
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
...
...
@@ -158,12 +158,12 @@
#define CONFIG_BOOTCOMMAND "bootm 0xfe000000"
/* autoboot command */
#define CONFIG_BOOTDELAY 3
/* disable autoboot */
#define CONFIG_LOADS_ECHO
1
/* echo on for serial download */
#define CONFIG_LOADS_ECHO 1
/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1
/* allow baudrate change */
#define CONFIG_MII
1
/* MII PHY management */
#define CONFIG_NET_MULTI
1
/* required for netconsole */
#define CONFIG_PHY1_ADDR
3
#define CONFIG_MII 1
/* MII PHY management */
#define CONFIG_NET_MULTI
1
/* required for netconsole */
#define CONFIG_PHY1_ADDR
3
#define CONFIG_HAS_ETH1 1
/* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1
/* PHY address, See schematics */
#define CONFIG_NETMASK 255.255.255.0
...
...
@@ -196,49 +196,49 @@
#ifdef CONFIG_440_EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
CFG_CMD_DATE |
\
CFG_CMD_DHCP |
\
CFG_CMD_DIAG |
\
CFG_CMD_ECHO |
\
CFG_CMD_EEPROM |
\
CFG_CMD_ELF |
\
/* CFG_CMD_EXT2
|*/
\
/* CFG_CMD_FAT |*/
\
CFG_CMD_I2C |
\
/* CFG_CMD_IDE |*/
\
CFG_CMD_IRQ |
\
/* CFG_CMD_KGDB |*/
\
CFG_CMD_MII |
\
CFG_CMD_PCI
|
\
CFG_CMD_PING |
\
CFG_CMD_REGINFO |
\
CFG_CMD_SDRAM |
\
CFG_CMD_FLASH
|
\
/* CFG_CMD_SPI |*/
\
CFG_CMD_USB |
\
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2
|*/
\
/* CFG_CMD_FAT |*/
\
CFG_CMD_I2C |
\
/* CFG_CMD_IDE |*/
\
CFG_CMD_IRQ |
\
/* CFG_CMD_KGDB |*/
\
CFG_CMD_MII |
\
CFG_CMD_PCI
|
\
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH
|
\
/* CFG_CMD_SPI |*/
\
CFG_CMD_USB |
\
0 ) & ~CFG_CMD_IMLS)
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
CFG_CMD_DATE |
\
CFG_CMD_DHCP |
\
CFG_CMD_DIAG |
\
CFG_CMD_ECHO |
\
CFG_CMD_EEPROM |
\
CFG_CMD_ELF |
\
/* CFG_CMD_EXT2
|*/
\
/* CFG_CMD_FAT |*/
\
CFG_CMD_I2C |
\
/* CFG_CMD_IDE |*/
\
CFG_CMD_IRQ |
\
/* CFG_CMD_KGDB |*/
\
CFG_CMD_MII |
\
CFG_CMD_PCI
|
\
CFG_CMD_PING |
\
CFG_CMD_REGINFO |
\
CFG_CMD_SDRAM |
\
CFG_CMD_FLASH
|
\
/* CFG_CMD_SPI |*/
\
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2
|*/
\
/* CFG_CMD_FAT |*/
\
CFG_CMD_I2C |
\
/* CFG_CMD_IDE |*/
\
CFG_CMD_IRQ |
\
/* CFG_CMD_KGDB |*/
\
CFG_CMD_MII |
\
CFG_CMD_PCI
|
\
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH
|
\
/* CFG_CMD_SPI |*/
\
0 ) & ~CFG_CMD_IMLS)
#endif
...
...
@@ -263,8 +263,8 @@
#define CFG_MEMTEST_END 0x0C00000
/* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000
/* default load address */
#define CFG_EXTBDINFO
1
/* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI
1
/* support kdi files */
#define CFG_EXTBDINFO 1
/* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI
1
/* support kdi files */
#define CFG_HZ 1000
/* decrementer freq: 1 ms ticks */
...
...
@@ -273,18 +273,18 @@
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI
/* include pci support
*/
#undef
CONFIG_PCI_PNP
/* do (not) pci plug-and-play
*/
#define CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup
*/
#define CFG_PCI_TARGBASE
0x80000000
/* PCIaddr mapped to CFG_PCI_MEMBASE */
#define CONFIG_PCI
/* include pci support
*/
#undef
CONFIG_PCI_PNP
/* do (not) pci plug-and-play
*/
#define CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup
*/
#define CFG_PCI_TARGBASE
0x80000000
/* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT
/* enable board pci_pre_init()
*/
#define CFG_PCI_PRE_INIT
/* enable board pci_pre_init()
*/
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014
/* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe
/* Whatever */
#define CFG_PCI_SUBSYS_VENDORID 0x1014
/* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe
/* Whatever */
/*
* For booting Linux, the board info and command line data
...
...
include/configs/walnut.h
浏览文件 @
095b8a37
...
...
@@ -34,21 +34,21 @@
*/
#define CONFIG_405GP 1
/* This is a PPC405 CPU */
#define CONFIG_4xx 1
/* ...member of PPC4xx family
*/
#define CONFIG_WALNUT
1
/* ...on a WALNUT board
*/
/* ...and on a SYCAMORE board
*/
#define CONFIG_4xx 1
/* ...member of PPC4xx family
*/
#define CONFIG_WALNUT
1
/* ...on a WALNUT board
*/
/* ...and on a SYCAMORE board
*/
#define CONFIG_BOARD_EARLY_INIT_F 1
/* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ
33333333
/* external frequency to pll
*/
#define CONFIG_SYS_CLK_FREQ
33333333
/* external frequency to pll
*/
#define CONFIG_PREBOOT "echo;"
\
#define CONFIG_PREBOOT "echo;"
\
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define
CONFIG_EXTRA_ENV_SETTINGS \
#define
CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=walnut\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
...
...
@@ -62,15 +62,15 @@
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"
\
"bootm\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"
\
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/walnut/uImage\0" \
"kernel_addr=fff80000\0" \
"ramdisk_addr=fff80000\0" \
"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;"
\
"cp.b 100000 fffc0000 40000;"
\
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
...
...
@@ -88,7 +88,7 @@
#define CFG_LOADS_BAUD_CHANGE 1
/* allow baudrate change */
#define CONFIG_MII 1
/* MII PHY management */
#define
CONFIG_PHY_ADDR 1
/* PHY address */
#define
CONFIG_PHY_ADDR 1
/* PHY address */
#define CONFIG_RTC_DS174x 1
/* use DS1743 RTC in Walnut */
...
...
@@ -105,7 +105,7 @@
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO
| \
CFG_CMD_REGINFO
| \
CFG_CMD_SDRAM | \
CFG_CMD_SNTP )
...
...
@@ -122,9 +122,9 @@
#define CFG_LONGHELP
/* undef to save memory */
#define CFG_PROMPT "=> "
/* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define
CFG_CBSIZE 1024
/* Console I/O Buffer Size */
#define
CFG_CBSIZE 1024
/* Console I/O Buffer Size */
#else
#define
CFG_CBSIZE 256
/* Console I/O Buffer Size */
#define
CFG_CBSIZE 256
/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
/* Print Buffer Size */
#define CFG_MAXARGS 16
/* max number of command args */
...
...
@@ -143,9 +143,9 @@
* set Linux BASE_BAUD to 403200.
*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef
CFG_EXT_SERIAL_CLOCK
/* external serial clock */
#undef
CFG_405_UART_ERRATA_59
/* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD
691200
#undef
CFG_EXT_SERIAL_CLOCK
/* external serial clock */
#undef
CFG_405_UART_ERRATA_59
/* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD
691200
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
...
...
@@ -154,10 +154,10 @@
#define CFG_LOAD_ADDR 0x100000
/* default load address */
#define CFG_EXTBDINFO 1
/* To use extended board_into (bd_t) */
#define
CFG_HZ 1000
/* decrementer freq: 1 ms ticks
*/
#define
CFG_HZ 1000
/* decrementer freq: 1 ms ticks
*/
#define CONFIG_AUTO_COMPLETE 1
/* add autocompletion support
*/
#define CONFIG_LOOPW
1
/* enable loopw command
*/
#define CONFIG_AUTO_COMPLETE 1
/* add autocompletion support
*/
#define CONFIG_LOOPW
1
/* enable loopw command
*/
#define CONFIG_ZERO_BOOTDELAY_CHECK
/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1
/* include version env variable */
...
...
@@ -168,7 +168,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_HARD_I2C 1
/* I2C with hardware support */
#undef
CONFIG_SOFT_I2C
/* I2C bit-banged */
#undef
CONFIG_SOFT_I2C
/* I2C bit-banged */
#define CFG_I2C_SPEED 400000
/* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
...
...
@@ -176,24 +176,24 @@
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0
/* configure ar pci adapter
*/
#define PCI_HOST_FORCE
1
/* configure as pci host
*/
#define PCI_HOST_AUTO
2
/* detected via arbiter enable
*/
#define CONFIG_PCI
/* include pci support
*/
#define CONFIG_PCI_HOST
PCI_HOST_FORCE
/* select pci host function
*/
#define CONFIG_PCI_PNP
/* do pci plug-and-play
*/
/* resource configuration
*/
#define PCI_HOST_ADAPTER 0
/* configure ar pci adapter
*/
#define PCI_HOST_FORCE
1
/* configure as pci host
*/
#define PCI_HOST_AUTO
2
/* detected via arbiter enable
*/
#define CONFIG_PCI
/* include pci support
*/
#define CONFIG_PCI_HOST
PCI_HOST_FORCE
/* select pci host function
*/
#define CONFIG_PCI_PNP
/* do pci plug-and-play
*/
/* resource configuration
*/
#define CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8
/* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe
/* Whatever */
#define CFG_PCI_PTM1LA
0x00000000
/* point to sdram
*/
#define CFG_PCI_PTM1MS
0x80000001
/* 2GB, enable hard-wired to 1
*/
#define CFG_PCI_PTM1PCI 0x00000000
/* Host: use this pci address
*/
#define CFG_PCI_PTM2LA
0x00000000
/* disabled
*/
#define CFG_PCI_PTM2MS
0x00000000
/* disabled
*/
#define CFG_PCI_PTM2PCI 0x04000000
/* Host: use this pci address
*/
#define CFG_PCI_PTM1LA
0x00000000
/* point to sdram
*/
#define CFG_PCI_PTM1MS
0x80000001
/* 2GB, enable hard-wired to 1
*/
#define CFG_PCI_PTM1PCI 0x00000000
/* Host: use this pci address
*/
#define CFG_PCI_PTM2LA
0x00000000
/* disabled
*/
#define CFG_PCI_PTM2MS
0x00000000
/* disabled
*/
#define CFG_PCI_PTM2PCI 0x04000000
/* Host: use this pci address
*/
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
...
...
@@ -209,10 +209,10 @@
/*
* Define here the location of the environment variables (FLASH or NVRAM).
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
*
supported for backward compatibility.
*
supported for backward compatibility.
*/
#if 1
#define CFG_ENV_IS_IN_FLASH
1
/* use FLASH for environment vars */
#define CFG_ENV_IS_IN_FLASH
1
/* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_NVRAM 1
/* use NVRAM for environment vars */
#endif
...
...
@@ -227,8 +227,8 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE
/* FLASH bank #0
*/
#define FLASH_BASE1_PRELIM 0
/* FLASH bank #1
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE
/* FLASH bank #0
*/
#define FLASH_BASE1_PRELIM 0
/* FLASH bank #1
*/
#define CFG_MAX_FLASH_BANKS 1
/* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256
/* max number of sectors on one chip */
...
...
@@ -238,14 +238,14 @@
#define CFG_FLASH_EMPTY_INFO
/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_ADDR0
0x5555
#define CFG_FLASH_ADDR1
0x2aaa
#define CFG_FLASH_WORD_SIZE
unsigned char
#define CFG_FLASH_ADDR0
0x5555
#define CFG_FLASH_ADDR1
0x2aaa
#define CFG_FLASH_WORD_SIZE
unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000
/* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000
/* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define
CFG_ENV_SIZE 0x4000
/* Total Size of Environment Sector */
#define
CFG_ENV_SIZE 0x4000
/* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
...
...
@@ -280,44 +280,44 @@
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CFG_EBC_PB0AP 0x9B015480
#define CFG_EBC_PB0CR 0xFFF18000
/* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit
*/
#define CFG_EBC_PB0CR 0xFFF18000
/* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit
*/
#define CFG_EBC_PB1AP 0x02815480
#define CFG_EBC_PB1CR 0xF0018000
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit
*/
#define CFG_EBC_PB1CR 0xF0018000
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit
*/
#define CFG_EBC_PB2AP 0x04815A80
#define CFG_EBC_PB2CR 0xF0118000
/* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit
*/
#define CFG_EBC_PB2CR 0xF0118000
/* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit
*/
#define CFG_EBC_PB3AP 0x01815280
#define CFG_EBC_PB3CR 0xF0218000
/* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit
*/
#define CFG_EBC_PB3CR 0xF0218000
/* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit
*/
#define CFG_EBC_PB7AP 0x01815280
#define CFG_EBC_PB7CR 0xF0318000
/* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit
*/
#define CFG_EBC_PB7CR 0xF0318000
/* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit
*/
/*-----------------------------------------------------------------------
* External peripheral base address
*-----------------------------------------------------------------------
*/
#define
CFG_KEY_REG_BASE_ADDR 0xF0100000
#define
CFG_IR_REG_BASE_ADDR 0xF0200000
#define
CFG_FPGA_REG_BASE_ADDR 0xF0300000
#define
CFG_KEY_REG_BASE_ADDR 0xF0100000
#define
CFG_IR_REG_BASE_ADDR 0xF0200000
#define
CFG_FPGA_REG_BASE_ADDR 0xF0300000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area
*/
#define CFG_INIT_DCACHE_CS
4
/* use cs # 4 for data cache memory */
#define CFG_INIT_DCACHE_CS
4
/* use cs # 4 for data cache memory */
#define CFG_INIT_RAM_ADDR
0x40000000
/* inside of SDRAM
*/
#define CFG_INIT_RAM_END
0x2000
/* End of used area in RAM
*/
#define CFG_INIT_RAM_ADDR
0x40000000
/* inside of SDRAM
*/
#define CFG_INIT_RAM_END
0x2000
/* End of used area in RAM
*/
#define CFG_GBL_DATA_SIZE 128
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET
CFG_GBL_DATA_OFFSET
#define CFG_INIT_SP_OFFSET
CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
*/
#define SPD_EEPROM_ADDRESS
0x50
#define SPD_EEPROM_ADDRESS
0x50
/*
* Internal Definitions
...
...
include/configs/yellowstone.h
浏览文件 @
095b8a37
...
...
@@ -28,11 +28,11 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YELLOWSTONE 1
/* Board is BAMBOO
*/
#define CONFIG_YELLOWSTONE 1
/* Board is BAMBOO
*/
#define CONFIG_440_GR 1
/* Specific PPC440GR support */
#define CONFIG_4xx 1
/* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F
1
/* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_F 1
/* Call board_early_init_f */
#undef CFG_DRAM_TEST
/* disable - takes long time! */
#define CONFIG_SYS_CLK_FREQ 66666666
/* external freq to pll */
...
...
@@ -63,14 +63,14 @@
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000
/* DCache */
#define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256
/* num bytes initial data */
#define CFG_GBL_DATA_SIZE 256
/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024)
/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024)
/* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024)
/* 128MB
*/
#define CFG_SDRAM_BANKS
(2)
#define CFG_KBYTES_SDRAM ( 128 * 1024)
/* 128MB
*/
#define CFG_SDRAM_BANKS
(2)
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
...
...
@@ -92,7 +92,7 @@
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10)
/* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1
/* DS1556 RTC */
#define CONFIG_RTC_DS1556 1
/* DS1556 RTC */
/*-----------------------------------------------------------------------
* FLASH related
...
...
@@ -107,7 +107,7 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM
/* Don't use SPD EEPROM for setup */
#undef CONFIG_SPD_EEPROM
/* Don't use SPD EEPROM for setup */
/*-----------------------------------------------------------------------
* I2C
...
...
@@ -121,7 +121,7 @@
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef
CFG_ENV_IS_IN_NVRAM
/*No NVRAM on board*/
#undef
CFG_ENV_IS_IN_NVRAM
/*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH
/* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1
...
...
@@ -144,7 +144,7 @@
#define CFG_LOADS_BAUD_CHANGE 1
/* allow baudrate change */
#define CONFIG_MII 1
/* MII PHY management */
#define CONFIG_NET_MULTI 1
/* required for netconsole */
#define CONFIG_NET_MULTI 1
/* required for netconsole */
#define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1
/* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1
/* PHY address, See schematics */
...
...
@@ -178,48 +178,48 @@
#ifdef CONFIG_440_EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/*
CFG_CMD_EXT2 |*/
\
/*
CFG_CMD_EXT2 |*/
\
/* CFG_CMD_FAT |*/
\
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/
\
CFG_CMD_IRQ | \
/*
CFG_CMD_KGDB |*/
\
CFG_CMD_MII
| \
/*
CFG_CMD_KGDB |*/
\
CFG_CMD_MII
| \
CFG_CMD_PCI | \
CFG_CMD_PING |
\
CFG_CMD_REGINFO |
\
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH
| \
CFG_CMD_FLASH
| \
/* CFG_CMD_SPI |*/
\
CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS)
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/*
CFG_CMD_EXT2 |*/
\
/*
CFG_CMD_EXT2 |*/
\
/* CFG_CMD_FAT |*/
\
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/
\
CFG_CMD_IRQ | \
/*
CFG_CMD_KGDB |*/
\
CFG_CMD_MII
| \
/*
CFG_CMD_KGDB |*/
\
CFG_CMD_MII
| \
CFG_CMD_PCI | \
CFG_CMD_PING |
\
CFG_CMD_REGINFO |
\
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH
| \
CFG_CMD_FLASH
| \
/* CFG_CMD_SPI |*/
\
0 ) & ~CFG_CMD_IMLS)
#endif
...
...
@@ -246,7 +246,7 @@
#define CFG_LOAD_ADDR 0x100000
/* default load address */
#define CFG_EXTBDINFO 1
/* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI
1
/* support kdi files */
#define CONFIG_LYNXKDI
1
/* support kdi files */
#define CFG_HZ 1000
/* decrementer freq: 1 ms ticks */
...
...
@@ -255,18 +255,18 @@
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI
/* include pci support
*/
#undef
CONFIG_PCI_PNP
/* do (not) pci plug-and-play
*/
#define CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup
*/
#define CFG_PCI_TARGBASE 0x80000000
/* PCIaddr mapped to CFG_PCI_MEMBASE */
#define CONFIG_PCI
/* include pci support
*/
#undef
CONFIG_PCI_PNP
/* do (not) pci plug-and-play
*/
#define CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup
*/
#define CFG_PCI_TARGBASE 0x80000000
/* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT
/* enable board pci_pre_init()
*/
#define CFG_PCI_PRE_INIT
/* enable board pci_pre_init()
*/
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014
/* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe
/* Whatever */
#define CFG_PCI_SUBSYS_VENDORID 0x1014
/* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe
/* Whatever */
/*
* For booting Linux, the board info and command line data
...
...
include/configs/yosemite.h
浏览文件 @
095b8a37
...
...
@@ -28,11 +28,11 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YOSEMITE 1
/* Board is BAMBOO
*/
#define CONFIG_YOSEMITE 1
/* Board is BAMBOO
*/
#define CONFIG_440_EP 1
/* Specific PPC440EP support */
#define CONFIG_4xx 1
/* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F
1
/* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_F 1
/* Call board_early_init_f */
#undef CFG_DRAM_TEST
/* disable - takes long time! */
#define CONFIG_SYS_CLK_FREQ 66666666
/* external freq to pll */
...
...
@@ -63,14 +63,14 @@
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000
/* DCache */
#define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256
/* num bytes initial data */
#define CFG_GBL_DATA_SIZE 256
/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024)
/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024)
/* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024)
/* 128MB
*/
#define CFG_SDRAM_BANKS
(2)
#define CFG_KBYTES_SDRAM ( 128 * 1024)
/* 128MB
*/
#define CFG_SDRAM_BANKS
(2)
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
...
...
@@ -92,7 +92,7 @@
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10)
/* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1
/* DS1556 RTC */
#define CONFIG_RTC_DS1556 1
/* DS1556 RTC */
/*-----------------------------------------------------------------------
* FLASH related
...
...
@@ -105,9 +105,9 @@
#define CFG_FLASH_ERASE_TOUT 120000
/* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 120000
/* Timeout for Flash Write (in ms) */
#else
#define CFG_FLASH_CFI
/* The flash is CFI compatible
*/
#define CFG_FLASH_CFI_DRIVER
/* Use common CFI driver
*/
#define CFG_FLASH_CFI_AMD_RESET
1
/* AMD RESET for STM 29W320DB!
*/
#define CFG_FLASH_CFI
/* The flash is CFI compatible
*/
#define CFG_FLASH_CFI_DRIVER
/* Use common CFI driver
*/
#define CFG_FLASH_CFI_AMD_RESET
1
/* AMD RESET for STM 29W320DB!
*/
#define CFG_MAX_FLASH_BANKS 1
/* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512
/* max number of sectors on one chip */
...
...
@@ -121,7 +121,7 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM
/* Don't use SPD EEPROM for setup */
#undef CONFIG_SPD_EEPROM
/* Don't use SPD EEPROM for setup */
/*-----------------------------------------------------------------------
* I2C
...
...
@@ -135,7 +135,7 @@
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef
CFG_ENV_IS_IN_NVRAM
/*No NVRAM on board*/
#undef
CFG_ENV_IS_IN_NVRAM
/*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH
/* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1
...
...
@@ -158,7 +158,7 @@
#define CFG_LOADS_BAUD_CHANGE 1
/* allow baudrate change */
#define CONFIG_MII 1
/* MII PHY management */
#define CONFIG_NET_MULTI 1
/* required for netconsole */
#define CONFIG_NET_MULTI 1
/* required for netconsole */
#define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1
/* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1
/* PHY address, See schematics */
...
...
@@ -192,48 +192,48 @@
#ifdef CONFIG_440_EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/*
CFG_CMD_EXT2 |*/
\
/*
CFG_CMD_EXT2 |*/
\
/* CFG_CMD_FAT |*/
\
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/
\
CFG_CMD_IRQ | \
/*
CFG_CMD_KGDB |*/
\
CFG_CMD_MII
| \
/*
CFG_CMD_KGDB |*/
\
CFG_CMD_MII
| \
CFG_CMD_PCI | \
CFG_CMD_PING |
\
CFG_CMD_REGINFO |
\
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH
| \
CFG_CMD_FLASH
| \
/* CFG_CMD_SPI |*/
\
CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS)
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL
| \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/*
CFG_CMD_EXT2 |*/
\
/*
CFG_CMD_EXT2 |*/
\
/* CFG_CMD_FAT |*/
\
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/
\
CFG_CMD_IRQ | \
/*
CFG_CMD_KGDB |*/
\
CFG_CMD_MII
| \
/*
CFG_CMD_KGDB |*/
\
CFG_CMD_MII
| \
CFG_CMD_PCI | \
CFG_CMD_PING |
\
CFG_CMD_REGINFO |
\
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH
| \
CFG_CMD_FLASH
| \
/* CFG_CMD_SPI |*/
\
0 ) & ~CFG_CMD_IMLS)
#endif
...
...
@@ -260,7 +260,7 @@
#define CFG_LOAD_ADDR 0x100000
/* default load address */
#define CFG_EXTBDINFO 1
/* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI
1
/* support kdi files */
#define CONFIG_LYNXKDI
1
/* support kdi files */
#define CFG_HZ 1000
/* decrementer freq: 1 ms ticks */
...
...
@@ -269,18 +269,18 @@
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI
/* include pci support
*/
#undef
CONFIG_PCI_PNP
/* do (not) pci plug-and-play
*/
#define CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup
*/
#define CFG_PCI_TARGBASE 0x80000000
/* PCIaddr mapped to CFG_PCI_MEMBASE */
#define CONFIG_PCI
/* include pci support
*/
#undef
CONFIG_PCI_PNP
/* do (not) pci plug-and-play
*/
#define CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup
*/
#define CFG_PCI_TARGBASE 0x80000000
/* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT
/* enable board pci_pre_init()
*/
#define CFG_PCI_PRE_INIT
/* enable board pci_pre_init()
*/
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014
/* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe
/* Whatever */
#define CFG_PCI_SUBSYS_VENDORID 0x1014
/* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe
/* Whatever */
/*
* For booting Linux, the board info and command line data
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录