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提交 080d8975 编写于 作者: T Tom Rini
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

上级 adcdeacc 08ad9b06
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Makefile
浏览文件 @ 080d8975
......@@ -740,7 +740,11 @@ ALL-y += u-boot.srec u-boot.bin System.map
ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
......@@ -925,6 +929,21 @@ endif
u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
$(call if_changed,cat)
#Add a target to create boot binary having SPL binary in PBI format
#concatenated with u-boot binary. It is need by PowerPC SoC having
#internal SRAM <= 512KB.
MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
--gap-fill=0xff
u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE
$(call if_changed,pad_cat)
# PPC4xx needs the SPL at the end of the image, since the reset vector
# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
# and need to introduce a new build target with the full blown U-Boot
......
README
浏览文件 @ 080d8975
......@@ -431,6 +431,14 @@ The following options need to be configured:
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
CONFIG_SYS_CPC_REINIT_F
This CONFIG is defined when the CPC is configured as SRAM at the
time of U-boot entry and is required to be re-initialized.
CONFIG_DEEP_SLEEP
Inidcates this SoC supports deep sleep feature. If deep sleep is
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
......@@ -458,6 +466,9 @@ The following options need to be configured:
CONFIG_SYS_FSL_DDRC_GEN3
Freescale DDR3 controller.
CONFIG_SYS_FSL_DDRC_GEN4
Freescale DDR4 controller.
CONFIG_SYS_FSL_DDRC_ARM_GEN3
Freescale DDR3 controller for ARM-based SoCs.
......@@ -473,7 +484,15 @@ The following options need to be configured:
CONFIG_SYS_FSL_DDR3
Board config to use DDR3. It can be enabled for SoCs with
Freescale DDR3 controllers.
Freescale DDR3 or DDR3L controllers.
CONFIG_SYS_FSL_DDR3L
Board config to use DDR3L. It can be enabled for SoCs with
DDR3L controllers.
CONFIG_SYS_FSL_DDR4
Board config to use DDR4. It can be enabled for SoCs with
DDR4 controllers.
CONFIG_SYS_FSL_IFC_BE
Defines the IFC controller register space as Big Endian
......@@ -490,6 +509,10 @@ The following options need to be configured:
PBI commands can be used to configure SoC before it starts the execution.
Please refer doc/README.pblimage for more details
CONFIG_SPL_FSL_PBL
It adds a target to create boot binary having SPL binary in PBI format
concatenated with u-boot binary.
CONFIG_SYS_FSL_DDR_BE
Defines the DDR controller register space as Big Endian
......@@ -3317,6 +3340,9 @@ FIT uImage format:
continuing (the hardware starts execution after just
loading the first page rather than the full 4K).
CONFIG_SPL_SKIP_RELOCATE
Avoid SPL relocation
CONFIG_SPL_NAND_BASE
Include nand_base.c in the SPL. Requires
CONFIG_SPL_NAND_DRIVERS.
......@@ -4502,8 +4528,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros
are used to identify the storage device (NOR flash, SPI, etc) and the address
within that device.
- CONFIG_SYS_QE_FMAN_FW_ADDR
The address in the storage device where the firmware is located. The
- CONFIG_SYS_FMAN_FW_ADDR
The address in the storage device where the FMAN microcode is located. The
meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
is also specified.
- CONFIG_SYS_QE_FW_ADDR
The address in the storage device where the QE microcode is located. The
meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
is also specified.
......
arch/powerpc/cpu/mpc85xx/Makefile
浏览文件 @ 080d8975
......@@ -102,7 +102,9 @@ obj-y += cpu.o
obj-y += cpu_init.o
obj-y += cpu_init_early.o
obj-y += interrupts.o
ifneq ($(CONFIG_QEMU_E500),y)
obj-y += speed.o
endif
obj-y += tlb.o
obj-y += traps.o
......
arch/powerpc/cpu/mpc85xx/cmd_errata.c
浏览文件 @ 080d8975
......@@ -113,6 +113,21 @@ static void check_erratum_a4580(uint32_t svr)
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
/*
* This workaround can be implemented in PBI, or by u-boot.
*/
static void check_erratum_a007212(void)
{
u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
if (in_be32(plldgdcr) & 0x1fe) {
/* check if PLL ratio is set by workaround */
puts("Work-around for Erratum A007212 enabled\n");
}
}
#endif
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
......@@ -268,6 +283,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
puts("Work-around for Erratum A005125 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007075
if (has_erratum_a007075())
puts("Work-around for Erratum A007075 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
......@@ -277,6 +296,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (has_erratum_a006261())
puts("Work-around for Erratum A006261 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
check_erratum_a007212();
#endif
return 0;
}
......
arch/powerpc/cpu/mpc85xx/cpu.c
浏览文件 @ 080d8975
......@@ -130,6 +130,11 @@ int checkcpu (void)
get_sys_info(&sysinfo);
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
if (sysinfo.diff_sysclk == 1)
puts("Single Source Clock Configuration\n");
#endif
puts("Clock Configuration:");
for_each_cpu(i, core, nr_cores, mask) {
if (!(i & 3))
......@@ -272,7 +277,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#define CONFIG_SYS_FSL_TBCLK_DIV 8
#endif
unsigned long get_tbclk (void)
__weak unsigned long get_tbclk (void)
{
unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
......@@ -338,7 +343,8 @@ void mpc85xx_reginfo(void)
!defined(CONFIG_SYS_INIT_L2_ADDR)
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
defined(CONFIG_QEMU_E500)
return fsl_ddr_sdram_size();
#else
return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
......
arch/powerpc/cpu/mpc85xx/cpu_init.c
浏览文件 @ 080d8975
......@@ -33,9 +33,35 @@
#endif
#include "../../../../drivers/block/fsl_sata.h"
#ifdef CONFIG_U_QE
#include "../../../../drivers/qe/qe.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
* For deriving usb clock from 100MHz sysclk, reference divisor is set
* to a value of 5, which gives an intermediate value 20(100/5). The
* multiplication factor integer is set to 24, which when multiplied to
* above intermediate value provides clock for usb ip.
*/
void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
{
sys_info_t sysinfo;
get_sys_info(&sysinfo);
if (sysinfo.diff_sysclk == 1) {
clrbits_be32(&usb_phy->pllprg[1],
CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
setbits_be32(&usb_phy->pllprg[1],
CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
}
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
{
......@@ -84,7 +110,7 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
#endif
#ifdef CONFIG_QE
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
......@@ -173,17 +199,14 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
#endif
#ifdef CONFIG_SYS_FSL_CPC
static void enable_cpc(void)
#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
static void disable_cpc_sram(void)
{
int i;
u32 size = 0;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
u32 cpccfg0 = in_be32(&cpc->cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
#ifdef CONFIG_RAMBOOT_PBL
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
......@@ -198,8 +221,21 @@ static void enable_cpc(void)
out_be32(&cpc->cpccsr0, 0);
out_be32(&cpc->cpcsrcr0, 0);
}
}
}
#endif
static void enable_cpc(void)
{
int i;
u32 size = 0;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
u32 cpccfg0 = in_be32(&cpc->cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
#endif
......@@ -267,11 +303,77 @@ static void corenet_tb_init(void)
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
void fsl_erratum_a007212_workaround(void)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_pll_ratio;
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
#endif
#endif
/*
* Even this workaround applies to selected version of SoCs, it is
* safe to apply to all versions, with the limitation of odd ratios.
* If RCW has disabled DDR PLL, we have to apply this workaround,
* otherwise DDR will not work.
*/
ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
/* check if RCW sets ratio to 0, required by this workaround */
if (ddr_pll_ratio != 0)
return;
ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
/* check if reserved bits have the desired ratio */
if (ddr_pll_ratio == 0) {
printf("Error: Unknown DDR PLL ratio!\n");
return;
}
ddr_pll_ratio >>= 1;
setbits_be32(plldadcr1, 0x02000001);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
setbits_be32(plldadcr2, 0x02000001);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
setbits_be32(plldadcr3, 0x02000001);
#endif
#endif
setbits_be32(dpdovrcr4, 0xe0000000);
out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
#endif
#endif
udelay(100);
clrbits_be32(plldadcr1, 0x02000001);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
clrbits_be32(plldadcr2, 0x02000001);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
clrbits_be32(plldadcr3, 0x02000001);
#endif
#endif
clrbits_be32(dpdovrcr4, 0xe0000000);
}
#endif
void cpu_init_f (void)
{
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
......@@ -298,6 +400,10 @@ void cpu_init_f (void)
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
disable_law(law.index);
#if defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram();
#endif
#endif
#ifdef CONFIG_CPM2
......@@ -309,10 +415,12 @@ void cpu_init_f (void)
#if defined(CONFIG_CPM2)
m8560_cpm_reset();
#endif
#ifdef CONFIG_QE
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
/* Config QE ioports */
config_qe_ioports();
#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
......@@ -330,6 +438,17 @@ void cpu_init_f (void)
in_be32(&gur->dcsrcr);
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
}
/* Implement a dummy function for those platforms w/o SERDES */
......@@ -598,6 +717,9 @@ skip_l2:
puts("disabled\n");
#endif
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram();
#endif
enable_cpc();
#ifndef CONFIG_SYS_FSL_NO_SERDES
......@@ -716,6 +838,9 @@ skip_l2:
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
usb_single_source_clk_configure(usb_phy);
#endif
setbits_be32(&usb_phy->port1.ctrl,
CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
setbits_be32(&usb_phy->port1.drvvbuscfg,
......@@ -767,8 +892,6 @@ skip_l2:
return 0;
}
extern void setup_ivors(void);
void arch_preboot_os(void)
{
u32 msr;
......@@ -781,8 +904,6 @@ void arch_preboot_os(void)
msr = mfmsr();
msr &= ~(MSR_ME|MSR_CE);
mtmsr(msr);
setup_ivors();
}
#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
......@@ -797,21 +918,13 @@ int sata_initialize(void)
void cpu_secondary_init_r(void)
{
#ifdef CONFIG_QE
#ifdef CONFIG_U_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
#elif defined CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
int ret;
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
/* load QE firmware from NAND flash to DDR first */
ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
&fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
if (ret && ret == -EUCLEAN) {
printf ("NAND read for QE firmware at offset %x failed %d\n",
CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
}
#endif
#ifdef CONFIG_QE
qe_init(qe_base);
qe_reset();
#endif
......
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
浏览文件 @ 080d8975
......@@ -79,7 +79,7 @@ void setup_ifc(void)
#endif
/* We run cpu_init_early_f in AS = 1 */
void cpu_init_early_f(void)
void cpu_init_early_f(void *fdt)
{
u32 mas0, mas1, mas2, mas3, mas7;
int i;
......@@ -102,6 +102,12 @@ void cpu_init_early_f(void)
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
*/
gd->fdt_blob = fdt;
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
......
arch/powerpc/cpu/mpc85xx/fdt.c
浏览文件 @ 080d8975
......@@ -275,12 +275,16 @@ static inline void ft_fixup_l2cache(void *blob)
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
/* Only initialize every eighth thread */
if (reg && !((*reg) % 8))
if (reg && !((*reg) % 8)) {
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
(*reg / 4) + 32 + 1);
}
#else
if (reg)
#endif
if (reg) {
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
(*reg * 2) + 32 + 1);
(*reg * 2) + 32 + 1);
}
#endif
#endif
fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
......@@ -582,6 +586,33 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
#if defined(CONFIG_PPC_T1040)
static void fdt_fixup_l2_switch(void *blob)
{
uchar l2swaddr[6];
int node;
/* The l2switch node from device-tree has
* compatible string "vitesse-9953" */
node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
if (node == -FDT_ERR_NOTFOUND)
/* no l2switch node has been found */
return;
/* Get MAC address for the l2switch from "l2switchaddr"*/
if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) {
printf("Warning: MAC address for l2switch not found\n");
memset(l2swaddr, 0, sizeof(l2swaddr));
}
/* Add MAC address to l2switch node */
fdt_setprop(blob, node, "local-mac-address", l2swaddr,
sizeof(l2swaddr));
}
#else
#define fdt_fixup_l2_switch(x)
#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
int off;
......@@ -719,6 +750,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"clock-frequency", gd->bus_clk/2, 1);
fdt_fixup_usb(blob);
fdt_fixup_l2_switch(blob);
}
/*
......
arch/powerpc/cpu/mpc85xx/fixed_ivor.S 已删除 100644 → 0
浏览文件 @ adcdeacc
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* Kumar Gala <kumar.gala@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* This file is intended to be included by other asm code since
* we will want to execute this on both the primary core when
* it does a bootm and the secondary core's that get released
* out of the spin table */
#define SET_IVOR(vector_number, vector_offset) \
li r3,vector_offset@l; \
mtspr SPRN_IVOR##vector_number,r3;
#define SET_GIVOR(vector_number, vector_offset) \
li r3,vector_offset@l; \
mtspr SPRN_GIVOR##vector_number,r3;
SET_IVOR(0, 0x020) /* Critical Input */
SET_IVOR(1, 0x000) /* Machine Check */
SET_IVOR(2, 0x060) /* Data Storage */
SET_IVOR(3, 0x080) /* Instruction Storage */
SET_IVOR(4, 0x0a0) /* External Input */
SET_IVOR(5, 0x0c0) /* Alignment */
SET_IVOR(6, 0x0e0) /* Program */
SET_IVOR(7, 0x100) /* FP Unavailable */
SET_IVOR(8, 0x120) /* System Call */
SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
SET_IVOR(10, 0x160) /* Decrementer */
SET_IVOR(11, 0x180) /* Fixed Interval Timer */
SET_IVOR(12, 0x1a0) /* Watchdog Timer */
SET_IVOR(13, 0x1c0) /* Data TLB Error */
SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
SET_IVOR(15, 0x040) /* Debug */
/* e500v1 & e500v2 only */
#ifndef CONFIG_E500MC
SET_IVOR(32, 0x200) /* SPE Unavailable */
SET_IVOR(33, 0x220) /* Embedded FP Data */
SET_IVOR(34, 0x240) /* Embedded FP Round */
#endif
SET_IVOR(35, 0x260) /* Performance monitor */
/* e500mc only */
#ifdef CONFIG_E500MC
SET_IVOR(36, 0x280) /* Processor doorbell */
SET_IVOR(37, 0x2a0) /* Processor doorbell critical */
SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */
SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */
SET_IVOR(40, 0x300) /* Hypervisor system call */
SET_IVOR(41, 0x320) /* Hypervisor Priviledge */
SET_GIVOR(2, 0x060) /* Guest Data Storage */
SET_GIVOR(3, 0x080) /* Guest Instruction Storage */
SET_GIVOR(4, 0x0a0) /* Guest External Input */
SET_GIVOR(8, 0x120) /* Guest System Call */
SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */
SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */
#endif
arch/powerpc/cpu/mpc85xx/qe_io.c
浏览文件 @ 080d8975
......@@ -12,7 +12,7 @@
#include "asm/io.h"
#include "asm/immap_85xx.h"
#if defined(CONFIG_QE)
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
#define NUM_OF_PINS 32
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
{
......
arch/powerpc/cpu/mpc85xx/release.S
浏览文件 @ 080d8975
......@@ -405,9 +405,6 @@ __second_half_boot_page:
bne 3b
isync
/* setup IVORs to match fixed offsets */
#include "fixed_ivor.S"
/* get the upper bits of the addr */
lwz r11,ENTRY_ADDR_UPPER(r10)
......
arch/powerpc/cpu/mpc85xx/speed.c
浏览文件 @ 080d8975
......@@ -74,28 +74,33 @@ void get_sys_info(sys_info_t *sys_info)
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
uint single_src;
#endif
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
uint ddr_refclk_sel;
unsigned int porsr1_sys_clk;
porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
& FSL_DCFG_PORSR1_SYSCLK_MASK;
if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
sys_info->diff_sysclk = 1;
else
sys_info->diff_sysclk = 0;
/*
* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
* are driven by separate DDR Refclock or single source
* differential clock.
*/
single_src = (in_be32(&gur->rcwsr[5]) >>
ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
/*
* For single source clocking, both ddrclock and syclock
* For single source clocking, both ddrclock and sysclock
* are driven by differential sysclock.
*/
if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
printf("Single Source Clock Configuration\n");
if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
} else
else
#endif
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
......@@ -107,6 +112,13 @@ void get_sys_info(sys_info_t *sys_info)
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
if (mem_pll_rat == 0) {
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
}
#endif
/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
......@@ -151,8 +163,8 @@ void get_sys_info(sys_info_t *sys_info)
sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
defined(CONFIG_PPC_T2081)
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#else
......@@ -336,6 +348,10 @@ void get_sys_info(sys_info_t *sys_info)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#ifdef CONFIG_U_QE
sys_info->freq_qe = sys_info->freq_systembus / 2;
#endif
#else /* CONFIG_FSL_CORENET */
uint plat_ratio, e500_ratio, half_freq_systembus;
int i;
......
arch/powerpc/cpu/mpc85xx/start.S
浏览文件 @ 080d8975
......@@ -26,6 +26,8 @@
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
#define LAW_EN 0x80000000
#if defined(CONFIG_NAND_SPL) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
#define MINIMAL_SPL
......@@ -78,6 +80,13 @@ _start_e500:
li r1,MSR_DE
mtmsr r1
/*
* If we got an ePAPR device tree pointer passed in as r3, we need that
* later in cpu_init_early_f(). Save it to a safe register before we
* clobber it so that we can fetch it from there later.
*/
mr r24, r3
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr r3,SPRN_SVR
rlwinm r3,r3,0,0xff
......@@ -115,7 +124,8 @@ _start_e500:
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
!defined(CONFIG_E6500)
/* ISBC uses L2 as stack.
* Disable L2 cache here so that u-boot can enable it later
* as part of it's normal flow
......@@ -460,7 +470,8 @@ nexti: mflr r1 /* R1 = our PC */
2: cmpw r3, r4
blt 1b
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
!defined(CONFIG_SECURE_BOOT)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
......@@ -481,12 +492,6 @@ nexti: mflr r1 /* R1 = our PC */
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
0, BOOKE_PAGESZ_1M, \
CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
......@@ -574,7 +579,6 @@ infinite_debug_loop:
#ifdef CONFIG_FSL_CORENET
#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
#define LAW_EN 0x80000000
#define LAW_SIZE_4K 0xb
#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
#define CCSRAR_C 0x80000000 /* Commit */
......@@ -1142,6 +1146,10 @@ _start_cont:
mr r1,r3 /* Transfer to SP(r1) */
GET_GOT
/* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
mr r3, r24
bl cpu_init_early_f
/* switch back to AS = 0 */
......@@ -1644,6 +1652,7 @@ relocate_code:
mr r10,r5 /* Save copy of Destination Address */
GET_GOT
#ifndef CONFIG_SPL_SKIP_RELOCATE
mr r3,r5 /* Destination Address */
lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
......@@ -1734,6 +1743,7 @@ relocate_code:
mtlr r0
blr /* NEVER RETURNS! */
#endif
.globl in_ram
in_ram:
......@@ -1965,10 +1975,4 @@ flush_dcache:
isync
blr
.globl setup_ivors
setup_ivors:
#include "fixed_ivor.S"
blr
#endif /* !MINIMAL_SPL */
arch/powerpc/cpu/mpc85xx/t1040_ids.c
浏览文件 @ 080d8975
......@@ -46,6 +46,7 @@ struct liodn_id_table liodn_tbl[] = {
SET_DMA_LIODN(2, 227),
/* SET_NEXUS_LIODN(557), -- not yet implemented */
SET_QE_LIODN(559),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
......
arch/powerpc/cpu/mpc85xx/tlb.c
浏览文件 @ 080d8975
......@@ -24,7 +24,7 @@ void invalidate_tlb(u8 tlb)
mtspr(MMUCSR0, 0x2);
}
void init_tlbs(void)
__weak void init_tlbs(void)
{
int i;
......@@ -236,20 +236,26 @@ void init_addr_map(void)
}
#endif
unsigned int
setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
enum tlb_map_type map_type)
{
int i;
unsigned int tlb_size;
unsigned int wimge = MAS2_M;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
unsigned int wimge;
unsigned int perm;
unsigned int max_cam, tsize_mask;
u64 size, memsize = (u64)memsize_in_meg << 20;
if (map_type == TLB_MAP_RAM) {
perm = MAS3_SX|MAS3_SW|MAS3_SR;
wimge = MAS2_M;
#ifdef CONFIG_SYS_PPC_DDR_WIMGE
wimge = CONFIG_SYS_PPC_DDR_WIMGE;
wimge = CONFIG_SYS_PPC_DDR_WIMGE;
#endif
size = min(memsize, CONFIG_MAX_MEM_MAPPED);
} else {
perm = MAS3_SW|MAS3_SR;
wimge = MAS2_I|MAS2_G;
}
if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
/* Convert (4^max) kB to (2^max) bytes */
max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
......@@ -261,11 +267,11 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
}
for (i = 0; size && i < 8; i++) {
int ram_tlb_index = find_free_tlbcam();
int tlb_index = find_free_tlbcam();
u32 camsize = __ilog2_u64(size) & tsize_mask;
u32 align = __ilog2(ram_tlb_address) & tsize_mask;
u32 align = __ilog2(v_addr) & tsize_mask;
if (ram_tlb_index == -1)
if (tlb_index == -1)
break;
if (align == -2) align = max_cam;
......@@ -277,18 +283,29 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
tlb_size = camsize - 10;
set_tlb(1, ram_tlb_address, p_addr,
MAS3_SX|MAS3_SW|MAS3_SR, wimge,
0, ram_tlb_index, tlb_size, 1);
set_tlb(1, v_addr, p_addr, perm, wimge,
0, tlb_index, tlb_size, 1);
size -= 1ULL << camsize;
memsize -= 1ULL << camsize;
ram_tlb_address += 1UL << camsize;
v_addr += 1UL << camsize;
p_addr += 1UL << camsize;
}
return size;
}
unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
unsigned int memsize_in_meg)
{
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
u64 memsize = (u64)memsize_in_meg << 20;
memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
if (memsize)
print_size(memsize, " left unmapped\n");
return memsize_in_meg;
}
......
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
浏览文件 @ 080d8975
......@@ -4,6 +4,12 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include "config.h" /* CONFIG_BOARDDIR */
#ifndef CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_MONITOR_LEN 0x80000
#endif
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
......@@ -76,7 +82,7 @@ SECTIONS
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
. = ADDR(.text) + 0x80000;
. = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
__bss_start = .;
.bss (NOLOAD) :
......
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
浏览文件 @ 080d8975
......@@ -57,6 +57,16 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
#ifdef CONFIG_SPL_SKIP_RELOCATE
. = ALIGN(4);
__bss_start = .;
.bss : {
*(.sbss*)
*(.bss*)
}
. = ALIGN(4);
__bss_end = .;
#endif
/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
......@@ -66,11 +76,16 @@ SECTIONS
} :text = 0xffff
#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
#ifndef BOOT_PAGE_OFFSET
#define BOOT_PAGE_OFFSET 0x1000
#endif
.bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
{
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
}
#ifndef RESET_VECTOR_OFFSET
#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
#endif
#elif defined(CONFIG_FSL_ELBC)
#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
#else
......@@ -81,6 +96,7 @@ SECTIONS
} = 0xffff
#endif
#ifndef CONFIG_SPL_SKIP_RELOCATE
/*
* Make sure that the bss segment isn't linked at 0x0, otherwise its
* address won't be updated during relocation fixups.
......@@ -95,4 +111,5 @@ SECTIONS
}
. = ALIGN(4);
__bss_end = .;
#endif
}
arch/powerpc/cpu/mpc85xx/u-boot.lds
浏览文件 @ 080d8975
......@@ -12,7 +12,12 @@
#define RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifndef CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_MONITOR_LEN 0x80000
#endif
OUTPUT_ARCH(powerpc)
ENTRY(_start_e500)
PHDRS
{
......@@ -84,7 +89,7 @@ SECTIONS
{
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
. = ADDR(.text) + 0x80000;
. = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
#else
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
......
arch/powerpc/cpu/mpc8xxx/law.c
浏览文件 @ 080d8975
......@@ -221,6 +221,32 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
}
#endif /* not SPL */
void disable_non_ddr_laws(void)
{
int i;
int id;
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
u32 lawar = in_be32(LAWAR_ADDR(i));
if (lawar & LAW_EN) {
id = (lawar & ~LAW_EN) >> 20;
switch (id) {
case LAW_TRGT_IF_DDR_1:
case LAW_TRGT_IF_DDR_2:
case LAW_TRGT_IF_DDR_3:
case LAW_TRGT_IF_DDR_4:
case LAW_TRGT_IF_DDR_INTRLV:
case LAW_TRGT_IF_DDR_INTLV_34:
case LAW_TRGT_IF_DDR_INTLV_123:
case LAW_TRGT_IF_DDR_INTLV_1234:
continue;
default:
disable_law(i);
}
}
}
}
void init_laws(void)
{
int i;
......@@ -233,6 +259,23 @@ void init_laws(void)
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \
!defined(CONFIG_E500MC)
/* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
* which is not disabled before transferring the control to uboot.
* Disable the LAW 0 entry here.
*/
disable_law(0);
#endif
#if !defined(CONFIG_SECURE_BOOT)
/*
* if any non DDR LAWs has been created earlier, remove them before
* LAW table is parsed.
*/
disable_non_ddr_laws();
#endif
/*
* Any LAWs that were set up before we booted assume they are meant to
* be around and mark them used.
......@@ -244,15 +287,6 @@ void init_laws(void)
gd->arch.used_laws |= (1 << i);
}
#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
/*
* in SPL boot we've already parsed the law_table and setup those LAWs
* so don't do it again.
*/
return;
#endif
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index == -1)
set_next_law(law_table[i].addr, law_table[i].size,
......
arch/powerpc/include/asm/config_mpc85xx.h
浏览文件 @ 080d8975
......@@ -19,8 +19,8 @@
*/
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
#define FSL_DDR_VER_4_7 47
#define FSL_DDR_VER_5_0 50
#include <fsl_ddrc_version.h>
#define CONFIG_SYS_FSL_DDR_BE
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
......@@ -154,6 +154,7 @@
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
......@@ -401,6 +402,7 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
......@@ -442,6 +444,7 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
......@@ -476,6 +479,7 @@
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
#define CONFIG_SYS_FSL_ERRATUM_A005812
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
......@@ -490,6 +494,7 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
......@@ -527,6 +532,7 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
......@@ -553,6 +559,7 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
......@@ -571,6 +578,7 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
......@@ -668,8 +676,10 @@
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006475
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#ifdef CONFIG_PPC_B4860
......@@ -704,6 +714,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#endif
#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
#define CONFIG_MAX_CPUS 4
#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
......@@ -736,6 +749,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define CONFIG_E6500
......@@ -777,6 +793,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
......@@ -793,10 +810,15 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_SEC_COMPAT 6
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_QEMU_E500)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
#else
#error Processor type not defined for this platform
#endif
......@@ -813,7 +835,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
!defined(CONFIG_SYS_FSL_DDRC_GEN3)
!defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
!defined(CONFIG_SYS_FSL_DDRC_GEN4)
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
......
arch/powerpc/include/asm/fsl_errata.h
浏览文件 @ 080d8975
......@@ -60,4 +60,20 @@ static inline bool has_erratum_a006261(void)
}
#endif
static inline bool has_erratum_a007075(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
case SVR_B4860:
case SVR_B4420:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_P1010:
return IS_SVR_REV(svr, 1, 0);
case SVR_P4080:
return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
}
return false;
}
#endif
arch/powerpc/include/asm/fsl_liodn.h
浏览文件 @ 080d8975
......@@ -99,6 +99,10 @@ extern void fdt_fixup_liodn(void *blob);
SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
#define SET_QE_LIODN(liodn) \
SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
CONFIG_SYS_MPC85xx_QE_OFFSET)
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
CONFIG_SYS_FSL_QMAN_OFFSET, \
......
arch/powerpc/include/asm/fsl_secure_boot.h
浏览文件 @ 080d8975
......@@ -10,10 +10,22 @@
#ifdef CONFIG_SECURE_BOOT
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
#elif defined(CONFIG_BSC9132QDS)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
#else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif
#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
#if defined(CONFIG_B4860QDS) || \
defined(CONFIG_T4240QDS) || \
defined(CONFIG_T2080QDS) || \
defined(CONFIG_T1040QDS) || \
defined(CONFIG_T1040RDB)
#define CONFIG_SYS_CPC_REINIT_F
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
#endif
#endif
#endif
arch/powerpc/include/asm/immap_85xx.h
浏览文件 @ 080d8975
......@@ -1583,6 +1583,12 @@ typedef struct cpc_corenet {
typedef struct ccsr_gur {
u32 porsr1; /* POR status 1 */
u32 porsr2; /* POR status 2 */
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
#endif
u8 res_008[0x20-0x8];
u32 gpporcr1; /* General-purpose POR configuration */
u32 gpporcr2; /* General-purpose POR configuration 2 */
......@@ -1739,6 +1745,8 @@ typedef struct ccsr_gur {
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
......@@ -1889,7 +1897,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
u32 sata2liodnr; /* SATA 2 LIODN */
u32 sata3liodnr; /* SATA 3 LIODN */
u32 sata4liodnr; /* SATA 4 LIODN */
u8 res22[32];
u8 res22[24];
u32 qeliodnr; /* QE LIODN */
u8 res_57c[4];
u32 dma1liodnr; /* DMA 1 LIODN */
u32 dma2liodnr; /* DMA 2 LIODN */
u32 dma3liodnr; /* DMA 3 LIODN */
......@@ -2877,6 +2887,7 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
&& !defined(CONFIG_PPC_B4420)
......@@ -3151,4 +3162,26 @@ struct dcsr_dcfg_regs {
#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
#define CONFIG_SYS_MPC85xx_SCFG \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
/* The supplement configuration unit register */
struct ccsr_scfg {
u32 dpslpcr; /* 0x000 Deep Sleep Control register */
u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
u32 res1[4];
u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
u32 res2;
u32 pixclkcr; /* 0x028 Pixel Clock Control register */
u32 res3[245];
u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
u32 emiiocr; /* 0x404 EMI MDIO Control Register */
u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
u32 res4[60];
u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
};
#endif /*__IMMAP_85xx__*/
arch/powerpc/include/asm/mmu.h
浏览文件 @ 080d8975
......@@ -509,6 +509,14 @@ extern void print_tlbcam(void);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
enum tlb_map_type {
TLB_MAP_RAM,
TLB_MAP_IO,
};
extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
enum tlb_map_type map_type);
extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
......
arch/powerpc/lib/board.c
浏览文件 @ 080d8975
......@@ -343,6 +343,13 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_PRAM
ulong reg;
#endif
#ifdef CONFIG_DEEP_SLEEP
const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
u32 start_addr;
typedef void (*func_t)(void);
func_t kernel_resume;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
......@@ -360,6 +367,15 @@ void board_init_f(ulong bootflag)
if ((*init_fnc_ptr) () != 0)
hang();
#ifdef CONFIG_DEEP_SLEEP
/* Jump to kernel in deep sleep case */
if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
start_addr = in_be32(&scfg->sparecr[1]);
kernel_resume = (func_t)start_addr;
kernel_resume();
}
#endif
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
......
board/freescale/b4860qds/Makefile
浏览文件 @ 080d8975
......@@ -4,9 +4,14 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += b4860qds.o
obj-y += ddr.o
obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
board/freescale/b4860qds/b4_pbi.cfg
浏览文件 @ 080d8975
......@@ -22,6 +22,9 @@
09110024 00100008
09110028 00100008
0911002c 00100008
#slowing down the MDC clock to make it <= 2.5 MHZ
094fc030 00008148
094fd030 00008148
#Flush PBL data
09138000 00000000
091380c0 00000000
board/freescale/b4860qds/ddr.c
浏览文件 @ 080d8975
......@@ -179,6 +179,7 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
......@@ -186,7 +187,9 @@ phys_size_t initdram(int board_type)
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
#else
dram_size = fsl_ddr_sdram_size();
#endif
return dram_size;
}
......
board/freescale/b4860qds/spl.c 0 → 100644
浏览文件 @ 080d8975
/* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <i2c.h>
#include "../common/qixis.h"
#include "b4860qds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch ((sysclk_conf & 0x0C) >> 2) {
case QIXIS_CLK_100:
return 100000000;
case QIXIS_CLK_125:
return 125000000;
case QIXIS_CLK_133:
return 133333333;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch (ddrclk_conf & 0x03) {
case QIXIS_CLK_100:
return 100000000;
case QIXIS_CLK_125:
return 125000000;
case QIXIS_CLK_133:
return 133333333;
}
return 66666666;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, uart_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("" : : : "memory");
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
uart_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
uart_clk / 16 / CONFIG_BAUDRATE);
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
env_relocate();
#else
/* relocate environment function pointers etc. */
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
#endif
i2c_init_all();
puts("\n\n");
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_NAND_BOOT
nand_boot();
#endif
}
board/freescale/b4860qds/tlb.c
浏览文件 @ 080d8975
......@@ -62,6 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for SRIO2.
*/
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
/* *I*G* - SRIO1 */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
......@@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 17, BOOKE_PAGESZ_2G, 1)
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
board/freescale/qemu-ppce500/Makefile 0 → 100644
浏览文件 @ 080d8975
#
# Copyright 2007 Freescale Semiconductor, Inc.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += qemu-ppce500.o
board/freescale/qemu-ppce500/qemu-ppce500.c 0 → 100644
浏览文件 @ 080d8975
/*
* Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/fsl_pci.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <netdev.h>
#include <fdtdec.h>
#include <errno.h>
#include <malloc.h>
DECLARE_GLOBAL_DATA_PTR;
static void *get_fdt_virt(void)
{
return (void *)CONFIG_SYS_TMPVIRT;
}
static uint64_t get_fdt_phys(void)
{
return (uint64_t)(uintptr_t)gd->fdt_blob;
}
static void map_fdt_as(int esel)
{
u32 mas0, mas1, mas2, mas3, mas7;
uint64_t fdt_phys = get_fdt_phys();
unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful;
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
write_tlb(mas0, mas1, mas2, mas3, mas7);
}
uint64_t get_phys_ccsrbar_addr_early(void)
{
void *fdt = get_fdt_virt();
uint64_t r;
/*
* To be able to read the FDT we need to create a temporary TLB
* map for it.
*/
map_fdt_as(10);
r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc"));
disable_tlb(10);
return r;
}
int board_early_init_f(void)
{
return 0;
}
int checkboard(void)
{
return 0;
}
static int pci_map_region(void *fdt, int pci_node, int range_id,
phys_size_t *ppaddr, pci_addr_t *pvaddr,
pci_size_t *psize, ulong *pmap_addr)
{
uint64_t addr;
uint64_t size;
ulong map_addr;
int r;
r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size);
if (r)
return r;
if (ppaddr)
*ppaddr = addr;
if (psize)
*psize = size;
if (!pmap_addr)
return 0;
map_addr = *pmap_addr;
/* Align map_addr */
map_addr += size - 1;
map_addr &= ~(size - 1);
if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
return -1;
/* Map virtual memory for range */
assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
*pmap_addr = map_addr + size;
if (pvaddr)
*pvaddr = map_addr;
return 0;
}
void pci_init_board(void)
{
struct pci_controller *pci_hoses;
void *fdt = get_fdt_virt();
int pci_node = -1;
int pci_num = 0;
int pci_count = 0;
ulong map_addr;
puts("\n");
/* Start MMIO and PIO range maps above RAM */
map_addr = CONFIG_SYS_PCI_MAP_START;
/* Count and allocate PCI buses */
pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
"device_type", "pci", 4);
while (pci_node != -FDT_ERR_NOTFOUND) {
pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
"device_type", "pci", 4);
pci_count++;
}
if (pci_count) {
pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
} else {
printf("PCI: disabled\n\n");
return;
}
/* Spawn PCI buses based on device tree */
pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
"device_type", "pci", 4);
while (pci_node != -FDT_ERR_NOTFOUND) {
struct fsl_pci_info pci_info = { };
const fdt32_t *reg;
int r;
reg = fdt_getprop(fdt, pci_node, "reg", NULL);
pci_info.regs = fdt_translate_address(fdt, pci_node, reg);
/* Map MMIO range */
r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
&pci_info.mem_size, &map_addr);
if (r)
break;
/* Map PIO range */
r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
&pci_info.io_size, &map_addr);
if (r)
break;
/*
* The PCI framework finds virtual addresses for the buses
* through our address map, so tell it the physical addresses.
*/
pci_info.mem_bus = pci_info.mem_phys;
pci_info.io_bus = pci_info.io_phys;
/* Instantiate */
pci_info.pci_num = pci_num + 1;
fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);
printf("PCI: base address %lx\n", pci_info.regs);
fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);
/* Jump to next PCI node */
pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
"device_type", "pci", 4);
pci_num++;
}
puts("\n");
}
int last_stage_init(void)
{
void *fdt = get_fdt_virt();
int len = 0;
const uint64_t *prop;
int chosen;
chosen = fdt_path_offset(fdt, "/chosen");
if (chosen < 0) {
printf("Couldn't find /chosen node in fdt\n");
return -EIO;
}
/* -kernel boot */
prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len);
if (prop && (len >= 8))
setenv_hex("qemu_kernel_addr", *prop);
/* Give the user a variable for the host fdt */
setenv_hex("fdt_addr_r", (ulong)fdt);
return 0;
}
static uint64_t get_linear_ram_size(void)
{
void *fdt = get_fdt_virt();
const void *prop;
int memory;
int len;
memory = fdt_path_offset(fdt, "/memory");
prop = fdt_getprop(fdt, memory, "reg", &len);
if (prop && len >= 16)
return *(uint64_t *)(prop+8);
panic("Couldn't determine RAM size");
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
#endif
void print_laws(void)
{
/* We don't emulate LAWs yet */
}
phys_size_t fixed_sdram(void)
{
return get_linear_ram_size();
}
phys_size_t fsl_ddr_sdram_size(void)
{
return get_linear_ram_size();
}
void init_tlbs(void)
{
phys_size_t ram_size;
/*
* Create a temporary AS=1 map for the fdt
*
* We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
* which was only 4k big. This way we don't have to clear any other maps.
*/
map_fdt_as(0);
/* Fetch RAM size from the fdt */
ram_size = get_linear_ram_size();
/* And remove our fdt map again */
disable_tlb(0);
/* Create an internal map of manually created TLB maps */
init_used_tlb_cams();
/* Create a dynamic AS=0 CCSRBAR mapping */
assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
1024 * 1024, TLB_MAP_IO));
/* Create a RAM map that spans all accessible RAM */
setup_ddr_tlbs(ram_size >> 20);
/* Create a map for the TLB */
assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(),
1024 * 1024, TLB_MAP_RAM));
}
void init_laws(void)
{
/* We don't emulate LAWs yet */
}
static uint32_t get_cpu_freq(void)
{
void *fdt = get_fdt_virt();
int cpus_node = fdt_path_offset(fdt, "/cpus");
int cpu_node = fdt_first_subnode(fdt, cpus_node);
const char *prop = "clock-frequency";
return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
}
void get_sys_info(sys_info_t *sys_info)
{
int freq = get_cpu_freq();
memset(sys_info, 0, sizeof(sys_info_t));
sys_info->freq_systembus = freq;
sys_info->freq_ddrbus = freq;
sys_info->freq_processor[0] = freq;
}
int get_clocks (void)
{
sys_info_t sys_info;
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
gd->arch.lbc_clk = sys_info.freq_ddrbus;
return 0;
}
unsigned long get_tbclk (void)
{
void *fdt = get_fdt_virt();
int cpus_node = fdt_path_offset(fdt, "/cpus");
int cpu_node = fdt_first_subnode(fdt, cpus_node);
const char *prop = "timebase-frequency";
return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
}
/********************************************
* get_bus_freq
* return system bus freq in Hz
*********************************************/
ulong get_bus_freq (ulong dummy)
{
sys_info_t sys_info;
get_sys_info(&sys_info);
return sys_info.freq_systembus;
}
board/freescale/t1040qds/ddr.c
浏览文件 @ 080d8975
/*
* Copyright 2013 Freescale Semiconductor, Inc.
* Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -39,14 +39,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
......@@ -59,13 +55,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
......@@ -81,7 +74,7 @@ found:
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
popts->half_strength_driver_enable = 1;
/*
* Write leveling override
*/
......@@ -97,8 +90,14 @@ found:
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
#ifdef CONFIG_SYS_FSL_DDR4
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
#endif
}
phys_size_t initdram(int board_type)
......
board/freescale/t1040qds/ddr.h
浏览文件 @ 080d8975
/*
* Copyright 2013 Freescale Semiconductor, Inc.
* Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -14,9 +14,6 @@ struct board_specific_parameters {
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
u32 cpo;
u32 write_data_delay;
u32 force_2t;
};
/*
......@@ -28,21 +25,25 @@ struct board_specific_parameters {
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
{2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
{2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
{2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
{1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
{1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
{1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif
{}
};
......
board/freescale/t1040qds/t1040qds.c
浏览文件 @ 080d8975
......@@ -18,6 +18,8 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
#include <asm/mpc85xx_gpio.h>
#include "../common/qixis.h"
#include "t1040qds.h"
......@@ -89,6 +91,30 @@ int select_i2c_ch_pca9547(u8 ch)
return 0;
}
static void qe_board_setup(void)
{
u8 brdcfg15, brdcfg9;
if (hwconfig("qe") && hwconfig("tdm")) {
brdcfg15 = QIXIS_READ(brdcfg[15]);
/*
* TDMRiser uses QE-TDM
* Route QE_TDM signals to TDM Riser slot
*/
QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
} else if (hwconfig("qe") && hwconfig("uart")) {
brdcfg15 = QIXIS_READ(brdcfg[15]);
brdcfg9 = QIXIS_READ(brdcfg[9]);
/*
* Route QE_TDM signals to UCC
* ProfiBus controlled by UCC3
*/
brdcfg15 &= 0xfc;
QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
}
}
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
......@@ -196,6 +222,8 @@ int misc_init_r(void)
}
}
qe_board_setup();
return 0;
}
......@@ -245,3 +273,14 @@ int board_need_mem_reset(void)
{
return 1;
}
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* does not provide HW signals for power management */
QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
board/freescale/t104xrdb/Makefile
浏览文件 @ 080d8975
......@@ -4,10 +4,14 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += t104xrdb.o
obj-y += ddr.o
obj-y += cpld.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
board/freescale/t104xrdb/README
浏览文件 @ 080d8975
......@@ -198,3 +198,76 @@ The below commands apply to the board
2.To change from vbank4 to vbank0
=> qixis reset (it will boot using vbank0)
NAND boot with 2 Stage boot loader
----------------------------------
PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
SPL further initialise DDR using SPD and environment variables and copy
u-boot(768 KB) from flash to DDR.
Finally SPL transer control to u-boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework during boot :-
-----------------------------------------------
Area | Address |
-----------------------------------------------
Secure boot | 0xFFFC0000 (32KB) |
headers | |
-----------------------------------------------
GD, BD | 0xFFFC8000 (4KB) |
-----------------------------------------------
ENV | 0xFFFC9000 (8KB) |
-----------------------------------------------
HEAP | 0xFFFCB000 (30KB) |
-----------------------------------------------
STACK | 0xFFFD8000 (22KB) |
-----------------------------------------------
U-boot SPL | 0xFFFD8000 (160KB) |
-----------------------------------------------
NAND Flash memory Map on T104xRDB
------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot 1MB
0x180000 0x19FFFF u-boot env 128KB
0x280000 0x29FFFF FMAN Ucode 128KB
0x380000 0x39FFFF QE Firmware 128KB
SD Card memory Map on T104xRDB
------------------------------------------
Block #blocks Definition Size
0x008 2048 u-boot 1MB
0x800 0024 u-boot env 8KB
0x820 0256 FMAN Ucode 128KB
0x920 0256 QE Firmware 128KB
SPI Flash memory Map on T104xRDB
------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot 1MB
0x100000 0x101FFF u-boot env 8KB
0x110000 0x12FFFF FMAN Ucode 128KB
0x130000 0x14FFFF QE Firmware 128KB
Please note QE Firmware is only valid for T1040RDB
Switch Settings: (ON is 0, OFF is 1)
===============
NAND boot SW setting:
SW1: 10001000
SW2: 00111001
SW3: 11110001
SPI boot SW setting:
SW1: 00100010
SW2: 10111001
SW3: 11100001
SD boot SW setting:
SW1: 00100000
SW2: 00111001
SW3: 11100001
board/freescale/t104xrdb/cpld.c 0 → 100644
浏览文件 @ 080d8975
/**
* Copyright 2014 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*
* This file provides support for the board-specific CPLD used on some Freescale
* reference boards.
*
* The following macros need to be defined:
*
* CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include "cpld.h"
u8 cpld_read(unsigned int reg)
{
void *p = (void *)CONFIG_SYS_CPLD_BASE;
return in_8(p + reg);
}
void cpld_write(unsigned int reg, u8 value)
{
void *p = (void *)CONFIG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
/**
* Set the boot bank to the alternate bank
*/
void cpld_set_altbank(void)
{
u8 reg = CPLD_READ(flash_ctl_status);
reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
CPLD_WRITE(flash_ctl_status, reg);
CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
}
/**
* Set the boot bank to the default bank
*/
void cpld_set_defbank(void)
{
u8 reg = CPLD_READ(flash_ctl_status);
reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
CPLD_WRITE(flash_ctl_status, reg);
CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
}
#ifdef DEBUG
static void cpld_dump_regs(void)
{
printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
printf("int_status = 0x%02x\n", CPLD_READ(int_status));
printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
putc('\n');
}
#endif
int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
if (argc <= 1)
return cmd_usage(cmdtp);
if (strcmp(argv[1], "reset") == 0) {
if (strcmp(argv[2], "altbank") == 0)
cpld_set_altbank();
else
cpld_set_defbank();
#ifdef DEBUG
} else if (strcmp(argv[1], "dump") == 0) {
cpld_dump_regs();
#endif
} else
rc = cmd_usage(cmdtp);
return rc;
}
U_BOOT_CMD(
cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
"Reset the board or alternate bank",
"reset - hard reset to default bank\n"
"cpld reset altbank - reset to alternate bank\n"
#ifdef DEBUG
"cpld dump - display the CPLD registers\n"
#endif
);
board/freescale/t104xrdb/cpld.h 0 → 100644
浏览文件 @ 080d8975
/**
* Copyright 2013 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*
* This file provides support for the ngPIXIS, a board-specific FPGA used on
* some Freescale reference boards.
*/
/*
* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
*/
struct cpld_data {
u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
u8 hw_ver; /* 0x02 - Hardware Revision Register */
u8 sw_ver; /* 0x03 - Software Revision register */
u8 res0[12]; /* 0x04 - 0x0F - not used */
u8 reset_ctl1; /* 0x10 - Reset control Register1 */
u8 reset_ctl2; /* 0x11 - Reset control Register2 */
u8 int_status; /* 0x12 - Interrupt status Register */
u8 flash_ctl_status; /* 0x13 - Flash control and status register */
u8 fan_ctl_status; /* 0x14 - Fan control and status register */
u8 led_ctl_status; /* 0x15 - LED control and status register */
u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
u8 boot_override; /* 0x18 - Boot override register */
u8 boot_config1; /* 0x19 - Boot config override register*/
u8 boot_config2; /* 0x1A - Boot config override register*/
} cpld_data_t;
/* Pointer to the CPLD register set */
u8 cpld_read(unsigned int reg);
void cpld_write(unsigned int reg, u8 value);
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
#define CPLD_WRITE(reg, value)\
cpld_write(offsetof(struct cpld_data, reg), value)
board/freescale/t104xrdb/ddr.c
浏览文件 @ 080d8975
......@@ -113,6 +113,7 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
......@@ -120,6 +121,8 @@ phys_size_t initdram(int board_type)
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
#else
dram_size = fsl_ddr_sdram_size();
#endif
return dram_size;
}
board/freescale/t104xrdb/eth.c
浏览文件 @ 080d8975
......@@ -41,6 +41,7 @@ int board_eth_init(bd_t *bis)
/* T1040RDB only supports SGMII on DTSEC3 */
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
#endif
case PHY_INTERFACE_MODE_RGMII:
if (FM1_DTSEC4 == i)
......
board/freescale/t104xrdb/spl.c 0 → 100644
浏览文件 @ 080d8975
/* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, uart_clk;
#ifdef CONFIG_SPL_NAND_BOOT
u32 porsr1, pinctl;
#endif
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#ifdef CONFIG_SPL_NAND_BOOT
/*
* There is T1040 SoC issue where NOR, FPGA are inaccessible during
* NAND boot because IFC signals > IFC_AD7 are not enabled.
* This workaround changes RCW source to make all signals enabled.
*/
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
#endif
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("" : : : "memory");
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
uart_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
uart_clk / 16 / CONFIG_BAUDRATE);
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
i2c_init_all();
puts("\n\n");
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}
board/freescale/t104xrdb/t1040_rcw.cfg 0 → 100644
浏览文件 @ 080d8975
#PBL preamble and RCW header
aa55aa55 010e0100
# serdes protocol 0x66
0c18000e 0e000000 00000000 00000000
66000002 80000002 e8106000 01000000
00000000 00000000 00000000 00032810
00000000 0342500f 00000000 00000000
board/freescale/t104xrdb/t1042_rcw.cfg 0 → 100644
浏览文件 @ 080d8975
#PBL preamble and RCW header
aa55aa55 010e0100
# serdes protocol 0x66
0c18000e 0e000000 00000000 00000000
06000002 00400002 e8106000 01000000
00000000 00000000 00000000 00030810
00000000 01fe0a06 00000000 00000000
board/freescale/t104xrdb/t104x_pbi.cfg 0 → 100644
浏览文件 @ 080d8975
#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
#Configure CPC1 as 256KB SRAM
09010100 00000000
09010104 fffc0007
09010f00 08000000
09010000 80000000
#Configure LAW for CPC1
09000cd0 00000000
09000cd4 fffc0000
09000cd8 81000011
#Configure alternate space
09000010 00000000
09000014 ff000000
09000018 81000000
#Configure SPI controller
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#Flush PBL data
091380c0 000FFFFF
board/freescale/t104xrdb/t104xrdb.c
浏览文件 @ 080d8975
......@@ -17,16 +17,30 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <asm/mpc85xx_gpio.h>
#include "t104xrdb.h"
#include "cpld.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
u8 sw;
printf("Board: %sRDB\n", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
sw = CPLD_READ(flash_ctl_status);
sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
if (sw <= 7)
printf("vBank: %d\n", sw);
else
printf("Unsupported Bank=%x\n", sw);
return 0;
}
......@@ -91,3 +105,12 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
#endif
}
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
board/freescale/t104xrdb/tlb.c
浏览文件 @ 080d8975
......@@ -53,6 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -82,6 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -102,6 +104,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
board/freescale/t208xqds/Makefile
浏览文件 @ 080d8975
......@@ -4,11 +4,16 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_T2080QDS) += t208xqds.o
obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
obj-$(CONFIG_T2081QDS) += t208xqds.o
obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
board/freescale/t208xqds/ddr.c
浏览文件 @ 080d8975
......@@ -107,13 +107,16 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
puts(" DDR: ");
return dram_size;
}
board/freescale/t208xqds/spl.c 0 → 100644
浏览文件 @ 080d8975
/* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
#include "../common/qixis.h"
#include "t208xqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT)
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_SPI_BOOT)
puts("\nSPI boot...\n");
#elif defined(CONFIG_SPL_NAND_BOOT)
puts("\nNAND boot...\n");
#endif
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
i2c_init_all();
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}
board/freescale/t208xqds/tlb.c
浏览文件 @ 080d8975
......@@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCIe 1, 0x80000000 */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -141,6 +143,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
board/freescale/t208xrdb/Makefile
浏览文件 @ 080d8975
......@@ -4,10 +4,15 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_T2080RDB) += t208xrdb.o
obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
obj-$(CONFIG_T2080RDB) += cpld.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
board/freescale/t208xrdb/README
浏览文件 @ 080d8975
......@@ -67,7 +67,7 @@ T2080PCIe-RDB board Overview
- One PCIe x2 end-point device (C293 Crypto co-processor)
- IFC/Local Bus
- NOR: 128MB 16-bit NOR Flash
- NAND: 512MB 8-bit NAND flash
- NAND: 1GB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
- SATA
- Two SATA 2.0 onnectors on-board
......@@ -120,7 +120,7 @@ Start Address End Address Definition Max size
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
......@@ -146,7 +146,8 @@ Software configurations and board settings
------------------------------------------
1. NOR boot:
a. build NOR boot image
$ make T2080RDB
$ make T2080RDB_config
$ make
b. program u-boot.bin image to NOR flash
=> tftp 1000000 u-boot.bin
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
......@@ -155,18 +156,18 @@ Software configurations and board settings
Switching between default bank and alternate bank on NOR flash
To change boot source to vbank4:
via software: run command 'cpld reset altbank' in u-boot.
via DIP-switch: set SW3[5:7] = '011'
via DIP-switch: set SW3[5:7] = '100'
To change boot source to vbank0:
via software: run command 'cpld reset' in u-boot.
via DIP-Switch: set SW3[5:7] = '111'
via DIP-Switch: set SW3[5:7] = '000'
2. NAND Boot:
a. build PBL image for NAND boot
$ make T2080RDB_NAND_config
$ make u-boot.pbl
b. program u-boot.pbl to NAND flash
=> tftp 1000000 u-boot.pbl
$ make
b. program u-boot-with-spl-pbl.bin to NAND flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> nand erase 0 d0000
=> nand write 1000000 0 $filesize
set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
......@@ -174,9 +175,9 @@ Software configurations and board settings
3. SPI Boot:
a. build PBL image for SPI boot
$ make T2080RDB_SPIFLASH_config
$ make u-boot.pbl
b. program u-boot.pbl to SPI flash
=> tftp 1000000 u-boot.pbl
$ make
b. program u-boot-with-spl-pbl.bin to SPI flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> sf probe 0
=> sf erase 0 d0000
=> sf write 1000000 0 $filesize
......@@ -185,13 +186,68 @@ Software configurations and board settings
4. SD Boot:
a. build PBL image for SD boot
$ make T2080RDB_SDCARD_config
$ make u-boot.pbl
b. program u-boot.pbl to TF card
=> tftp 1000000 u-boot.pbl
=> mmc write 1000000 8 1650
$ make
b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> mmc write 1000000 8 0x800
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
2-stage NAND/SPI/SD boot loader
-------------------------------
PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
SPL further initializes DDR using SPD and environment variables
and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
Finally SPL transers control to u-boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework
-------------------------------------------------
|Area | Address |
-------------------------------------------------
|SecureBoot header | 0xFFFC0000 (32KB) |
-------------------------------------------------
|GD, BD | 0xFFFC8000 (4KB) |
-------------------------------------------------
|ENV | 0xFFFC9000 (8KB) |
-------------------------------------------------
|HEAP | 0xFFFCB000 (50KB) |
-------------------------------------------------
|STACK | 0xFFFD8000 (22KB) |
-------------------------------------------------
|U-boot SPL | 0xFFFD8000 (160KB) |
-------------------------------------------------
NAND Flash memory Map on T2080RDB
--------------------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
0x100000 0x17FFFF u-boot env 512KB (1 block)
0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
0x200000 0x27FFFF CS4315 ucode 512KB (1 block)
Micro SD Card memory Map on T2080RDB
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 u-boot img 1MB
0x800 0016 u-boot env 8KB
0x820 0128 FMAN ucode 64KB
0x8a0 0512 CS4315 ucode 256KB
SPI Flash memory Map on T2080RDB
----------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot img 1MB
0x100000 0x101FFF u-boot env 8KB
0x110000 0x11FFFF FMAN ucode 64KB
0x120000 0x15FFFF CS4315 ucode 256KB
How to update the ucode of Cortina CS4315/CS4340 10G PHY
--------------------------------------------------------
=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
......
board/freescale/t208xrdb/cpld.h
浏览文件 @ 080d8975
......@@ -35,8 +35,8 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_LBMAP_MASK 0x3F
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_OVERRIDE 0x40
#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */
#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */
#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
board/freescale/t208xrdb/ddr.c
浏览文件 @ 080d8975
......@@ -100,13 +100,15 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
return dram_size;
}
board/freescale/t208xrdb/spl.c 0 → 100644
浏览文件 @ 080d8975
/* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT)
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_SPI_BOOT)
puts("\nSPI boot...\n");
#elif defined(CONFIG_SPL_NAND_BOOT)
puts("\nNAND boot...\n");
#endif
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
i2c_init_all();
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}
board/freescale/t208xrdb/t208xrdb.c
浏览文件 @ 080d8975
......@@ -44,7 +44,7 @@ int checkboard(void)
puts("NAND\n");
} else {
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
printf("NOR vBank%d\n", ~reg & 0x7);
printf("NOR vBank%d\n", reg);
}
#endif
......
board/freescale/t208xrdb/tlb.c
浏览文件 @ 080d8975
......@@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCIe 1, 0x80000000 */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -140,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 19, BOOKE_PAGESZ_2G, 1)
......
board/freescale/t4qds/Makefile
浏览文件 @ 080d8975
......@@ -4,10 +4,14 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_T4240QDS) += t4240qds.o
obj-$(CONFIG_T4240EMU) += t4240emu.o
obj-y += ddr.o
obj-$(CONFIG_T4240QDS)+= eth.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
board/freescale/t4qds/ddr.c
浏览文件 @ 080d8975
......@@ -117,11 +117,15 @@ phys_size_t initdram(int board_type)
puts("Initializing....using SPD\n");
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
return dram_size;
}
board/freescale/t4qds/spl.c 0 → 100644
浏览文件 @ 080d8975
/* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include "../common/qixis.h"
#include "t4240qds_qixis.h"
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#ifdef CONFIG_SPL_NAND_BOOT
u32 porsr1, pinctl;
#endif
#ifdef CONFIG_SPL_NAND_BOOT
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
#endif
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("" : : : "memory");
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#ifdef CONFIG_SPL_MMC_BOOT
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_NAND_BOOT)
puts("\nNAND boot...\n");
#endif
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
i2c_init_all();
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}
board/freescale/t4qds/t4_pbi.cfg
浏览文件 @ 080d8975
......@@ -13,20 +13,6 @@
09000d00 00000000
09000d04 fff80000
09000d08 81000012
#workaround for IFC bus speed
091241c0 f03f3f3f
091241c4 ff003f3f
09124010 00000101
09124130 0000000c
#workaround for SERDES A-006031
090ea000 064740e6
090ea020 064740e6
090eb000 064740e6
090eb020 064740e6
090ec000 064740e6
090ec020 064740e6
090ed000 064740e6
090ed020 064740e6
#Configure alternate space
09000010 00000000
09000014 ff000000
......
board/freescale/t4qds/t4_rcw.cfg
浏览文件 @ 080d8975
#PBL preamble and RCW header
aa55aa55 010e0100
#serdes protocol 1_28_6_12
120c0019 0c101915 00000000 00000000
04383063 30548c00 6c020000 1d000000
16070019 18101916 00000000 00000000
04383060 30548c00 ec020000 f5000000
00000000 ee0000ee 00000000 000307fc
00000000 00000000 00000000 00000020
00000000 00000000 00000000 00000028
board/freescale/t4qds/tlb.c
浏览文件 @ 080d8975
......@@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -105,6 +105,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......@@ -136,6 +137,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
boards.cfg
浏览文件 @ 080d8975
此差异已折叠。
common/ddr_spd.c
浏览文件 @ 080d8975
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
......@@ -116,3 +116,46 @@ ddr3_spd_check(const ddr3_spd_eeprom_t *spd)
return 1;
}
}
unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd)
{
char *p = (char *)spd;
int csum16;
int len;
char crc_lsb; /* byte 126 */
char crc_msb; /* byte 127 */
len = 126;
csum16 = crc16(p, len);
crc_lsb = (char) (csum16 & 0xff);
crc_msb = (char) (csum16 >> 8);
if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb) {
printf("SPD checksum unexpected.\n"
"Checksum lsb in SPD = %02X, computed SPD = %02X\n"
"Checksum msb in SPD = %02X, computed SPD = %02X\n",
spd->crc[0], crc_lsb, spd->crc[1], crc_msb);
return 1;
}
p = (char *)((ulong)spd + 128);
len = 126;
csum16 = crc16(p, len);
crc_lsb = (char) (csum16 & 0xff);
crc_msb = (char) (csum16 >> 8);
if (spd->mod_section.uc[126] != crc_lsb ||
spd->mod_section.uc[127] != crc_msb) {
printf("SPD checksum unexpected.\n"
"Checksum lsb in SPD = %02X, computed SPD = %02X\n"
"Checksum msb in SPD = %02X, computed SPD = %02X\n",
spd->mod_section.uc[126],
crc_lsb, spd->mod_section.uc[127],
crc_msb);
return 1;
}
return 0;
}
common/fdt_support.c
浏览文件 @ 080d8975
......@@ -49,6 +49,37 @@ static void write_cell(u8 *addr, u64 val, int size)
}
}
/**
* fdt_getprop_u32_default_node - Return a node's property or a default
*
* @fdt: ptr to device tree
* @off: offset of node
* @cell: cell offset in property
* @prop: property name
* @dflt: default value if the property isn't found
*
* Convenience function to return a node's property or a default value if
* the property doesn't exist.
*/
u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
const char *prop, const u32 dflt)
{
const fdt32_t *val;
int len;
val = fdt_getprop(fdt, off, prop, &len);
/* Check if property exists */
if (!val)
return dflt;
/* Check if property is long enough */
if (len < ((cell + 1) * sizeof(uint32_t)))
return dflt;
return fdt32_to_cpu(*val);
}
/**
* fdt_getprop_u32_default - Find a node and return it's property or a default
*
......@@ -63,18 +94,13 @@ static void write_cell(u8 *addr, u64 val, int size)
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
const char *prop, const u32 dflt)
{
const fdt32_t *val;
int off;
off = fdt_path_offset(fdt, path);
if (off < 0)
return dflt;
val = fdt_getprop(fdt, off, prop, NULL);
if (val)
return fdt32_to_cpu(*val);
else
return dflt;
return fdt_getprop_u32_default_node(fdt, off, 0, prop, dflt);
}
/**
......@@ -1409,3 +1435,97 @@ u64 fdt_get_base_address(void *fdt, int node)
return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0;
}
/*
* Read a property of size <prop_len>. Currently only supports 1 or 2 cells.
*/
static int fdt_read_prop(const fdt32_t *prop, int prop_len, int cell_off,
uint64_t *val, int cells)
{
const fdt32_t *prop32 = &prop[cell_off];
const fdt64_t *prop64 = (const fdt64_t *)&prop[cell_off];
if ((cell_off + cells) > prop_len)
return -FDT_ERR_NOSPACE;
switch (cells) {
case 1:
*val = fdt32_to_cpu(*prop32);
break;
case 2:
*val = fdt64_to_cpu(*prop64);
break;
default:
return -FDT_ERR_NOSPACE;
}
return 0;
}
/**
* fdt_read_range - Read a node's n'th range property
*
* @fdt: ptr to device tree
* @node: offset of node
* @n: range index
* @child_addr: pointer to storage for the "child address" field
* @addr: pointer to storage for the CPU view translated physical start
* @len: pointer to storage for the range length
*
* Convenience function that reads and interprets a specific range out of
* a number of the "ranges" property array.
*/
int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
uint64_t *addr, uint64_t *len)
{
int pnode = fdt_parent_offset(fdt, node);
const fdt32_t *ranges;
int pacells;
int acells;
int scells;
int ranges_len;
int cell = 0;
int r = 0;
/*
* The "ranges" property is an array of
* { <child address> <parent address> <size in child address space> }
*
* All 3 elements can span a diffent number of cells. Fetch their size.
*/
pacells = fdt_getprop_u32_default_node(fdt, pnode, 0, "#address-cells", 1);
acells = fdt_getprop_u32_default_node(fdt, node, 0, "#address-cells", 1);
scells = fdt_getprop_u32_default_node(fdt, node, 0, "#size-cells", 1);
/* Now try to get the ranges property */
ranges = fdt_getprop(fdt, node, "ranges", &ranges_len);
if (!ranges)
return -FDT_ERR_NOTFOUND;
ranges_len /= sizeof(uint32_t);
/* Jump to the n'th entry */
cell = n * (pacells + acells + scells);
/* Read <child address> */
if (child_addr) {
r = fdt_read_prop(ranges, ranges_len, cell, child_addr,
acells);
if (r)
return r;
}
cell += acells;
/* Read <parent address> */
if (addr)
*addr = fdt_translate_address(fdt, node, ranges + cell);
cell += pacells;
/* Read <size in child address space> */
if (len) {
r = fdt_read_prop(ranges, ranges_len, cell, len, scells);
if (r)
return r;
}
return 0;
}
doc/README.b4860qds
浏览文件 @ 080d8975
......@@ -328,3 +328,39 @@ The below commands apply to both B4860QDS and B4420QDS.
On Linux the interfaces are renamed as:
. eth2 -> fm1-gb2
. eth3 -> fm1-gb3
NAND boot with 2 Stage boot loader
----------------------------------
PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
SPL further initialise DDR using SPD and environment variables and copy
u-boot(768 KB) from flash to DDR.
Finally SPL transer control to u-boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework during boot :-
-----------------------------------------------
Area | Address |
-----------------------------------------------
Secure boot | 0xFFFC0000 (32KB) |
headers | |
-----------------------------------------------
GD, BD | 0xFFFC8000 (4KB) |
-----------------------------------------------
ENV | 0xFFFC9000 (8KB) |
-----------------------------------------------
HEAP | 0xFFFCB000 (30KB) |
-----------------------------------------------
STACK | 0xFFFD8000 (22KB) |
-----------------------------------------------
U-boot SPL | 0xFFFD8000 (160KB) |
-----------------------------------------------
NAND Flash memory Map on B4860 and B4420QDS
------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot 1MB
0x140000 0x15FFFF u-boot env 128KB
0x1A0000 0x1BFFFF FMAN Ucode 128KB
doc/README.t4240qds
浏览文件 @ 080d8975
......@@ -120,3 +120,56 @@ The override voltage takes effect when booting.
Note: voltage adjustment needs to be done step by step. Changing voltage too
rapidly may cause current surge. The voltage stepping is done by software.
Users can set the final voltage directly.
2-stage NAND/SD boot loader
-------------------------------
PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
SPL further initialise DDR using SPD and environment variables
and copy u-boot(768 KB) from NAND/SD device to DDR.
Finally SPL transers control to u-boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework
-------------------------------------------------
|Area | Address |
-------------------------------------------------
|SecureBoot header | 0xFFFC0000 (32KB) |
-------------------------------------------------
|GD, BD | 0xFFFC8000 (4KB) |
-------------------------------------------------
|ENV | 0xFFFC9000 (8KB) |
-------------------------------------------------
|HEAP | 0xFFFCB000 (50KB) |
-------------------------------------------------
|STACK | 0xFFFD8000 (22KB) |
-------------------------------------------------
|U-boot SPL | 0xFFFD8000 (160KB) |
-------------------------------------------------
NAND Flash memory Map on T4QDS
--------------------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot img 1MB
0x140000 0x15FFFF u-boot env 128KB
0x160000 0x17FFFF FMAN Ucode 128KB
Micro SD Card memory Map on T4QDS
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 u-boot img 1MB
0x800 0016 u-boot env 8KB
0x820 0128 FMAN ucode 64KB
Switch Settings: (ON is 1, OFF is 0)
===============
NAND boot SW setting:
SW1[1:8] = 10000010
SW2[1.1] = 0
SW6[1:4] = 1001
SD boot SW setting:
SW1[1:8] = 00100000
SW2[1.1] = 0
drivers/ddr/fsl/Makefile
浏览文件 @ 080d8975
#
# Copyright 2008-2011 Freescale Semiconductor, Inc.
# Copyright 2008-2014 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# Version 2 as published by the Free Software Foundation.
#
obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR4) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
ifdef CONFIG_DDR_SPD
SPD := y
endif
......@@ -24,6 +25,7 @@ ifdef SPD
obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR4) += ddr4_dimm_params.o
endif
obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
......@@ -32,3 +34,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
drivers/ddr/fsl/ctrl_regs.c
浏览文件 @ 080d8975
此差异已折叠。
drivers/ddr/fsl/ddr4_dimm_params.c 0 → 100644
浏览文件 @ 080d8975
此差异已折叠。
drivers/ddr/fsl/fsl_ddr_gen4.c 0 → 100644
浏览文件 @ 080d8975
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <fsl_ddr.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
/*
* regs has the to-be-set values for DDR controller registers
* ctrl_num is the DDR controller number
* step: 0 goes through the initialization in one pass
* 1 sets registers and returns before enabling controller
* 2 resumes from step 1 and continues to initialize
* Dividing the initialization to two steps to deassert DDR reset signal
* to comply with JEDEC specs for RDIMMs.
*/
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i, bus_width;
struct ccsr_ddr __iomem *ddr;
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
#endif
default:
printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
return;
}
if (step == 2)
goto step2;
if (regs->ddr_eor)
ddr_out32(&ddr->eor, regs->ddr_eor);
ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i == 0) {
ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
ddr_out32(&ddr->cs0_config, regs->cs[i].config);
ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
} else if (i == 1) {
ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
ddr_out32(&ddr->cs1_config, regs->cs[i].config);
ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
} else if (i == 2) {
ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
ddr_out32(&ddr->cs2_config, regs->cs[i].config);
ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
} else if (i == 3) {
ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
ddr_out32(&ddr->cs3_config, regs->cs[i].config);
ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
}
}
ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
#ifndef CONFIG_SYS_FSL_DDR_EMU
/*
* Skip these two registers if running on emulator
* because emulator doesn't have skew between bytes.
*/
if (regs->ddr_wrlvl_cntl_2)
ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
if (regs->ddr_wrlvl_cntl_3)
ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
#endif
ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
ddr_out32(&ddr->err_disable, regs->err_disable);
ddr_out32(&ddr->err_int_en, regs->err_int_en);
for (i = 0; i < 32; i++) {
if (regs->debug[i]) {
debug("Write to debug_%d as %08x\n",
i+1, regs->debug[i]);
ddr_out32(&ddr->debug[i], regs->debug[i]);
}
}
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
* deasserted. Clocks start when any chip select is enabled and clock
* control register is set. Because all DDR components are connected to
* one reset signal, this needs to be done in two steps. Step 1 is to
* get the clocks started. Step 2 resumes after reset signal is
* deasserted.
*/
if (step == 1) {
udelay(200);
return;
}
step2:
/* Set, but do not enable the memory */
temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
/*
* 500 painful micro-seconds must elapse between
* the DDR clock setup and the DDR config enable.
* DDR2 need 200 us, and DDR3 need 500 us from spec,
* we choose the max, that is 500 us for all of case.
*/
udelay(500);
asm volatile("sync;isync");
/* Let the controller go */
temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (!(regs->cs[i].config & 0x80000000))
continue;
total_gb_size_per_controller += 1 << (
((regs->cs[i].config >> 14) & 0x3) + 2 +
((regs->cs[i].config >> 8) & 0x7) + 12 +
((regs->cs[i].config >> 4) & 0x3) + 0 +
((regs->cs[i].config >> 0) & 0x7) + 8 +
3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
26); /* minus 26 (count of 64M) */
}
if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
total_gb_size_per_controller *= 3;
else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
total_gb_size_per_controller <<= 1;
/*
* total memory / bus width = transactions needed
* transactions needed / data rate = seconds
* to add plenty of buffer, double the time
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
* Let's wait for 800ms
*/
bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
(get_ddr_freq(0) >> 20)) << 2;
total_gb_size_per_controller >>= 4; /* shift down to gb size */
debug("total %d GB\n", total_gb_size_per_controller);
debug("Need to wait up to %d * 10ms\n", timeout);
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
(timeout >= 0)) {
udelay(10000); /* throttle polling rate */
timeout--;
}
if (timeout <= 0)
printf("Waiting for D_INIT timeout. Memory may not work.\n");
}
drivers/ddr/fsl/interactive.c
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drivers/ddr/fsl/main.c
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drivers/ddr/fsl/mpc85xx_ddr_gen3.c
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drivers/ddr/fsl/options.c
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drivers/ddr/fsl/util.c
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drivers/misc/fsl_ifc.c
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......@@ -162,3 +162,10 @@ void init_early_memctl_regs(void)
set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
#endif
}
void init_final_memctl_regs(void)
{
#ifdef CONFIG_SYS_CSPR0_FINAL
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
#endif
}
drivers/mmc/fsl_esdhc_spl.c
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drivers/mtd/nand/fsl_ifc_spl.c
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......@@ -88,11 +88,7 @@ static inline int bad_block(uchar *marker, int port_size)
return __raw_readw((u16 *)marker) != 0xffff;
}
#ifdef CONFIG_TPL_BUILD
int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
#else
static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
......@@ -217,15 +213,6 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
return 0;
}
/*
* Defines a static function nand_load_image() here, because non-static makes
* the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
*/
#ifndef CONFIG_TPL_BUILD
#define nand_spl_load_image(offs, uboot_size, vdst) \
nand_load(offs, uboot_size, vdst)
#endif
/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
......
drivers/mtd/spi/fsl_espi_spl.c
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drivers/net/fm/fm.c
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drivers/net/fm/memac_phy.c
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drivers/net/phy/atheros.c
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drivers/net/phy/vitesse.c
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drivers/qe/qe.c
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drivers/qe/qe.h
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drivers/usb/host/ehci-fsl.c
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include/common_timing_params.h
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include/configs/B4860QDS.h
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include/configs/BSC9131RDB.h
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include/configs/BSC9132QDS.h
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include/configs/C29XPCIE.h
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include/configs/MPC8536DS.h
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include/configs/MPC8569MDS.h
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include/configs/P1010RDB.h
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include/configs/P1022DS.h
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include/configs/P1023RDB.h
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include/configs/P1023RDS.h
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include/configs/P1_P2_RDB.h
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include/configs/P2020DS.h
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include/configs/P2041RDB.h
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include/configs/T1040QDS.h
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include/configs/T1040RDB.h 已删除 100644 → 0
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include/configs/T208xQDS.h
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include/configs/T208xRDB.h
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include/configs/T4240EMU.h
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include/configs/T4240QDS.h
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include/configs/corenet_ds.h
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include/configs/km/km8309-common.h
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include/configs/km/kmp204x-common.h
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include/configs/p1_p2_rdb_pc.h
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include/configs/p1_twr.h
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include/configs/qemu-ppce500.h 0 → 100644
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include/configs/t4qds.h
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include/ddr_spd.h
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include/e500.h
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include/fdt_support.h
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include/fsl_ddr.h
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include/fsl_ddr_dimm_params.h
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include/fsl_ddr_sdram.h
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include/fsl_ddrc_version.h 0 → 100644
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include/fsl_esdhc.h
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include/fsl_ifc.h
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include/fsl_immap.h
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include/fsl_usb.h
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include/spi_flash.h
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include/usb/ehci-fsl.h
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