- Enable SGMII support for 0x8d Serdes 2 protocol.
    - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol.
    - Updated debug statement
    - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1)
    - Rename onboard PHY address defines for more readability
    - Add these new Defines in B4860QDS.h file
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NSuresh Gupta <suresh.gupta@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>