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    mips: cache: Bulletproof the code against cornercases · fbb0de08
    Marek Vasut 提交于
    This patch makes sure that the flush/invalidate_dcache_range() functions
    can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
    This call is valid and is happily produced by USB EHCI code for example.
    The expected behavior of the cache function(s) in this case is that they
    will do no operation, since the size is zero.
    
    The current implementation though has a problem where such invocation will
    result in a hard CPU hang. This is because under such conditions, where the
    start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
    will then try to iterate over the entire address space, which in itself is
    wrong. But iterating over the entire address space might also hit some odd
    address which will cause bus hang. The later happens on the Atheros MIPS.
    Signed-off-by: NMarek Vasut <marex@denx.de>
    Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
    Cc: Hans de Goede <hdegoede@redhat.com>
    fbb0de08
cache.c 2.7 KB