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    armv7r: K3: Allow SPL to run only on core 0 · ccdb7c22
    Lokesh Vutla 提交于
    Based on the MCU R5 efuse settings, R5F cores in MCU domain
    either work in split mode or in lock step mode.
    
    If efuse settings are in lockstep mode: ROM release R5 cores
    and SPL continues to run on the R5 core is lockstep mode.
    
    If efuse settings are in split mode: ROM releases both the R5
    cores simultaneously and allow SPL to run on both the cores.
    In this case it is bootloader's responsibility to detect core
    1 and park it. Else both the core will be running bootloader
    independently which might result in an unexpected behaviour.
    Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
    Reviewed-by: NTom Rini <trini@konsulko.com>
    ccdb7c22
lowlevel_init.S 351 字节