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由 Anup Patel 提交于
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: NPaul Walmsley <paul.walmsley@sifive.com> Signed-off-by: NAtish Patra <atish.patra@wdc.com> Signed-off-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NAlexander Graf <agraf@suse.de>
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