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由 Emil Medve 提交于
* Make the U-Boot update command sequence conditional. Helps prevent accidental erasing if an upload or previous step fails * Make it easier to update other FLASH banks * Enable DDR controller cache line interleaving and bank cs0/cs1 by default Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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