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    arm64: mvebu: Add L3 cache flush functionality to A8K family · b58385df
    Konstantin Porotchkin 提交于
    Add missing L3 cache flush functionality which absence prevents
    Linux kernel from normal boot in case the L3 cache is enabled
    by ATF.
    The L3 cache is named the "last level" cache in order to keep
    the terminology similar to the ATF code.
    This cache should not be disabled by u-boot since the Linux
    kernel cannot activate it, so it is activates at ATF stage.
    However the cache flush is required for preventing data corruption
    after disabling the MMU and the data cache before passing control
    to the loaded Linux image.
    Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
    Cc: Stefan Roese <sr@denx.de>
    Cc: Nadav Haklai <nadavh@marvell.com>
    Cc: Neta Zur Hershkovits <neta@marvell.com>
    Cc: Omri Itach <omrii@marvell.com>
    Cc: Igal Liberman <igall@marvell.com>
    Cc: Haim Boot <hayim@marvell.com>
    Cc: Hanna Hawa <hannah@marvell.com>
    Signed-off-by: NStefan Roese <sr@denx.de>
    b58385df
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