RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NRick Chen <rick@andestech.com>