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    clk: sunxi: add and use dummy gate clocks · d6cb09d8
    Andre Przywara 提交于
    Some devices enumerate various clocks in their DT, and many drivers
    just blanketly try to enable all of them. This creates problems
    since we only model a few gate clocks, and the clock driver outputs
    a warning when a clock is not described:
    =========
    sunxi_set_gate: (CLK#3) unhandled
    =========
    
    Some clocks don't have an enable bit, or are already enabled in a
    different way, so we might want to just ignore them.
    
    Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
    a GATE_DUMMY macro that can be used in the clock description array.
    Define a few clocks, used by some pinctrl devices, that way to suppress
    the runtime warnings.
    Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
    Reviewed-by: NSamuel Holland <samuel@sholland.org>
    d6cb09d8
clk_h6.c 3.2 KB