We need to align the cache buffer to ARCH_DMA_MINALIGN in order to avoid
access errors like

CACHE: Misaligned operation at range [be0231e0, be0235e0]

seen on the MCIMX7SABRE.

Fixes: d5aee659 ("fs: ext4: cache extent data")
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NPeter Robinson <pbrobinson@gmail.com>