In GMII mode (which operates at 3.3V) both SICRH TSEC1/2 output buffer
impedance bits should be clear, i.e., SICRH[TSIOB1] = 0 and SICRH[TSIOB2] = 0.
SICRH[TSIOB1] was erroneously being set high.

U-Boot always operated this PHY interface in GMII mode.  It is assumed this
was missed in the clean up by the original board porters, and copied along
to the TQM and sbc boards.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Acked-by: NIra Snyder <iws@ovro.caltech.edu>
Reviewed-by: NDavid Hawkins <dwh@ovro.caltech.edu>
Tested-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
CC: Dave Liu <DaveLiu@freescale.com>