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由 Sergei Ianovich 提交于
Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS. If SDRAM is not reset, it causes memory bus congestion and the device hangs. We put SDRAM in selfresh mode before watchdog reset, removing potential freezes. Signed-off-by: NSergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
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