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由 Yangbo Lu 提交于
The SDHC clock divider value for LS1028A should be default 2, not 1. Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
181c65b8
The SDHC clock divider value for LS1028A should be default 2,
not 1.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>