serial_sh.c 4.6 KB
Newer Older
1 2 3
/*
 * SuperH SCIF device driver.
 * Copyright (c) 2007 Nobuhiro Iwamatsu
4
 *
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <common.h>
#include <asm/processor.h>

#ifdef CFG_SCIF_CONSOLE

#if defined (CONFIG_CONS_SCIF0)
#define SCIF_BASE	SCIF0_BASE
#elif defined (CONFIG_CONS_SCIF1)
#define SCIF_BASE	SCIF1_BASE
#else
#error "Default SCIF doesn't set....."
#endif

33 34 35 36 37 38 39 40 41 42 43
#if defined(CONFIG_SH3)
/* There are SH7720's register */
#define SCSMR	(volatile unsigned short *)(SCIF_BASE + 0x0)
#define SCBRR	(volatile unsigned char  *)(SCIF_BASE + 0x4)
#define SCSCR	(volatile unsigned short *)(SCIF_BASE + 0x8)
#define SCFSR	(volatile unsigned short *)(SCIF_BASE + 0x14)   /* SCSSR */
#define SCFCR	(volatile unsigned short *)(SCIF_BASE + 0x18)
#define SCFDR	(volatile unsigned short *)(SCIF_BASE + 0x1C)
#define SCFTDR	(volatile unsigned char  *)(SCIF_BASE + 0x20)
#define SCFRDR	(volatile unsigned char  *)(SCIF_BASE + 0x24)
#else
N
Nobuhiro Iwamatsu 已提交
44
#define SCSMR 	(vu_short *)(SCIF_BASE + 0x0)
45
#define SCBRR 	(vu_char  *)(SCIF_BASE + 0x4)
N
Nobuhiro Iwamatsu 已提交
46 47 48 49 50 51
#define SCSCR 	(vu_short *)(SCIF_BASE + 0x8)
#define SCFTDR 	(vu_char  *)(SCIF_BASE + 0xC)
#define SCFSR 	(vu_short *)(SCIF_BASE + 0x10)
#define SCFRDR 	(vu_char  *)(SCIF_BASE + 0x14)
#define SCFCR 	(vu_short *)(SCIF_BASE + 0x18)
#define SCFDR 	(vu_short *)(SCIF_BASE + 0x1C)
52 53
#endif

54
#if defined(CONFIG_SH4A)
N
Nobuhiro Iwamatsu 已提交
55 56 57 58
#define SCRFDR	(vu_short *)(SCIF_BASE + 0x20)
#define SCSPTR	(vu_short *)(SCIF_BASE + 0x24)
#define SCLSR   (vu_short *)(SCIF_BASE + 0x28)
#define SCRER	(vu_short *)(SCIF_BASE + 0x2C)
59
#define LSR_ORER	1
60
#elif defined (CONFIG_SH4)
N
Nobuhiro Iwamatsu 已提交
61 62
#define SCSPTR 	(vu_short *)(SCIF_BASE + 0x20)
#define SCLSR 	(vu_short *)(SCIF_BASE + 0x24)
63
#define LSR_ORER	1
64
#elif defined (CONFIG_SH3)
65 66
#define SCLSR	SCFSR	/* SCSSR */
#define LSR_ORER	0x0200
67 68 69
#endif

#define SCR_RE 		(1 << 4)
70
#define SCR_TE 		(1 << 5)
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
#define FCR_RFRST	(1 << 1) /* RFCL */
#define FCR_TFRST	(1 << 2) /* TFCL */
#define FSR_DR   	(1 << 0)
#define FSR_RDF  	(1 << 1)
#define FSR_FER  	(1 << 3)
#define FSR_BRK  	(1 << 4)
#define FSR_FER  	(1 << 3)
#define FSR_TEND 	(1 << 6)
#define FSR_ER   	(1 << 7)

/*----------------------------------------------------------------------*/

void serial_setbrg (void)
{
	DECLARE_GLOBAL_DATA_PTR;
86 87 88 89 90 91 92

#if defined(CONFIG_CPU_SH7720)
	int divisor = gd->baudrate * 16;

	*SCBRR = (CONFIG_SYS_CLK_FREQ * 2 + (divisor / 2)) /
						(gd->baudrate * 32) - 1;
#else
93 94
	int divisor = gd->baudrate * 32;

95
	*SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) /
96
						(gd->baudrate * 32) - 1;
97
#endif
98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
}

int serial_init (void)
{
	*SCSCR = (SCR_RE | SCR_TE);
	*SCSMR = 0 ;
	*SCSMR = 0;
	*SCFCR = (FCR_RFRST | FCR_TFRST);
	*SCFCR;
	*SCFCR = 0;

	serial_setbrg();
	return 0;
}

static int serial_tx_fifo_level (void)
{
	return (*SCFDR >> 8) & 0x1F;
}

static int serial_rx_fifo_level (void)
{
	return (*SCFDR >> 0) & 0x1F;
}

void serial_raw_putc (const char c)
{
	unsigned int fsr_bits_to_clear;

	while (1) {
		if (*SCFSR & FSR_TEND) {		/* Tx fifo is empty */
			fsr_bits_to_clear = FSR_TEND;
			break;
		}
	}

	*SCFTDR = c;
	if (fsr_bits_to_clear != 0)
		*SCFSR &= ~fsr_bits_to_clear;
}

void serial_putc (const char c)
{
	if (c == '\n')
		serial_raw_putc ('\r');
	serial_raw_putc (c);
}

void serial_puts (const char *s)
{
	char c;
	while ((c = *s++) != 0)
		serial_putc (c);
}

int serial_tstc (void)
{
	return serial_rx_fifo_level() ? 1 : 0;
}

#define FSR_ERR_CLEAR   0x0063
#define RDRF_CLEAR      0x00fc
void handle_error( void ){

	(void)*SCFSR ;
	*SCFSR = FSR_ERR_CLEAR ;
	(void)*SCLSR ;
	*SCLSR = 0x00 ;
}

int serial_getc_check( void ){
	unsigned short status;

	status = *SCFSR ;

	if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
		handle_error();
	if( *SCLSR & LSR_ORER )
		handle_error();
	return (status & ( FSR_DR | FSR_RDF ));
}

int serial_getc (void)
{
	unsigned short status ;
	char ch;
	while(!serial_getc_check());

	ch = *SCFRDR;
	status =  *SCFSR ;

	*SCFSR = RDRF_CLEAR ;

	if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
		handle_error();

	if( *SCLSR & LSR_ORER )
		handle_error();

	return ch ;
}

#endif	/* CFG_SCIF_CONSOLE */