提交 1306c08a 编写于 作者: R Rajendra Nayak 提交者: Tony Lindgren

ARM: OMAP4+: Remove static iotable mappings for SRAM

In order to handle errata I688, a page of sram was reserved by doing a
static iotable map. Now that we use gen_pool to manage sram, we can
completely remove all of these static mappings and use gen_pool_alloc()
to get the one page of sram space needed to implement errata I688.
omap_bus_sync will be NOP until SRAM initialization happens.
Suggested-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
上级 8b9a2810
......@@ -10,6 +10,9 @@ Required properties:
Should be "ti,omap5-mpu" for OMAP5
- ti,hwmods: "mpu"
Optional properties:
- sram: Phandle to the ocmcram node
Examples:
- For an OMAP5 SMP system:
......
......@@ -81,6 +81,7 @@
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
sram = <&ocmcram>;
};
dsp {
......
......@@ -104,8 +104,9 @@
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap5-mpu";
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
sram = <&ocmcram>;
};
};
......
......@@ -231,15 +231,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
.length = L4_PER_44XX_SIZE,
.type = MT_DEVICE,
},
#ifdef CONFIG_OMAP4_ERRATA_I688
{
.virtual = OMAP4_SRAM_VA,
.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
.length = PAGE_SIZE,
.type = MT_MEMORY_RW_SO,
},
#endif
};
#endif
......@@ -269,14 +260,6 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
.length = L4_PER_54XX_SIZE,
.type = MT_DEVICE,
},
#ifdef CONFIG_OMAP4_ERRATA_I688
{
.virtual = OMAP4_SRAM_VA,
.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
.length = PAGE_SIZE,
.type = MT_MEMORY_RW_SO,
},
#endif
};
#endif
......
......@@ -25,6 +25,7 @@
#include <linux/irqchip/irq-crossbar.h>
#include <linux/of_address.h>
#include <linux/reboot.h>
#include <linux/genalloc.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
......@@ -71,6 +72,26 @@ void omap_bus_sync(void)
}
EXPORT_SYMBOL(omap_bus_sync);
static int __init omap4_sram_init(void)
{
struct device_node *np;
struct gen_pool *sram_pool;
np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
if (!np)
pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
__func__);
sram_pool = of_get_named_gen_pool(np, "sram", 0);
if (!sram_pool)
pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
__func__);
else
sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
return 0;
}
omap_arch_initcall(omap4_sram_init);
/* Steal one page physical memory for barrier implementation */
int __init omap_barrier_reserve_memblock(void)
{
......@@ -91,7 +112,6 @@ void __init omap_barriers_init(void)
dram_io_desc[0].type = MT_MEMORY_RW_SO;
iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
dram_sync = (void __iomem *) dram_io_desc[0].virtual;
sram_sync = (void __iomem *) OMAP4_SRAM_VA;
pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
(long long) paddr, dram_io_desc[0].virtual);
......
......@@ -124,12 +124,6 @@ static void __init omap2_map_sram(void)
{
int cached = 1;
#ifdef CONFIG_OMAP4_ERRATA_I688
if (cpu_is_omap44xx()) {
omap_sram_start += PAGE_SIZE;
omap_sram_size -= SZ_16K;
}
#endif
if (cpu_is_omap34xx()) {
/*
* SRAM must be marked as non-cached on OMAP3 since the
......
......@@ -74,9 +74,3 @@ static inline void omap_push_sram_idle(void) {}
*/
#define OMAP2_SRAM_PA 0x40200000
#define OMAP3_SRAM_PA 0x40200000
#ifdef CONFIG_OMAP4_ERRATA_I688
#define OMAP4_SRAM_PA 0x40304000
#define OMAP4_SRAM_VA 0xfe404000
#else
#define OMAP4_SRAM_PA 0x40300000
#endif
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