提交 f198cc43 编写于 作者: A Andy Polyakov

SPARC assembly pack: enforce V8+ ABI constraints.

Even though it's hard to imagine, it turned out that upper half of
arguments passed to V8+ subroutine can be non-zero.

["n" pseudo-instructions, such as srln being srl in 32-bit case and
srlx in 64-bit one, were implemented in binutils 2.10. It's assumed
that Solaris assembler implemented it around same time, i.e. 2000.]
Reviewed-by: NRichard Levitte <levitte@openssl.org>
上级 0685b15a
...@@ -106,7 +106,7 @@ $code.=<<___; ...@@ -106,7 +106,7 @@ $code.=<<___;
des_t4_cbc_encrypt: des_t4_cbc_encrypt:
cmp $len, 0 cmp $len, 0
be,pn $::size_t_cc, .Lcbc_abort be,pn $::size_t_cc, .Lcbc_abort
nop srln $len, 0, $len ! needed on v8+, "nop" on v9
ld [$ivec + 0], %f0 ! load ivec ld [$ivec + 0], %f0 ! load ivec
ld [$ivec + 4], %f1 ld [$ivec + 4], %f1
...@@ -207,7 +207,7 @@ des_t4_cbc_encrypt: ...@@ -207,7 +207,7 @@ des_t4_cbc_encrypt:
des_t4_cbc_decrypt: des_t4_cbc_decrypt:
cmp $len, 0 cmp $len, 0
be,pn $::size_t_cc, .Lcbc_abort be,pn $::size_t_cc, .Lcbc_abort
nop srln $len, 0, $len ! needed on v8+, "nop" on v9
ld [$ivec + 0], %f2 ! load ivec ld [$ivec + 0], %f2 ! load ivec
ld [$ivec + 4], %f3 ld [$ivec + 4], %f3
...@@ -315,7 +315,7 @@ $code.=<<___; ...@@ -315,7 +315,7 @@ $code.=<<___;
des_t4_ede3_cbc_encrypt: des_t4_ede3_cbc_encrypt:
cmp $len, 0 cmp $len, 0
be,pn $::size_t_cc, .Lcbc_abort be,pn $::size_t_cc, .Lcbc_abort
nop srln $len, 0, $len ! needed on v8+, "nop" on v9
ld [$ivec + 0], %f0 ! load ivec ld [$ivec + 0], %f0 ! load ivec
ld [$ivec + 4], %f1 ld [$ivec + 4], %f1
...@@ -467,7 +467,7 @@ des_t4_ede3_cbc_encrypt: ...@@ -467,7 +467,7 @@ des_t4_ede3_cbc_encrypt:
des_t4_ede3_cbc_decrypt: des_t4_ede3_cbc_decrypt:
cmp $len, 0 cmp $len, 0
be,pn $::size_t_cc, .Lcbc_abort be,pn $::size_t_cc, .Lcbc_abort
nop srln $len, 0, $len ! needed on v8+, "nop" on v9
ld [$ivec + 0], %f2 ! load ivec ld [$ivec + 0], %f2 ! load ivec
ld [$ivec + 4], %f3 ld [$ivec + 4], %f3
......
...@@ -453,6 +453,8 @@ gcm_gmult_vis3: ...@@ -453,6 +453,8 @@ gcm_gmult_vis3:
.align 32 .align 32
gcm_ghash_vis3: gcm_ghash_vis3:
save %sp,-$frame,%sp save %sp,-$frame,%sp
nop
srln $len,0,$len ! needed on v8+, "nop" on v9
ldx [$Xip+8],$C2 ! load Xi ldx [$Xip+8],$C2 ! load Xi
ldx [$Xip+0],$C3 ldx [$Xip+0],$C3
......
...@@ -48,6 +48,7 @@ ${alg}${bits}_t4_cbc_encrypt: ...@@ -48,6 +48,7 @@ ${alg}${bits}_t4_cbc_encrypt:
save %sp, -$::frame, %sp save %sp, -$::frame, %sp
cmp $len, 0 cmp $len, 0
be,pn $::size_t_cc, .L${bits}_cbc_enc_abort be,pn $::size_t_cc, .L${bits}_cbc_enc_abort
srln $len, 0, $len ! needed on v8+, "nop" on v9
sub $inp, $out, $blk_init ! $inp!=$out sub $inp, $out, $blk_init ! $inp!=$out
___ ___
$::code.=<<___ if (!$::evp); $::code.=<<___ if (!$::evp);
...@@ -265,6 +266,7 @@ ${alg}${bits}_t4_cbc_decrypt: ...@@ -265,6 +266,7 @@ ${alg}${bits}_t4_cbc_decrypt:
save %sp, -$::frame, %sp save %sp, -$::frame, %sp
cmp $len, 0 cmp $len, 0
be,pn $::size_t_cc, .L${bits}_cbc_dec_abort be,pn $::size_t_cc, .L${bits}_cbc_dec_abort
srln $len, 0, $len ! needed on v8+, "nop" on v9
sub $inp, $out, $blk_init ! $inp!=$out sub $inp, $out, $blk_init ! $inp!=$out
___ ___
$::code.=<<___ if (!$::evp); $::code.=<<___ if (!$::evp);
...@@ -624,6 +626,7 @@ $::code.=<<___; ...@@ -624,6 +626,7 @@ $::code.=<<___;
.align 32 .align 32
${alg}${bits}_t4_ctr32_encrypt: ${alg}${bits}_t4_ctr32_encrypt:
save %sp, -$::frame, %sp save %sp, -$::frame, %sp
srln $len, 0, $len ! needed on v8+, "nop" on v9
prefetch [$inp], 20 prefetch [$inp], 20
prefetch [$inp + 63], 20 prefetch [$inp + 63], 20
...@@ -927,6 +930,7 @@ $::code.=<<___; ...@@ -927,6 +930,7 @@ $::code.=<<___;
.align 32 .align 32
${alg}${bits}_t4_xts_${dir}crypt: ${alg}${bits}_t4_xts_${dir}crypt:
save %sp, -$::frame-16, %sp save %sp, -$::frame-16, %sp
srln $len, 0, $len ! needed on v8+, "nop" on v9
mov $ivec, %o0 mov $ivec, %o0
add %fp, $::bias-16, %o1 add %fp, $::bias-16, %o1
......
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