add nofpu subarchs to the sh arch, and properly detect compiler's fpu config

arch/sh/bits/fenv.h

+#ifndef __SH_FPU_ANY__
+
+#define FE_ALL_EXCEPT 0
+#define FE_TONEAREST  0
+
+#else
+
 #define FE_TONEAREST  0
 #define FE_TOWARDZERO 1
 
@@ -8,6 +15,8 @@
 #define FE_INVALID    0x40
 #define FE_ALL_EXCEPT 0x7c
 
+#endif
+
 typedef unsigned long fexcept_t;
 
 typedef struct {

configure

@@ -421,8 +421,24 @@ fi
 test "$ARCH" = "microblaze" && trycppif __MICROBLAZEEL__ "$t" \
 && SUBARCH=${SUBARCH}el
 
-test "$ARCH" = "sh" && trycppif __BIG_ENDIAN__ "$t" \
-&& SUBARCH=${SUBARCH}eb
+if test "$ARCH" = "sh" ; then
+trycppif __BIG_ENDIAN__ "$t" && SUBARCH=${SUBARCH}eb
+if trycppif __SH_FPU_ANY__ ; then
+# Some sh configurations are broken and replace double with float
+# rather than using softfloat when the fpu is present but only
+# supports single precision. Reject them.
+printf "checking whether compiler's double type is IEEE double... "
+echo 'typedef char dblcheck[(int)sizeof(double)-5];' >> "$tmpc"
+if $CC $CFLAGS_C99FSE $CPPFLAGS $CFLAGS -c -o /dev/null "$tmpc" >/dev/null 2>&1 ; then
+printf "yes\n"
+else
+printf "no\n"
+fail "$0: error: compiler's floating point configuration is unsupported"
+fi
+else
+SUBARCH=${SUBARCH}-nofpu
+fi
+fi
 
 test "$SUBARCH" \
 && printf "configured for %s variant: %s\n" "$ARCH" "$ARCH$SUBARCH"

src/fenv/sh-nofpu/fenv.sub

+../fenv.c

src/fenv/sheb-nofpu/fenv.sub

+../fenv.c

src/setjmp/sh-nofpu/longjmp.s

+.global _longjmp
+.global longjmp
+.type   _longjmp, @function
+.type   longjmp,  @function
+_longjmp:
+longjmp:
+	mov.l  @r4+, r8
+	mov.l  @r4+, r9
+	mov.l  @r4+, r10
+	mov.l  @r4+, r11
+	mov.l  @r4+, r12
+	mov.l  @r4+, r13
+	mov.l  @r4+, r14
+	mov.l  @r4+, r15
+	lds.l  @r4+, pr
+
+	tst  r5, r5
+	movt r0
+	add  r5, r0
+
+	rts
+	 nop

src/setjmp/sh-nofpu/longjmp.sub

+longjmp.s

src/setjmp/sh-nofpu/setjmp.s

+.global __setjmp
+.global _setjmp
+.global setjmp
+.type   __setjmp, @function
+.type   _setjmp,  @function
+.type   setjmp,   @function
+__setjmp:
+_setjmp:
+setjmp:
+	add   #36, r4
+	sts.l  pr,   @-r4
+	mov.l  r15   @-r4
+	mov.l  r14,  @-r4
+	mov.l  r13,  @-r4
+	mov.l  r12,  @-r4
+	mov.l  r11,  @-r4
+	mov.l  r10,  @-r4
+	mov.l  r9,   @-r4
+	mov.l  r8,   @-r4
+	rts
+	 mov  #0, r0

src/setjmp/sh-nofpu/setjmp.sub

+setjmp.s

src/setjmp/sheb-nofpu/longjmp.sub

+../sh-nofpu/longjmp.s

src/setjmp/sheb-nofpu/setjmp.sub

+../sh-nofpu/setjmp.s