Description: support original vector base address

Reviewed-by: shenwei

kernel/arch/arm/cortex-m3/keil/los_interrupt.c

@@ -355,6 +355,7 @@ VOID HalExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
  **************************************************************************** */
 LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 {
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;
     g_hwiForm[0] = 0;             /* [0] Top of Stack */
     g_hwiForm[1] = Reset_Handler; /* [1] reset */
@@ -372,6 +373,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 
     /* Interrupt vector table location */
     SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
 #if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
     NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
 #endif

kernel/arch/arm/cortex-m3/keil/los_timer.c

@@ -59,10 +59,12 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalTickStart(OS_TICK_HANDLER *handler)
         return LOS_ERRNO_TICK_CFG_INVALID;
     }
 
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
 #if (OS_HWI_WITH_ARG == 1)
     OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
 #else
     OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+#endif
 #endif
 
     g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;

kernel/arch/arm/cortex-m4/iar/los_interrupt.c

@@ -34,6 +34,7 @@
 #include <stdarg.h>
 #include "los_debug.h"
 #include "los_task.h"
+#include "los_tick.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -355,6 +356,7 @@ VOID HalExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
  **************************************************************************** */
 LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 {
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;
     g_hwiForm[0] = 0;             /* [0] Top of Stack */
     g_hwiForm[1] = Reset_Handler; /* [1] reset */
@@ -372,6 +374,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 
     /* Interrupt vector table location */
     SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
 #if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
     NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
 #endif

kernel/arch/arm/cortex-m4/iar/los_timer.c

@@ -58,12 +58,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalTickStart(OS_TICK_HANDLER *handler)
         return LOS_ERRNO_TICK_CFG_INVALID;
     }
 
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
 #if (OS_HWI_WITH_ARG == 1)
     OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
 #else
     OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
 #endif
-
+#endif
     g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
     g_ullTickCount = 0;
 

kernel/arch/arm/cortex-m7/gcc/los_interrupt.c

@@ -350,6 +350,7 @@ VOID HalExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
  **************************************************************************** */
 LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 {
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;
     g_hwiForm[0] = 0;             /* [0] Top of Stack */
     g_hwiForm[1] = Reset_Handler; /* [1] reset */
@@ -368,6 +369,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 
     /* Interrupt vector table location */
     SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
 #if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
     NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
 #endif

kernel/arch/arm/cortex-m7/gcc/los_timer.c

@@ -58,10 +58,12 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalTickStart(OS_TICK_HANDLER *handler)
         return LOS_ERRNO_TICK_CFG_INVALID;
     }
 
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
 #if (OS_HWI_WITH_ARG == 1)
     OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
 #else
     OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+#endif
 #endif
 
     g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;

kernel/include/los_config.h

@@ -114,6 +114,23 @@ extern "C" {
 #define LOSCFG_PLATFORM_HWI                                 1
 #endif
 
+/**
+ * @ingroup los_config
+ * Configuration item for using system defined vector base address and interrupt handlers.
+ * If LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT is set to 0, vector base address will not be
+ * modified by system. In arm, it should be noted that PendSV_Handler and SysTick_Handler will
+ * be redefined in this case because system depends these interrupt handlers to run normally.
+ */
+#ifndef LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT
+#define LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT                 1
+#endif
+
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    #if (LOSCFG_PLATFORM_HWI == 0)
+        #error "if LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT is set to 1, then LOSCFG_PLATFORM_HWI must also be set to 1"
+    #endif
+#endif
+
 /**
  * @ingroup los_config
  * Maximum number of used hardware interrupts, including Tick timer interrupts.
@@ -326,7 +343,7 @@ extern "C" {
 
 #if (LOSCFG_BASE_CORE_SWTMR_ALIGN == 1)
     #if (LOSCFG_BASE_CORE_SWTMR == 0)
-        #error "if LOSCFG_BASE_CORE_SWTMR_ALIGN is set to 1, then LOSCFG_BASE_CORE_SWTMR must alse be set to 1"
+        #error "if LOSCFG_BASE_CORE_SWTMR_ALIGN is set to 1, then LOSCFG_BASE_CORE_SWTMR must also be set to 1"
     #endif
 #endif
 
@@ -356,7 +373,7 @@ extern "C" {
 
 #if (LOSCFG_BASE_CORE_SWTMR == 1)
     #if (LOSCFG_BASE_IPC_QUEUE == 0)
-        #error "if LOSCFG_BASE_CORE_SWTMR is set to 1, then LOSCFG_BASE_IPC_QUEUE must alse be set to 1"
+        #error "if LOSCFG_BASE_CORE_SWTMR is set to 1, then LOSCFG_BASE_IPC_QUEUE must also be set to 1"
     #endif
 #endif
 /* =============================================================================

targets/cortex-m4_stm32f429ig_fire-challenger_iar/board/iar_stm32f429ig_fire-challenger.c

@@ -26,3 +26,15 @@ void USART_Config(void)
 
   STM_EVAL_COMInit(COM1, &USART_InitStructure);
 }
+
+extern void OsTickHandler(void);
+void SysTick_Handler(void)
+{
+    OsTickHandler();
+}
+
+extern void HalPendSV(void);
+void PendSV_Handler(void)
+{
+    HalPendSV();
+}

targets/cortex-m4_stm32f429ig_fire-challenger_iar/target_config.h

@@ -37,6 +37,7 @@
 #define _TARGET_CONFIG_H
 
 #include "stm32f4xx.h"
+#include "stm32f4xx_it.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -54,6 +55,7 @@ extern "C" {
                                         Hardware interrupt module configuration
 =============================================================================*/
 #define LOSCFG_PLATFORM_HWI                                 1
+#define LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT                 0
 #define LOSCFG_PLATFORM_HWI_LIMIT                           128
 /*=============================================================================
                                        Task module configuration