* Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
* Cortex-M exception types: The task handler exits.
*/
#define OS_EXC_CAUSE_TASK_EXIT 18
/**
* @ingroup los_exc
* Cortex-M exception types: A fatal error.
*/
#define OS_EXC_CAUSE_FATAL_ERR 19
/**
* @ingroup los_exc
* Cortex-M exception types: Hard Fault caused by a debug event.
*/
#define OS_EXC_CAUSE_DEBUGEVT 20
/**
* @ingroup los_exc
* Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
*/
#define OS_EXC_CAUSE_VECTBL 21
/**
* @ingroup los_exc
* Exception information structure
*
* Description: Exception information saved when an exception is triggered on the Cortex-M33 platform.
*
*/
typedefstructTagExcInfo{
/**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
UINT16phase;
/**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
UINT16type;
/**< If the exact address access error indicates the wrong access address when the exception occurred */
UINT32faultAddr;
/**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
UINT32thrdPid;
/**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
UINT16nestCnt;
/**< reserve */
UINT16reserved;
/**< Hardware context at the time an exception to the automatic stack floating-point register occurs */