1. 11 5月, 2010 37 次提交
  2. 07 5月, 2010 1 次提交
  3. 06 5月, 2010 2 次提交
    • M
      microblaze: Defconfig update · 65134121
      Michal Simek 提交于
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      65134121
    • M
      microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros · 3274c570
      Michal Simek 提交于
      1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
      2. Change BUG_ON to WARN_ON
      3. Remove end aligned from CACHE_LOOP_LIMITS.
      C implementation do not need aligned end address and ASM code do aligned
      in their macros
      4. ASM optimized  CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address.
      Because end address is compound from start + size, end address is the first address
      which is exclude.
      
      Here is the corresponding code which describe it.
      +       int align = ~(line_length - 1);
      +       end = ((end & align) == end) ? end - line_length : end & align;
      
      a) end is aligned:
      it is necessary to subtruct line length because we don't want to work with
      next cacheline
      b) end address is not aligned:
      Just align it to be ready for ASM code.
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      3274c570