- 29 6月, 2017 7 次提交
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由 Maciej W. Rozycki 提交于
Reduce the log level for branch emulation error messages issued before sending SIGILL by `__compute_return_epc_for_insn' as these are triggered by user software and are not an event that would normally require any attention. The same signal sent from elsewhere does not actually leave any trace in the kernel log at all. Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16402/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
This is a user-visible message, so we want it to be spelled correctly. Fixes: 5f9f41c4 ("MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6") Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # 3.19+ Patchwork: https://patchwork.linux-mips.org/patch/16400/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Fix: * commit 8467ca01 ("MIPS: Emulate the new MIPS R6 branch compact (BC) instruction"), * commit 84fef630 ("MIPS: Emulate the new MIPS R6 BALC instruction"), * commit 69b9a2fd ("MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions"), * commit 28d6f93d ("MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions"), * commit c893ce38 ("MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions") and send SIGILL rather than returning -SIGILL for R6 branch and jump instructions. Returning -SIGILL is never correct as the API defines this function's result upon error to be -EFAULT and a signal actually issued. Fixes: 8467ca01 ("MIPS: Emulate the new MIPS R6 branch compact (BC) instruction") Fixes: 84fef630 ("MIPS: Emulate the new MIPS R6 BALC instruction") Fixes: 69b9a2fd ("MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions") Fixes: 28d6f93d ("MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions") Fixes: c893ce38 ("MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions") Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # 3.19+ Patchwork: https://patchwork.linux-mips.org/patch/16399/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Fix commit 319824ea ("MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6") and also send SIGILL rather than returning -SIGILL for BLTZAL, BLTZALL, BGEZAL and BGEZALL instruction encodings no longer supported in R6, except where emulated. Returning -SIGILL is never correct as the API defines this function's result upon error to be -EFAULT and a signal actually issued. Fixes: 319824ea ("MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6") Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # 3.19+ Patchwork: https://patchwork.linux-mips.org/patch/16398/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Use the more accurate `sigill_r2r6' name for the label used in the case of sending SIGILL in the absence of the instruction emulator for an earlier ISA level instruction that has been removed as from the R6 ISA, so that the `sigill_r6' name is freed for the situation where an R6 instruction is not supposed to be interpreted, because the executing processor does not support the R6 ISA. Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # 3.19+ Patchwork: https://patchwork.linux-mips.org/patch/16397/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Fix commit e50c0a8f ("Support the MIPS32 / MIPS64 DSP ASE.") and send SIGILL rather than SIGBUS whenever an unimplemented BPOSGE32 DSP ASE instruction has been encountered in `__compute_return_epc_for_insn' as our Reserved Instruction exception handler would in response to an attempt to actually execute the instruction. Sending SIGBUS only makes sense for the unaligned PC case, since moved to `__compute_return_epc'. Adjust function documentation accordingly, correct formatting and use `pr_info' rather than `printk' as the other exit path already does. Fixes: e50c0a8f ("Support the MIPS32 / MIPS64 DSP ASE.") Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # 2.6.14+ Patchwork: https://patchwork.linux-mips.org/patch/16396/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Complement commit fb6883e5 ("MIPS: microMIPS: Support handling of delay slots.") and actually decode the regular MIPS JALX major instruction opcode, the handling of which has been added with the said commit for EPC calculation in `__compute_return_epc_for_insn'. Fixes: fb6883e5 ("MIPS: microMIPS: Support handling of delay slots.") Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # 3.9+ Patchwork: https://patchwork.linux-mips.org/patch/16394/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 15 6月, 2017 1 次提交
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由 Paul Burton 提交于
The code handling the pop76 opcode (ie. bnezc & jialc instructions) in __compute_return_epc_for_insn() needs to set the value of $31 in the jialc case, which is encoded with rs = 0. However its check to differentiate bnezc (rs != 0) from jialc (rs = 0) was unfortunately backwards, meaning that if we emulate a bnezc instruction we clobber $31 & if we emulate a jialc instruction it actually behaves like a jic instruction. Fix this by inverting the check of rs to match the way the instructions are actually encoded. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Fixes: 28d6f93d ("MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions") Cc: stable <stable@vger.kernel.org> # v4.0+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16178/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 02 3月, 2017 1 次提交
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由 Ingo Molnar 提交于
We are going to split <linux/sched/signal.h> out of <linux/sched.h>, which will have to be picked up from other headers and a couple of .c files. Create a trivial placeholder <linux/sched/signal.h> file that just maps to <linux/sched.h> to make this patch obviously correct and bisectable. Include the new header in the files that are going to need it. Acked-by: NLinus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: NIngo Molnar <mingo@kernel.org>
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- 25 12月, 2016 1 次提交
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由 Linus Torvalds 提交于
This was entirely automated, using the script by Al: PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*<asm/uaccess.h>' sed -i -e "s!$PATT!#include <linux/uaccess.h>!" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h) to do the replacement at the end of the merge window. Requested-by: NAl Viro <viro@zeniv.linux.org.uk> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 06 10月, 2016 1 次提交
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由 Marcin Nowakowski 提交于
Current instruction decoder for uprobe/kprobe handler only handles branches with delay slots. For compact branches the behaviour is rather unpredictable - and depending on the encoding of a compact branch instruction may result in one (or more) of: - executing an instruction that follows a branch which wasn't in a delay slot and shouldn't have been executed - incorrectly emulating a branch leading to a jump to a wrong location - unexpected branching out of the single-stepped code and never reaching the breakpoint that should terminate the probe handler Results of these actions are generally unpredictable, but can end up with a probed application or kernel crash, so disable placing probes on compact branches until they are handled properly. Signed-off-by: NMarcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14336/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 05 10月, 2016 1 次提交
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由 Paul Gortmaker 提交于
Historically a lot of these existed because we did not have a distinction between what was modular code and what was providing support to modules via EXPORT_SYMBOL and friends. That changed when we forked out support for the latter into the export.h file. This means we should be able to reduce the usage of module.h in code that is obj-y Makefile or bool Kconfig. The advantage in doing so is that module.h itself sources about 15 other headers; adding significantly to what we feed cpp, and it can obscure what headers we are effectively using. Since module.h was the source for init.h (for __init) and for export.h (for EXPORT_SYMBOL) we consider each obj-y/bool instance for the presence of either and replace as needed. In the case of the n32/o32 files, we have to get rid of a couple no-op MODULE_ tags to facilitate the module.h removal. They piggy back off the fs/ elf binary support, which is also a bool Kconfig. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14032/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 05 7月, 2016 2 次提交
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由 Paul Burton 提交于
The opcodes currently defined in inst.h as cbcond0_op & cbcond1_op are actually defined in the MIPS base instruction set manuals as pop10 & pop30 respectively. Rename them as such, for consistency with the documentation. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Acked-by: NRalf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paul Burton 提交于
The opcodes currently defined in inst.h as beqzcjic_op & bnezcjialc_op are actually defined in the MIPS base instruction set manuals as pop66 & pop76 respectively. Rename them as such, for consistency with the documentation. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Acked-by: NRalf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 28 5月, 2016 1 次提交
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由 Ralf Baechle 提交于
As noticed by Sergei in the discussion of Andrea Gelmini's patch series. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Reported-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
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- 13 5月, 2016 1 次提交
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由 Paul Burton 提交于
The conditions for branching when emulating the BC1EQZ & BC1NEZ instructions were backwards, leading to each of those instructions being treated as the other. Fix this by reversing the conditions, and clear up the code a little for readability & checkpatch. Fixes: c8a34581 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions") Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13151/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 09 7月, 2015 1 次提交
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由 Markos Chandras 提交于
Commits f1b44067 ("MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions") and commit a8ff66f5 ("MIPS: Emulate the new MIPS R6 B{L,G}E{Z,}{AL,}C instructions") added support for emulating various branch compact instructions. However, it missed the case for those which use the old BLEZL and BGTZL opcodes leading to random crashes when the R6 emulator is disabled. We fix this by ensuring that the 'rt' field is not zero which is always true for these branch compact instructions. Fixes: f1b44067 ("MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions") Fixes: a8ff66f5 ("MIPS: Emulate the new MIPS R6 B{L,G}E{Z,}{AL,}C instructions") Cc: <stable@vger.kernel.org> # 4.0+ Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10582/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 01 4月, 2015 1 次提交
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由 Toma Tabacu 提交于
Remove a cast to the 'mips16e_instruction' union inside an if condition and instead do an assignment to a local 'union mips16e_instruction' variable's 'full' member before the if statement and use this variable in the if condition. This is the error message reported by clang: arch/mips/kernel/branch.c:38:8: error: cast to union type from type 'unsigned short' not present in union if (((union mips16e_instruction)inst).ri.opcode ^ ~~~~ The changed code can be compiled successfully by both gcc and clang. Signed-off-by: NToma Tabacu <toma.tabacu@imgtec.com> Signed-off-by: NDaniel Sanders <daniel.sanders@imgtec.com> Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: David Daney <david.daney@cavium.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9312/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 2月, 2015 12 次提交
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由 Leonid Yegoshin 提交于
MIPS R6 removed quite a few R2 instructions. However, there is plenty of <R6 userland code so we add an in-kernel emulator so we can still be able to execute all R2 userland out there. The emulator comes with a handy debugfs under /mips/ directory (r2-emul-stats) to provide some basic statistics of the instructions that are being emulated. Below are some statistics from booting a minimal buildroot image: Instruction Total BDslot ------------------------------ movs 236969 0 hilo 56686 0 muls 55279 0 divs 10941 0 dsps 0 0 bops 1 0 traps 0 0 fpus 0 0 loads 214981 17 stores 103364 0 llsc 56898 0 dsemul 150418 0 jr 370158 bltzl 43 bgezl 1594 bltzll 0 bgezll 0 bltzal 39 bgezal 39 beql 14503 bnel 138741 blezl 0 bgtzl 3988 Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
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由 Markos Chandras 提交于
MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and BNEZLAC instructions. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and BEQZALC instructions. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
MIPS R6 added the following four instructions which share the BGTZ and BGTZL opcode: BLTZALC: Compact branch-and-link if GPR rt is < to zero BGTZALC: Compact branch-and-link if GPR rt is > to zero BLTZL : Compact branch if GPR rt is < to zero BGTZL : Compact branch if GPR rt is > to zero BLTC : Compact branch if GPR rs is less than GPR rt BLTUC : Similar to BLTC but unsigned Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
MIPS R6 added the following four instructions which share the BLEZ and BLEZL opcodes: BLEZALC: Compact branch-and-link if GPR rt is <= to zero BGEZALC: Compact branch-and-link if GPR rt is >= to zero BLEZC : Compact branch if GPR rt is <= to zero BGEZC : Compact branch if GPR rt is >= to zero BGEC : Compact branch if GPR rs is less than or equal to GPR rt BGEUC : Similar to BGEC but unsigned. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
MIPS R6 introduced the following two branch instructions for COP1: BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
MIPS R6 removed the BLTZL, BGEZL, BLTZAL, BGEZAL, BEQL, BNEL, BLEZL, BGTZL branch likely instructions so we must not try to emulate them on MIPS R6 if the R2-to-R6 emulator is not present. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> -
由 Markos Chandras 提交于
The MIPS R6 JR instruction is an alias to the JALR one, so it may need emulation for non-R6 userlands. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
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- 07 11月, 2014 1 次提交
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由 Manuel Lauss 提交于
Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 31 5月, 2014 1 次提交
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由 David Daney 提交于
Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these. Add r4k_fpu.o to handle low level FPU initialization. Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support. Get rid of "#define cpu_has_fpu 0" Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NAndreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7006/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 23 5月, 2014 2 次提交
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由 Ralf Baechle 提交于
mm_isBranchInstr() did reside in the math emu code even though it logically is separate and also is used outside the math emu code. In addition GCC 4.9.0 leaves the following unnnecessarily bloated function body for a non-microMIPS configuration: <mm_isBranchInstr>: 105c: afa50004 sw a1,4(sp) 1060: afa60008 sw a2,8(sp) 1064: afa7000c sw a3,12(sp) 1068: 03e00008 jr ra 106c: 00001021 move v0,zero which stores arguments that are never going to be used on the stack frame. Move mm_isBranchInstr() from cp1emu.c to branch.c, then split mm_isBranchInstr() into a __mm_isBranchInstr() core and a mm_isBranchInstr() wrapper inline function which only invokes __mm_isBranchInstr() on microMIPS configurations. This shaves off 112 bytes off the kernel and improves code flow a bit. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> -
由 Ralf Baechle 提交于
Two issues: o For beql_op, beql_op, bne_op, bnel_op, blez_op, blezl_op, bgtz_op and bgtzl_op the wrong field was being checked for the instruction opcode. o For blez_op / blezl_op and bgtz_op / bgtzl_op the test was testing for the wrong opcode. This bug got introduced by d8d4e3ae [MIPS Kprobes: Refactor branch emulation]. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Acked-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com> Acked-by: NVictor Kamensky <kamensky@cisco.com>
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- 01 7月, 2013 1 次提交
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由 Tony Wu 提交于
Signed-off-by: NTony Wu <tung7970@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5536/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 09 5月, 2013 2 次提交
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由 Steven J. Hill 提交于
Add logic needed to properly calculate exceptions for delay slots when in MIPS16e mode. Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com> -
由 Leonid Yegoshin 提交于
Add logic needed to properly calculate exceptions for delay slots when in microMIPS mode. Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
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- 01 2月, 2013 1 次提交
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由 Ralf Baechle 提交于
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 08 12月, 2011 1 次提交
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由 Maneesh Soni 提交于
This patch refactors MIPS branch emulation code so as to allow skipping delay slot instruction in case of branch likely instructions when branch is not taken. This is useful for keeping the code common for use cases like kprobes where one would like to handle the branch instructions keeping the delay slot instuction also in picture for branch likely instructions. Also allow emulation when instruction to be decoded is not at pt_regs->cp0_epc as in case of kprobes where pt_regs->cp0_epc points to the breakpoint instruction. The patch also exports the function for modules. Signed-off-by: NManeesh Soni <manesoni@cisco.com> Signed-off-by: NVictor Kamensky <kamensky@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2913/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 18 10月, 2010 1 次提交
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由 Al Viro 提交于
Put the original syscall number into ->regs[0] when we leave syscall with error. Use it in restart logics. Everything else will have it 0 since we pass through SAVE_SOME on all the ways in. Note that in places like bad_stack and inllegal_syscall we leave it 0 - it's not restartable. Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk> Cc: linux-kernel@vger.kernel.org Cc: linux-arch@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1698/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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