This was caused by commit 5a8da524 ("ARM: dts: exynos5420: add dsi
node"), which conflicted with d51cad7d ("ARM: dts: remove display
power domain for exynos5420").

The DTS addition should never have been merged through the DRM tree in
the first place, and it lacked an ack from the platform maintainer
(who would have known that the disp_pd reference got removed).
Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds common part of dsi node.
Signed-off-by: NYoungJun Cho <yj44.cho@samsung.com>
Acked-by: NInki Dae <inki.dae@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

This patch adds mipi-phy node for MIPI DSI device.
Signed-off-by: NYoungJun Cho <yj44.cho@samsung.com>
Acked-by: NInki Dae <inki.dae@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

This patch extends nodes of PMU system controller on Exynos4210, 4x12,
5250 and 5420 SoCs with newly defined properties used by Exynos CLKOUT
driver.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Display domain is removed due to instability issues. Explaining
the problem below:

exynos_init_late triggers the pm_genpd_poweroff_unused which powers
off the unused power domains. This call hits before the trigger to
deferred probes.

DRM DP Panel defers the probe due to supply get failure. By the time,
deferred probe is scheduled again, Display Power Domain is powered
off by pm_genpd_poweroff_unused.

FIMD and DP drivers are accessing registers during Probe and Bind
callbacks. If display domain is enabled/disabled around register
accesses, display domain gets unstable and we are getting Power Domain
Disable fail notification. Increasing the Timeout also didn't help.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Adding the optional clock property for the mfc_pd for
handling the re-parenting while pd on/off.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.

The problem surfaced when the bootloader in Peach-pit board set
the EPLL clock as the parent of AUDSS mux. While booting the kernel,
we used to get a system hang during late boot if CLK_MAU_EPLL was
disabled.
Signed-off-by: NTushar Behera <tushar.b@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Reported-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add PMU syscon handle to HDMI dt node for controlling
PHY Enable/Disable bit.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

sss module device node missed clock macro.
This patch replace magic number with macro in clock
binding for exynos5420.
Signed-off-by: NBeomho Seo <beomho.seo@samsung.com>
Reviewed-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add required device node for ehci and ohci controllers to
enable USB 2.0 support.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NVikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add required device node for usb2phy to let enable USB 2.0
support.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NVikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds sysreg-syscon node to exynos5250 and exynos5420 device
tree, to access System Register's registers using syscon driver.
Signed-off-by: NKamil Debski <k.debski@samsung.com>
[gautam.vivek@samsung.com: Split this syreg-syscon dts entry]
[gautam.vivek@samsung.com: added similar syscon entry for exynos5420]
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
[vikas.sajjan@samsung.com: updated the binding document]
Signed-off-by: NVikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Updated as per the user manual.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

PD entry was missing in MFC codec node.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Reviewed-by : Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add device tree nodes for DWC3 controller present on
Exynos 5420 SoC, to enable support for USB 3.0.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add device tree nodes for USB 3.0 PHY present alongwith
USB 3.0 controller Exynos 5420 SoC. This phy driver is
based on generic phy framework.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Enable hdmi for exynos5420 based peach-pit board.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Replace compatible string for HDMI node in Exynos5420. Since
latest restructring in Drm hdmi driver, it is agreed to use
a seperate compatible string for Exynos5420 HDMI IP siince it
uses APB mapped Phy.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add device-tree bindings for the ARM CCI-400 on Exynos5420. There
are two slave interfaces: one for the A15 cluster and one for the
A7 cluster.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

G2D power domain also controls the CMU block of G2D. Since
clock registers can be accessed anytime for viewing
clk_summary, it can cause a system crash if g2d power domain
is disabled.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

MAU powerdomain provides clocks for Audio sub-system block.
This block comprises of the I2S audio controller, audio DMA
blocks and Audio sub-system clock registers.

Right now, there is no way to hook up power-domains with
clock providers.  During late boot when this power-domain
gets disabled, we get following external abort.

Unhandled fault: imprecise external abort (0x1406) at 0x00000000
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This change places MDMA1 in disabled node for Exynos5420.
If MDMA1 region is configured with secure mode, it makes
the boot failure with the following on smdk5420 board.
("Unhandled fault: imprecise external abort (0x1406) at 0x00000000")
Thus, arndale-octa board don't need to do the same thing anymore.
Signed-off-by: NSeungwon Jeon <tgih.jun@samsung.com>
Tested-by: NJavi Merino <javi.merino@arm.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Instead of hardcoding the SYSRAM details for each SoC,
pass this information through device tree (DT) and make
the code SoC agnostic. Generic DT SRAM bindings are
used for achieving this.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch includes,
    1] renaming of the HSI2C clocks
    2] renaming of spi clocks according to the datasheet
    3] fixes for child-parent relationships
    4] adding of more clocks related to PERIC block
    5] use GATE_IP_* offsets instead of GATE_BUS_*
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Adding labels to nodes which do not have it yet in exynos5420.
This is done so as to use reference based node updation in board
files.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Most of the clock related dt-binding header files are located in
dt-bindings/clock folder. It would be good to keep all the similar
header files at a single location.
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Reviewed-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add generic compatible strings to the respective board DT files.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds the device tree node for SSS module
found on Exynos5420 and Exynos5250
Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The patch replaces magic numbers with macros defined in DT header
in exynos5420 clock bindings.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Some boards might not have RTC xtal, so RTC shouldn't really be
enabled by default. Enable it in the required board files.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

In EXYNOS5 series SoCs, PMU has registers to enable/disable mask/unmask
watchdog timer which is not the case with s3c series SoCs so, there is a
need to have different compatible names for watchdog to handle these pmu
registers access.

Hence this patch removes watchdog node from Exynos5.dtsi common file and
make it separate by updating existing node in Exynos5250 and adding new node
to Exynos5420. This patch also makes the watchdog node enabled by default
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds pmusysreg node to exynos5250 and exynos5420 dtsi files to
handle PMU register accesses in a centralized way using syscon driver
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in)
for the AudioSS clock controller.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.

This patch adds the device tree nodes to the DT device list.

Nodes carry the misplaced second base address and the second
clock to access the misplaced base address.
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add the device-tree binding for the PWM controller to Exynos5250 and Exynos5420
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NOlof Johansson <olofj@chromium.org>
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add SPI device tree nodes to Exynos5420 SoC
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds dma controller node info on Exynos5420.
Exynos5420 has adma for audio IPs. As adma clk is dependent
on audss clk provider that will be added later.
Signed-off-by: NPadmavathi Venna <padma.v@samsung.com>
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added high speed I2C nodes to Exynos5420 DT file.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>