Add missing clock branch to enable onboard storage
for msm899(2/4).
Signed-off-by: NJeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

AHB clock branch is needed in order to enable SDHCI
on msm899(2/4).
Signed-off-by: NJeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Pull Samsung clk driver updates from Sylwester Nawrocki:

 - Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY
 - Exynos PLL code updates and overall minor clean-ups

* tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung:
  clk: samsung: mark s3c...._clk_sleep_init() as __init
  clk: samsung: Add enable/disable support for PLL35XX clocks
  clk: samsung: exynos5433: Correct typos in SoC name
  clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
  clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks

Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Use CLK_IS_CRITICAL to handle critical clocks,
  - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1,
  - Add IIC-DVFS clocks for R-Car H3 and M3-W,
  - Minor cleanups.

* tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add IIC-DVFS clock
  clk: renesas: r8a7795: Add IIC-DVFS clock
  clk: renesas: cpg-mssr: Add support for reset control
  clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock
  clk: renesas: cpg-mssr: Document suitability for RZ/G1
  dt-bindings: clock: renesas: cpg-mssr: Document reset control support
  clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff
  clk: renesas: mstp: Make INTC-SYS a critical clock
  clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL

The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.

The clock gating options are a subset of those on the Armada XP.

The core clock divider is different to the Armada XP also.
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

These functions are referencing s3c...._clk_regs[], which are marked as
__initdata. When compiling with CONFIG_DEBUG_SECTION_MISMATCH=y, this
produces warnings like

WARNING: vmlinux.o(.text+0x198350):
Section mismatch in reference from the function s3c2410_clk_sleep_init()
to the (unknown reference) .init.data:(unknown)

Mark the s3c...._clk_sleep_init() functions as __init in
order to fix this.

Fixes: ca2e90ac ("clk: samsung: add clock controller driver for s3c2412")
Signed-off-by: NMartin Kaiser <martin@kaiser.cx>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Some PLLs might be disabled by default after turning off and then on
a power domain which they belongs to.  To avoid configuring a disabled
PLL, add proper code for handling PLL enable/disable.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch fixes simple typos in Exynos5433 clocks driver. The SoC name
was referred a few times as '5443' instead of '5433'.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Default clock configuration applied by the bootloader for TM2 and TM2e
boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure
such configuration for those boards with 'assigned-clock-*' properties,
parameters for those two additional rates are needed.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
to setup initial clock configuration for display subsystem in device tree
in order to avoid dependency on the configuration left by the bootloader.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds DVFS clock for R8A7796 SoC.
Signed-off-by: NKhiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: NDien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds DVFS clock for R8A7795 SoC.
Signed-off-by: NKeita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: NDien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add optional support for the Reset Control feature of the Renesas Clock
Pulse Generator / Module Standby and Software Reset module on R-Car
Gen2, R-Car Gen3, and RZ/G1 SoCs.

This allows to reset SoC devices using the Reset Controller API.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

The spinlock is used to protect Read-Modify-Write register accesses,
which won't be limited to SMSTPCR register accesses.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

The Renesas CPG/MSSR driver is already in active use for RZ/G1 since
commits c0b2d75d ("clk: renesas: cpg-mssr: Add R8A7743 support")
and 9127d54b ("clk: renesas: cpg-mssr: Add R8A7745 support").
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

Document properties needed to use the Reset Control feature of the
Renesas Clock Pulse Generator / Module Standby and Software Reset
module.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

As the function header of cpg_mstp_clock_register() is split in an
unusual way, "git diff" gets confused when changes to the body of
the function are made, and attributes them to the wrong function.

Reformat the function header to fix this.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

s/Acumulate/Accumulate/
Signed-off-by: NPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The BayTrail and CherryTrail platforms provide platform clocks
through their Power Management Controller (PMC).

The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a
frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail
and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks
are available for general system use, where appropriate. For example,
the usage for platform clocks suggested in the datasheet is the
following:
  PLT_CLK[0..2] - Camera
  PLT_CLK[3] - Audio Codec
  PLT_CLK[4] -
  PLT_CLK[5] - COMMs
Signed-off-by: NIrina Tirdea <irina.tirdea@intel.com>
Signed-off-by: NPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The pmc_atom driver does not contain any architecture specific
code. It only enables the SoC Power Management Controller driver
for BayTrail and CherryTrail platforms.

Move the pmc_atom driver from arch/x86/platform/atom to
drivers/platform/x86. Also clean-up and reorder include files by
alphabetical order in pmc_atom.h
Signed-off-by: NIrina Tirdea <irina.tirdea@intel.com>
Signed-off-by: NPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The BayTrail and CherryTrail platforms provide platform clocks
through their Power Management Controller (PMC).

The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a
frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail
and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks
are available for general system use, where appropriate, and each
have Control & Frequency register fields associated with them.

Port from legacy by Pierre Bossart, integration in clock framework
by Irina Tirdea
Signed-off-by: NIrina Tirdea <irina.tirdea@intel.com>
Signed-off-by: NPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK
was not explicit

Fixes: 701190fd ('clk: x86: add support for Lynxpoint LPSS clocks')
Signed-off-by: NPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

In clock driver initialize phase the spinlock is missed to assignment
to struct clkgate_separated, finally there have no locking to protect
exclusive accessing for clock registers.

This bug introduces the console has no output after enable coresight
driver on 96boards Hikey; this is because console using UART3, which
has shared the same register with coresight clock enabling bit. After
applied this patch it can assign lock properly to protect exclusive
accessing, and console can work well after enabled coresight modules.

Fixes: 0aa0c95f ("clk: hisilicon: add common clock support")
Signed-off-by: NLeo Yan <leo.yan@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-ux500:
  clk: ux500: Convert ABx500 clocks to use OF probing
  clk: ux500: Add device tree bindings for ABx500 clocks
  clk: ux500: move AB8500 sysclk over to PRCMU clk driver

These clocks have been broken for a long time unfortunately, a
hurdle of misc problems made them stop working at some point
breaking USB and audio on Ux500.

The platform as such and all "regular" clocks are migrated to
OF/device tree, so let's migrate also this driver.

With this patch and the corresponding DTS fixes, and a bunch
of probe deferral fixes, audio starts working again on Ux500.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This adds device tree bindings for the ABx500 clocks on the
ST-Ericsson platforms.

Cc: devicetree@vger.kernel.org
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The AB8500 sysclk is just another PRCMU-controlled clock, there
is no reason why it should be in the ABx500-controlled part of
the clock implementation. Doing this and the corresponding device
tree changes makes USB work on the Ux500 again.
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The MT8135 is a 32-bit SoC, so only propose it on ARM architecture,
not ARM64.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Fixes: 234d511d ("clk: mediatek: Add hardware dependency")
Cc: Andreas Färber <afaerber@suse.de>
Acked-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

If I say "no" to "Clock driver for Mediatek MT2701", I don't want to
be asked individually about each sub-driver. No means no.

Additionally, this driver shouldn't be proposed at all on non-mediatek
builds, unless build-testing.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Fixes: e9862118 ("clk: mediatek: Add MT2701 clock support")
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NJames Liao <jamesjj.liao@mediatek.com>
Cc: Shunli Wang <shunli.wang@mediatek.com>
Cc: Erin Lo <erin.lo@mediatek.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Currently the divider selection logic blindly divides the parent_rate
by the clk rate and gives the divider value for the divider clocks
which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider
table parsing to get the closest divider available in the table
provided via Device tree.

The code is pretty much taken from: drivers/clk/clk-divider.c.
and used here to fix up the best divider selection logic.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Reported-by: NRichard Woodruff <r-woodruff2@ti.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Once a gdsc is brought in and out of HW control, there is a
power down and up cycle which can take upto 1us. Polling on
the gdsc status immediately after the hw control enable/disable
can mislead software/firmware to belive the gdsc is already either on
or off, while its yet to complete the power cycle.
To avoid this add a 1us delay post a enable/disable of HW control
mode.

Also after the HW control mode is disabled, poll on the status to
check gdsc status reflects its 'on' before force disabling it
in software.
Reported-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Reviewed-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Tested-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Fixes: 904bb4f5 ("clk: qcom: gdsc: Add support for gdscs with HW control")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

During meson8b clock probe, clk81 register address is fixed twice.
First using the meson8b_clk_gates array, then by directly changing
meson8b_clk81 register.

As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.

Fixed by just removing the second fixup.

Fixes: e31a1900 ("meson: clk: Add support for clock gates")
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch enables clocks for STM32F746 boards.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-stm32f4:
  clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards

Do not let the entire probe function fail even if some clocks fail
to register.  Let's continue with succeeded clocks.  This will give
the system more chances to boot and allow us to investigate the
cause of the failure.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-imx7:
  clk: imx7d: Add the OCOTP clock

* clk-bcm2835:
  clk: bcm2835: Add leaf clock measurement support, disabled by default
  clk: bcm2835: Register the DSI0/DSI1 pixel clocks.
  clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.

INTC-SYS is the module clock for the GIC.  Accessing the GIC while it is
disabled causes:

    Unhandled fault: asynchronous external abort (0x1211) at 0x00000000

Currently, the GIC-400 driver cannot enable its module clock for several
reasons:
  - It does not use a platform device, so Runtime PM is not an option,
  - gic_of_init() runs before any clocks are registered, so it cannot
    enable the clock explicitly,
  - gic_of_init() cannot return -EPROBE_DEFER, as IRQCHIP_DECLARE()
    doesn't support deferred probing.

Hence we have to keep on relying on the boot loader for enabling the
module clock.

To prevent the module clock from being disabled when the CCF core thinks
it is unused, and thus causing a system lock-up, add a check to the MSTP
clock driver and enable CLK_IS_CRITICAL. This will make sure the module
clock is never disabled.

This is a hard dependency for describing the INTC-SYS clock in DT on
R-Mobile APE6 and R-Car Gen2.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

When the Renesas CPG/MSSR driver was introduced, it was anticipated that
critical clocks would be handled through a new CLK_ENABLE_HAND_OFF flag
soon.  However, CLK_ENABLE_HAND_OFF never made it upstream.

Instead, commit 32b9b109 ("clk: Allow clocks to be marked as
CRITICAL") introduced CLK_IS_CRITICAL, a flag with slightly differing
semantics.  Still, it can be used to prevent e.g. the GIC module clock
from being turned off, until the GIC-400 driver has full support for
Runtime PM.

Hence migrate the Renesas CPG/MSSR driver from CLK_ENABLE_HAND_OFF to
CLK_IS_CRITICAL.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

This patch introduces the stm32f7 clock DT bindings.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the OCOTP so that this hardware block can be used.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>