- 20 10月, 2010 1 次提交
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由 Eric Bénard 提交于
* get_rate_arm : when 400MHz clock is selected (cctl & 1<<14), ARM clock is 400MHz (MPLL * 3 / 4) and not 800MHz * get_rate_per : peripherals's clock is derived from AHB and not from IPG (ref manual : figure 5-1) * can2_clk : use the correct ID * without this patch, peripherals getting their clock from PER clocks work fine because of the 2 errors which fix themselves (ARM clock x 2 and per clock actually based on IPG which is AHB/2) but flexcan can't work as it gets its clock from IPG and thus calculates its bitrate using a reference value which is twice what it really is. Signed-off-by: NEric Bénard <eric@eukrea.com>
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- 11 10月, 2010 2 次提交
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由 Wolfram Sang 提交于
So the correct clock will be taken for each of the two independent controllers. Signed-off-by: NWolfram Sang <w.sang@pengutronix.de> Cc: Eric Bénard <eric@eukrea.com> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Eric Bénard 提交于
Signed-off-by: NEric Bénard <eric@eukrea.com> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 01 10月, 2010 1 次提交
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由 Uwe Kleine-König 提交于
The driver recently learned to handle platform ids. Make use of this new feature. The up side is that the driver needs less knowledge about the spi interfaces used on different SoCs. Acked-by: NJason Wang <jason77.wang@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 26 7月, 2010 8 次提交
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由 Sascha Hauer 提交于
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Eric Bénard 提交于
DEBUG_LL is actually broken on i.MX25, this patch fix it. Signed-off-by: NEric Bénard <eric@eukrea.com> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Baruch Siach 提交于
The information in the i.MX25 Reference Manual is lacking. Add information from the Freescale BSP. Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Acked-by: NWolfram Sang <w.sang@pengutronix.de> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Reviewed-by: NWolfram Sang <w.sang@pengutronix.de> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Eric Bénard 提交于
* add clocks for audmux and ssi 1 & 2 * add irq for ssi 1 & 2 * add devices platform for ssi1 & 2 * update audmux-v2 for i.MX25 * add base addresses for audmux & ssi 1 & 2 * add iomux configuration for GPIO for AUD5 port Signed-off-by: NEric Bénard <eric@eukrea.com> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Eric Bénard 提交于
usb drivers need to get the right value for otg clock so calculate and return it Signed-off-by: NEric Bénard <eric@eukrea.com> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 18 2月, 2010 1 次提交
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由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 13 2月, 2010 1 次提交
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由 Russell King 提交于
Most machine classes want some way to register a block of clk_lookup structures, and most do it by implementing a clks_register() type function which walks an array, or by open-coding a loop. Consolidate all this into clkdev_add_table(). Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: NKevin Hilman <khilman@deeprootsystems.com> Acked-by: NEric Miao <eric.y.miao@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 29 1月, 2010 1 次提交
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由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 27 1月, 2010 6 次提交
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由 Baruch Siach 提交于
This makes the FEC clock configuration consistent with the UART one. Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Baruch Siach 提交于
The gpt_clk rate function doesn't consider the PER divider. This causes a significant drift in time accounting. Fix this by introducing the correct rate calculation function. Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Baruch Siach 提交于
This patch disables all unnecessary clock in mx25_clocks_init() to make a clean start, the same as is being done for the rest of the i.MX chips. This patch was tested on i.MX25 PDK. Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Baruch Siach 提交于
The fref is needless on mx25 since the reference clock is fixed at 24MHz. Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Sascha Hauer 提交于
For uarts and fec need two clocks, implement it using the secondary clock field in struct clk. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Sascha Hauer 提交于
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 04 1月, 2010 1 次提交
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由 Baruch Siach 提交于
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 14 8月, 2009 1 次提交
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由 Sascha Hauer 提交于
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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