1. 21 5月, 2010 2 次提交
    • P
      OMAP3 clock: rename RATE_IN_343X, RATE_IN_3430ES2 to match reality · 63405360
      Paul Walmsley 提交于
      Rename the RATE_IN_343X clksel_rate.rate flag to be RATE_IN_3XXX, to reflect
      that these rates are valid on all OMAP3 platforms, not just 343X.
      
      Also rename the RATE_IN_OMAP3430ES2 clksel_rate.rate flag to be
      RATE_IN_OMAP3430ES2PLUS, to reflect that these flags are valid on all
      OMAP3 platforms after 3430ES2.
      
      This patch should not result in any functional changes.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Richard Woodruff <r-woodruff2@ti.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      Cc: Ranjith Lohithakshan <ranjithl@ti.com>
      63405360
    • P
      OMAP2+ clock: remove DEFAULT_RATE clksel_rate flag · d74b4949
      Paul Walmsley 提交于
      The DEFAULT_RATE clksel_rate flag is essentially useless.  It was set
      on some of the lowest divisors, which, when switching to a much
      higher-rate parent, could have potentially resulted in rates that
      exceeded the hardware specifications for downstream clocks in the
      window between the clk_set_parent(), and a subsequent clk_set_rate().
      It seems much safer to just remove the flag and always use the highest
      available divisor (resulting in the lowest possible rate) after the
      switch, and this patch does so.
      
      Ideally, it would be best to first attempt to switch to a divisor that
      matches the clock's rate with the previous parent, if at all possible.
      But that is a project for some other day or some other person.  The
      parent changing code is rarely used.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      d74b4949
  2. 12 12月, 2009 1 次提交