Some gcc's are more anal than others about empty switch labels.
error: label at end of compound statement
Signed-off-by: NDave Jones <davej@redhat.com>

C7's are centrino speedstep-alike.
Signed-off-by: NDave Jones <davej@redhat.com>

Support for CN400 northbridge when ACPI C3 isn't available.
Tested on Epia SP13000. Thanks to Robert for testing it.
Signed-off-by: NRafa Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

On board of Epia SP13000 is 10x133Mhz VIA Nehemiah. It is reported
as 10x200MHz. This patch is fixing this issue.
Signed-off-by: NRafa Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

removing duplicated code.
Signed-off-by: NRafa Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

Please ignore previous message.

This patch is adding support for CPU connected to CLE266
chipset. For older CPU this is only way. For "Powersaver"
processor this way will be used if ACPI C3 isn't supported.

I have tested it. It seems to work exacly like ACPI.
But it is less safe. On CLE266 chipset port 0x22 is
blocking processor access to PCI bus too.
Signed-off-by: NRafa³ Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

Rename option "dont_scale_voltage" to "scale_voltage" because
don't will be default.
Use "pos" for calculating voltage. In this way driver don't need
to know mV value or low level value. Simply min U is one pos and
max U is second pos. All pos between these two are used.
Assume that min U is for min f and max U for max f. For frequency
between min and max calculate pos based on difference between
current frequency and min f.
Values in mobile VRM table changed to values from
C3-M datasheet.
Signed-off-by: NRafa³ Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

Some laptops with VIA C3 processor, CLE266 chipset and
AMI BIOS have incorrect latency values in FADT table. These
laptops seems to be C3 capable, but latency values are to
big: 101 for C2 and 1017 for C3. This option will allow
user to skip C3 latency test but not C3 address test. AMI
BIOS is setting C3 address to correct value in DSDT table.
Signed-off-by: NRafa Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

ACPI C3 works for "Powersaver" processors, so use it only for them.

Older CPU will change frequency on "halt" only. But we can protect transition
in two ways:
- by ACPI PM2 register, there is "bus master arbiter disable" bit.
  This isn't tested because VIA mainboards don't have PM2 register,
- by PLE133 PCI/AGP arbiter disable register.
  There are two bits in this register. First is "PCI arbiter disable",
  second "AGP arbiter disable". This is working on VIA Epia 800 mainboards.

Test on bm_control is more proper because this is true
when PM2 register exist.
Signed-off-by: NRafa³ Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

This table is only used by Ezra-T CPUs currently, and has values
for some other CPU. Fix them to match the values used by that CPU,
and for now make it clearer by renaming the variable.
Signed-off-by: NRafa³ Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

This is changing "always true" test to something usefull.
Signed-off-by: NRafa Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

I lost very important line in do_powersaver
Signed-off-by: NRafa Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

This patch makes the needlessly global longhaul_walk_callback() static.
Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Signed-off-by: NDave Jones <davej@redhat.com>

Without this longhaul will always fail when compiled into kernel,
as it needs to initialise after the ACPI processor module.

I lost this when I was splitting patches. Sorry.
Signed-off-by: NRafa Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

There is no need to worry about local APIC.
There is need to worry about I/O APIC, because I/O APIC
is replacing good old 8259. According to Nehemiah datasheet VIA is
using 3-wire bus to connect local APIC to I/O APIC.

"[...] When IA32_APIC_BASE[11] is set to 0, processor APICs based on the 3-wire APIC
 bus cannot be generally re-enabled until a system hardware reset. The 3-wire bus
 looses track of arbitration that would be necessary for complete re-enabling. Certain
 (local) APIC functionality can be enabled. [...]"

So we must set disable bit for each interrupt in I/O APIC registers.
Same situation as for PIC - we must poke registers direcly.
How to do this? I don't know. So at the moment it is better to fail.
Signed-off-by: NRafa³ Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

Minimal change necessary for hardware support.

Changes in longhaul.c:
- most important - now C3 state is causing transition,
- code responsible for clearing "bus master" bit removed,
- protect bcr2 transition in the same way as longhaul.
Signed-off-by: NRafa³ Bilski <rafalbilski@interia.pl>
Signed-off-by: NDave Jones <davej@redhat.com>

Signed-off-by: NDave Jones <davej@redhat.com>

Getting ready to move to core cpufreq.
- Use snprintf
- Remove unnecessary nesting improving readability.
Signed-off-by: NDave Jones <davej@redhat.com>

i386 Inline asm cleanup.  Use cr/dr accessor functions.

Also, a potential bugfix.  Also, some CR accessors really should be volatile.
Reads from CR0 (numeric state may change in an exception handler), writes to
CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction
re-ordering.  I did not add memory clobber to CR3 / CR4 / CR0 updates, as it
was not there to begin with, and in no case should kernel memory be clobbered,
except when doing a TLB flush, which already has memory clobber.

I noticed that page invalidation does not have a memory clobber.  I can't find
a bug as a result, but there is definitely a potential for a bug here:

#define __flush_tlb_single(addr) \
	__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
Signed-off-by: NZachary Amsden <zach@vmware.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

From: Denis Vlasenko <vda@ilport.com.ua>
Signed-off-by: NDave Jones <davej@redhat.com>

From patch by: Ken Staton <ken_staton@agilent.com>
Signed-off-by: NDave Jones <davej@redhat.com>

As mandated by the spec, disable timer around transitions.

From code by : Ken Staton <ken_staton@agilent.com
Signed-off-by: NDave Jones <davej@redhat.com>

The spec states that we have to do this, which is *horrid*.

Based on code from: Ken Staton <ken_staton@agilent.com>
Signed-off-by: NDave Jones <davej@redhat.com>

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!