1. 28 6月, 2005 5 次提交
    • D
      [PATCH] PCI: DMA bursting advice · e24c2d96
      David S. Miller 提交于
      After seeing, at best, "guesses" as to the following kind
      of information in several drivers, I decided that we really
      need a way for platforms to specifically give advice in this
      area for what works best with their PCI controller implementation.
      
      Basically, this new interface gives DMA bursting advice on
      PCI.  There are three forms of the advice:
      
      1) Burst as much as possible, it is not necessary to end bursts
         on some particular boundary for best performance.
      
      2) Burst on some byte count multiple.  A DMA burst to some multiple of
         number of bytes may be done, but it is important to end the burst
         on an exact multiple for best performance.
      
         The best example of this I am aware of are the PPC64 PCI
         controllers, where if you end a burst mid-cacheline then
         chip has to refetch the data and the IOMMU translations
         which hurts performance a lot.
      
      3) Burst on a single byte count multiple.  Bursts shall end
         exactly on the next multiple boundary for best performance.
      
         Sparc64 and Alpha's PCI controllers operate this way.  They
         disconnect any device which tries to burst across a cacheline
         boundary.
      
         Actually, newer sparc64 PCI controllers do not have this behavior.
         That is why the "pdev" is passed into the interface, so I can
         add code later to check which PCI controller the system is using
         and give advice accordingly.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      e24c2d96
    • M
      [PATCH] PCI: fix-pci-mmap-on-ppc-and-ppc64.patch · 2311b1f2
      Michael Ellerman 提交于
      This is an updated version of Ben's fix-pci-mmap-on-ppc-and-ppc64.patch
      which is in 2.6.12-rc4-mm1.
      
      It fixes the patch to work on PPC iSeries, removes some debug printks
      at Ben's request, and incorporates your
      fix-pci-mmap-on-ppc-and-ppc64-fix.patch also.
      
      Originally from Benjamin Herrenschmidt <benh@kernel.crashing.org>
      
      This patch was discussed at length on linux-pci and so far, the last
      iteration of it didn't raise any comment.  It's effect is a nop on
      architecture that don't define the new pci_resource_to_user() callback
      anyway.  It allows architecture like ppc who put weird things inside of
      PCI resource structures to convert to some different value for user
      visible ones.  It also fixes mmap'ing of IO space on those archs.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      2311b1f2
    • K
      [PATCH] ACPI based I/O APIC hot-plug: acpiphp support · a0d399a8
      Kenji Kaneshige 提交于
      This patch adds PCI based I/O xAPIC hot-add support to ACPIPHP
      driver. When PCI root bridge is hot-added, all PCI based I/O xAPICs
      under the root bridge are hot-added by this patch. Hot-remove support
      is TBD.
      Signed-off-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      a0d399a8
    • K
      [PATCH] ACPI based I/O APIC hot-plug: add interfaces · b1bb248a
      Kenji Kaneshige 提交于
      This patch adds the following new interfaces for I/O xAPIC
      hotplug. The implementation of these interfaces depends on each
      architecture.
      
          o int acpi_register_ioapic(acpi_handle handle, u64 phys_addr,
      			       u32 gsi_base);
      
              This new interface is to add a new I/O xAPIC specified by
              phys_addr and gsi_base pair. phys_addr is the physical address
              to which the I/O xAPIC is mapped and gsi_base is global system
              interrupt base of the I/O xAPIC. acpi_register_ioapic returns
              0 on success, or negative value on error.
      
          o int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base);
      
              This new interface is to remove a I/O xAPIC specified by
              gsi_base. acpi_unregister_ioapic returns 0 on success, or
              negative value on error.
      Signed-off-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      b1bb248a
    • R
      [PATCH] acpi bridge hotadd: ACPI based root bridge hot-add · c431ada4
      Rajesh Shah 提交于
      When you hot-plug a (root) bridge hierarchy, it may have p2p bridges and
      devices attached to it that have not been configured by firmware.  In this
      case, we need to configure the devices before starting them.  This patch
      separates device start from device scan so that we can introduce the
      configuration step in the middle.
      
      I kept the existing semantics for pci_scan_bus() since there are a huge number
      of callers to that function.
      
      Also, I have no way of testing the changes I made to the parisc files, so this
      needs review by those folks.  Sorry for the massive cross-post, this touches
      files in many different places.
      Signed-off-by: NRajesh Shah <rajesh.shah@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      c431ada4
  2. 27 6月, 2005 2 次提交
    • D
      [ATALK]: Include asm/byteorder.h in linux/atalk.h · 32e9e25e
      David S. Miller 提交于
      We're using __be16 in userland visible types, so we
      have to include asm/byteorder.h so that works.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      32e9e25e
    • J
      bonding: xor/802.3ad improved slave hash · 169a3e66
      Jay Vosburgh 提交于
      Add support for alternate slave selection algorithms to bonding
      balance-xor and 802.3ad modes.  Default mode (what we have now: xor of
      MAC addresses) is "layer2", new choice is "layer3+4", using IP and port
      information for hashing to select peer.
      
      Originally submitted by Jason Gabler for balance-xor mode;
      modified by Jay Vosburgh to additionally support 802.3ad mode.  Jason's
      original comment is as follows:
      
      The attached patch to the Linux Etherchannel Bonding driver modifies the
      driver's "balance-xor" mode as follows:
      
            - alternate hashing policy support for mode 2
              * Added kernel parameter "xmit_policy" to allow the specification
                of different hashing policies for mode 2.  The original mode 2
                policy is the default, now found in xmit_hash_policy_layer2().
              * Added xmit_hash_policy_layer34()
      
      This patch was inspired by hashing policies implemented by Cisco,
      Foundry and IBM, which are explained in
      Foundry documentation found at:
      http://www.foundrynet.com/services/documentation/sribcg/Trunking.html#112750Signed-off-by: NJason Gabler <jygabler@lbl.gov>
      Signed-off-by: NJay Vosburgh <fubar@us.ibm.com>
      169a3e66
  3. 26 6月, 2005 27 次提交
  4. 25 6月, 2005 1 次提交
  5. 24 6月, 2005 5 次提交