- 28 5月, 2014 1 次提交
-
-
由 Tero Kristo 提交于
This patch adds support for omap2 type aplls, which have gating and autoidle functionality. Signed-off-by: NTero Kristo <t-kristo@ti.com>
-
- 18 1月, 2014 1 次提交
-
-
由 J Keerthy 提交于
The patch adds support for DRA7 PCIe APLL. The APLL sources the optional functional clocks for PCIe module. APLL stands for Analog PLL. This is different when comapred with DPLL meaning Digital PLL, the phase detection is done using an analog circuit. Signed-off-by: NJ Keerthy <j-keerthy@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
-