1. 19 9月, 2014 3 次提交
  2. 08 5月, 2014 1 次提交
  3. 12 6月, 2013 1 次提交
  4. 01 11月, 2012 4 次提交
  5. 19 10月, 2012 1 次提交
    • T
      ARM: OMAP: Split plat/cpu.h into local soc.h for mach-omap1 and mach-omap2 · e4c060db
      Tony Lindgren 提交于
      We want to remove plat/cpu.h. To do this, let's first split
      it to private soc.h to mach-omap1 and mach-omap2. We have to
      keep plat/cpu.h around until the remaining drivers are fixed,
      so let's include the local soc.h in plat/cpu.h and for drivers
      still including plat/cpu.h.
      
      Once the drivers are fixed not to include plat/cpu.h, we
      can remove the file.
      
      This is needed for the ARM common zImage support.
      
      [tony@atomide.com: updated to not print a warning]
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      e4c060db
  6. 18 10月, 2012 1 次提交
  7. 11 9月, 2012 1 次提交
  8. 31 8月, 2012 2 次提交
  9. 09 7月, 2012 1 次提交
  10. 05 7月, 2012 2 次提交
    • V
      ARM: OMAP2+: am33xx: Change cpu_is_am33xx to soc_is_am33xx · 971b8a9c
      Vaibhav Hiremath 提交于
      As per recent discussion on the linux-omap list, we are
      moving in the direction where, we will have only architecture,
      ARCH_OMAP2PLUS and all devices/platforms will be treated
      as a SoC underneath.
      
      So the first step in this direction is to adopt this change
      for all new devices getting in, converting
      cpu_is_am33xx/335x() ==> soc_is_am33xx/335x()
      Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      971b8a9c
    • V
      ARM: OMAP2+: am33xx: Make am33xx as a separate class · 1c213ba1
      Vaibhav Hiremath 提交于
      Initially, we decided to make am33xx family of device to fall
      under omap3 class (cpu_is_omap34xx() = true), since it carries
      Cortex-A8 core. But while adding complete baseport support
      (like, clock, power and hwmod) support, it is observed that,
      we are creating more and more problems by treating am33xx device
      as omap3 family, as nothing matches between them
      (except cortex-A8 mpu).
      
      So,  after long discussion we have came to the conclusion that,
      we should not consider am33xx device as omap3 family, instead
      create separate class (SOC_AM33XX) under OMAP2PLUS.
      This means, for am33xx device, cpu_is_omap34xx() will return false,
      and only cpu_is_am33xx() will be true.
      
      Please refer to the link below, for mailing-list discussion on this -
      
      http://www.spinics.net/lists/linux-omap/msg69439.htmlSigned-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      [tony@atomide.com: fixed typo, updated for soc_is changes]
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      1c213ba1
  11. 18 4月, 2012 1 次提交
    • G
      ARM: OMAP: sram: fix BUG in dpll code for !PM case · 63878acf
      Grazvydas Ignotas 提交于
      _omap3_sram_configure_core_dpll is called when SDRC is reprogrammed,
      which is done regardless of CONFIG_PM setting, so we always need it's
      setup code too. Without this, we hit a BUG() on OMAP3 when kernel is
      built without CONFIG_PM:
      
      Reprogramming SDRC clock to 332000000 Hz
      ------------[ cut here ]------------
      kernel BUG at arch/arm/plat-omap/sram.c:342!
      Internal error: Oops - BUG: 0 [#1] ARM
      ...
      [<c001c694>] (omap3_configure_core_dpll+0x68/0x6c) from [<c001b2dc>] (omap3_core_dpll_m2_set_rate+0x1)
      [<c001b2dc>] (omap3_core_dpll_m2_set_rate+0x138/0x1b0) from [<c001a478>] (omap2_clk_set_rate+0x14/0x2)
      [<c001a478>] (omap2_clk_set_rate+0x14/0x20) from [<c001c9dc>] (clk_set_rate+0x54/0x74)
      [<c001c9dc>] (clk_set_rate+0x54/0x74) from [<c022b9c8>] (omap_sdrc_init+0x70/0x90)
      [<c022b9c8>] (omap_sdrc_init+0x70/0x90) from [<c022f178>] (omap3pandora_init+0x11c/0x164)
      [<c022f178>] (omap3pandora_init+0x11c/0x164) from [<c022849c>] (customize_machine+0x20/0x28)
      [<c022849c>] (customize_machine+0x20/0x28) from [<c0225810>] (do_one_initcall+0xa0/0x16c)
      [<c0225810>] (do_one_initcall+0xa0/0x16c) from [<c02259e0>] (kernel_init+0x104/0x1ac)
      [<c02259e0>] (kernel_init+0x104/0x1ac) from [<c0009cec>] (kernel_thread_exit+0x0/0x8)
      Signed-off-by: NGrazvydas Ignotas <notasas@gmail.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      63878acf
  12. 13 4月, 2012 1 次提交
    • P
      ARM: OMAP: OCM RAM: use memset_io() when clearing SRAM · 7cc0442c
      Paul Walmsley 提交于
      We currently treat the OCM RAM memory as memory that hangs off an
      I/O bus, so use memset_io() to clear it rather than memset().
      This also takes care of this sparse warning:
      
      arch/arm/plat-omap/sram.c:199:9: warning: cast removes address space of expression
      
      There is still one SRAM-related sparse warning, but it appears that
      fixing it correctly will take some time and thought.
      
      N.B., at some point, the OCM RAM IP block interface code should probably
      be reimplemented as an MTD device or something similar under drivers/.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      7cc0442c
  13. 06 3月, 2012 1 次提交
  14. 25 2月, 2012 1 次提交
  15. 09 12月, 2011 3 次提交
    • J
      ARM: OMAP1: Update dpll1 default rate reprogramming method · f9e5908f
      Janusz Krzysztofik 提交于
      According to comments in omap1_select_table_rate(), reprogramming dpll1
      is tricky, and should always be done from SRAM.
      
      While being at it, move OMAP730 special case handling inside
      omap_sram_reprogram_clock().
      
      Created on top of version 2 of the series "ARM: OMAP1: Fix dpll1
      reprogramming related issues", which it depends on.
      Tested on Amstrad Delta.
      Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      f9e5908f
    • T
      ARM: OMAP1: Set the omap1623 sram size to 16K · ee62e93a
      Tony Lindgren 提交于
      Now that we're always reprogramming the core clock we must make
      sure SRAM works. It seems that neither omap1621 or omap1623
      has 256K of SRAM. Set the SRAM size to safe value of 16K.
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      ee62e93a
    • S
      ARM: OMAP4: Fix errata i688 with MPU interconnect barriers. · 137d105d
      Santosh Shilimkar 提交于
      On OMAP4 SOC, intecronnects has many write buffers in the async bridges
      and they need to be drained before CPU enters into standby state.
      
      Patch 'OMAP4: PM: Add CPUX OFF mode support' added CPU PM support
      but OMAP errata i688 (Async Bridge Corruption) needs to be taken
      care to avoid issues like system freeze, CPU deadlocks, random
      crashes with register accesses, synchronisation loss on initiators
      operating on both interconnect port simultaneously.
      
      As per the errata, if a data is stalled inside asynchronous bridge
      because of back pressure, it may be accepted multiple times, creating
      pointer misalignment that will corrupt next transfers on that data
      path until next reset of the system (No recovery procedure once
      the issue is hit, the path remains consistently broken).
      Async bridge can be found on path between MPU to EMIF and
      MPU to L3 interconnect. This situation can happen only when the
      idle is initiated by a Master Request Disconnection (which is
      trigged by software when executing WFI on CPU).
      
      The work-around for this errata needs all the initiators
      connected through async bridge must ensure that data path
      is properly drained before issuing WFI. This condition will be
      met if one Strongly ordered access is performed to the
      target right before executing the WFI. In MPU case, L3 T2ASYNC
      FIFO and DDR T2ASYNC FIFO needs to be drained. IO barrier ensure
      that there is no synchronisation loss on initiators operating
      on both interconnect port simultaneously.
      
      Thanks to Russell for a tip to conver assembly function to
      C fuction there by reducing 40 odd lines of code from the patch.
      Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Signed-off-by: NRichard Woodruff <r-woodruff2@ti.com>
      Acked-by: NJean Pihet <j-pihet@ti.com>
      Reviewed-by: NKevin Hilman <khilman@ti.com>
      Tested-by: NVishwanath BS <vishwanath.bs@ti.com>
      Signed-off-by: NKevin Hilman <khilman@ti.com>
      137d105d
  16. 20 10月, 2011 2 次提交
  17. 30 6月, 2011 1 次提交
    • J
      ARM: pm: omap3: run the ASM sleep code from DDR · 46e130d2
      Jean Pihet 提交于
      Most of the ASM sleep code (in arch/arm/mach-omap2/sleep34xx.S)
      is copied to internal SRAM at boot and after wake-up from CORE OFF
      mode.  However only a small part of the code really needs to run from
      internal SRAM.
      
      This fix lets most of the ASM idle code run from the DDR in order to
      minimize the SRAM usage and the overhead in the code copy.
      
      The only pieces of code that are mandatory in SRAM are:
      - the i443 erratum WA,
      - the i581 erratum WA,
      - the security extension code.
      
      SRAM usage:
      - original code:
        . 560 bytes for omap3_sram_configure_core_dpll (used by DVFS),
        . 852 bytes for omap_sram_idle (used by suspend/resume in RETention),
        . 124 bytes for es3_sdrc_fix (used by suspend/resume in OFF mode on ES3.x),
        . 108 bytes for save_secure_ram_context (used on HS parts only).
      
      With this fix the usage for suspend/resume in RETention goes down 288
      bytes, so the gain in SRAM usage for suspend/resume is 564 bytes.
      
      Also fixed the SRAM initialization sequence to avoid an unnecessary
      copy to SRAM at boot time and for readability.
      
      Tested on Beagleboard (ES2.x) in idle with full RET and OFF modes.
      
      Kevin Hilman tested retention and off on 3430/n900, 3530/Overo and
      3630/Zoom3
      Signed-off-by: NJean Pihet <j-pihet@ti.com>
      Reviewed-by: NKevin Hilman <khilman@ti.com>
      Tested-by: NKevin Hilman <khilman@ti.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      46e130d2
  18. 31 5月, 2011 1 次提交
  19. 18 2月, 2011 1 次提交
  20. 04 2月, 2011 1 次提交
  21. 28 1月, 2011 1 次提交
  22. 22 12月, 2010 2 次提交
  23. 10 12月, 2010 1 次提交
  24. 25 11月, 2010 1 次提交
    • A
      arm: omap1: make some functions static · e6f16821
      Aaro Koskinen 提交于
      Make some functions static to get rid of the following sparse warnings:
      
      arch/arm/mach-omap1/mcbsp.c:177:12: warning: symbol 'omap1_mcbsp_init' was not declared. Should it be static?
      arch/arm/mach-omap1/mux.c:346:22: warning: symbol 'omap1_cfg_reg' was not declared. Should it be static?
      arch/arm/plat-omap/dma.c:177:5: warning: symbol 'omap_dma_in_1510_mode' was not declared. Should it be static?
      arch/arm/plat-omap/sram.c:273:12: warning: symbol 'omap1_sram_init' was not declared. Should it be static?
      Signed-off-by: NAaro Koskinen <aaro.koskinen@nokia.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      e6f16821
  25. 09 10月, 2010 2 次提交
    • P
      OMAP: split plat-omap/common.c · aa218daf
      Paul Walmsley 提交于
      Split plat-omap/common.c into three pieces:
      
      1. the 32KiHz sync timer and clocksource code, which now lives in
         plat-omap/counter_32k.c;
      
      2. the OMAP2+ common code, which has been moved to mach-omap2/common.c;
      
      3. and the remainder of the OMAP-wide common code, which includes the
         deprecated ATAGs code and a deprecated video RAM reservation function.
      
      The primary motivation for doing this is to move the OMAP2+-specific parts
      into an OMAP2+-specific file, so that build breakage related to the
      System Control Module code can be resolved.
      
      Benoît Cousson <b-cousson@ti.com> suggested a new filename and found
      some bugs in the counter_32k.c comments - thanks Benoît.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Benoît Cousson <b-cousson@ti.com>
      aa218daf
    • M
      OMAP: plat-omap: Fix static function warnings · b0a330dc
      Manjunath Kondaiah G 提交于
      This patch fixes sparse warnings due non declarations of static functions.
      
      arch/arm/plat-omap/sram.c:130:13: warning: symbol 'omap_detect_sram' was not declared. Should it be static?
      arch/arm/plat-omap/sram.c:216:13: warning: symbol 'omap_map_sram' was not declared. Should it be static?
      arch/arm/plat-omap/sram.c:450:12: warning: symbol 'omap_sram_init' was not declared. Should it be static?
      arch/arm/plat-omap/sram.c:348:12: warning: symbol 'omap242x_sram_init' was not declared. Should it be static?
      arch/arm/plat-omap/sram.c:369:12: warning: symbol 'omap243x_sram_init' was not declared. Should it be static?
      arch/arm/plat-omap/sram.c:425:12: warning: symbol 'omap34xx_sram_init' was not declared. Should it be static?
      arch/arm/plat-omap/sram.c:441:12: warning: symbol 'omap44xx_sram_init' was not declared. Should it be static
      
      arch/arm/plat-omap/mcbsp.c:36:6: warning: symbol 'omap_mcbsp_write' was not declared. Should it be static?
      arch/arm/plat-omap/mcbsp.c:50:5: warning: symbol 'omap_mcbsp_read' was not declared. Should it be static?
      arch/arm/plat-omap/mcbsp.c:65:6: warning: symbol 'omap_mcbsp_st_write' was not declared. Should it be static?
      arch/arm/plat-omap/mcbsp.c:70:5: warning: symbol 'omap_mcbsp_st_read' was not declared. Should it be static?
      arch/arm/plat-omap/mcbsp.c:1648:15: warning: symbol 'omap_st_add' was not declared. Should it be static?
      
      arch/arm/plat-omap/fb.c:414:15: warning: symbol 'omapfb_reserve_sram' was not declared. Should it be static?
      arch/arm/plat-omap/cpu-omap.c:43:5: warning: symbol 'omap_verify_speed' was not declared. Should it be static?
      arch/arm/plat-omap/cpu-omap.c:61:14: warning: symbol 'omap_getspeed' was not declared. Should it be static?
      Signed-off-by: NManjunath Kondaiah G <manjugk@ti.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Nishanth Menon <nm@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      b0a330dc
  26. 25 9月, 2010 1 次提交
  27. 24 9月, 2010 2 次提交