1. 30 11月, 2016 1 次提交
    • B
      drm/tilcdc: add a workaround for failed clk_set_rate() · cb42e20e
      Bartosz Golaszewski 提交于
      Some architectures don't use the common clock framework and don't
      implement all the clk interfaces for every clock. This is the case
      for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1.
      
      Trying to set the clock rate for the LCDC clock results in -EINVAL
      being returned.
      
      As a workaround for that: if the call to clk_set_rate() fails, fall
      back to adjusting the clock divider instead. Proper divider value is
      calculated by dividing the current clock rate by the required pixel
      clock rate in HZ.
      
      This code is based on a hack initially developed internally for
      baylibre by Karl Beldan <kbeldan@baylibre.com>.
      
      Tested with a da850-lcdk with an LCD display connected over VGA.
      Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
      Signed-off-by: NJyri Sarha <jsarha@ti.com>
      cb42e20e
  2. 18 10月, 2016 1 次提交
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